1 | ; |
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2 | ; $Id$ |
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3 | ; |
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4 | ;#{ |
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5 | ;# SCCS INFORMATION: |
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6 | ;# SID = @(#)sa29200.lnk 4.1; DLU=95/09/14-11:05:57 |
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7 | ;# Q = @(#) Copyright (C) 1995 Advanced Micro Devices, Inc. |
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8 | ;# Module Type = @(#) OSBOOT/DBG_CORE absolute liker file (AMD-EPD-29K, AMIR) |
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9 | ;# SCCS Path = %P\% |
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10 | ;# SCCS File = %F\% |
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11 | ;# FileName = sa29200.lnk |
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12 | ;# SCCS ID = 4.1 |
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13 | ;# Date Update = 14 Sep 1995, (DLU=95/09/14-11:05:57) |
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14 | ;# Date Extract = 12 Oct 1995, (DLE=95/10/12-16:27:31) |
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15 | ;#} |
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16 | ; @(#)sa29200.lnk 3.6 94/08/22 11:58:54, Srini, AMD. |
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17 | ; This is the linker command file used to bind the inrementally linked |
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18 | ; osboot.o module to a memory map. This also defines some link-time constants |
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19 | ; used in the code. These constants are genral for all 29K family members. |
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20 | ; You only need to customize, if necessary, the definitions that affect |
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21 | ; your target processor, and leave the rest alone. |
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22 | ; The default values in this file are for binding osboot.o for use with |
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23 | ; SA29200 stand-alone board with the -29200/-29205 option. |
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24 | ; |
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25 | ; Order the code segments according to the memory map structure. |
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26 | ; The defaul OSBOOT has only .text and .bss sections. You need to ORDER |
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27 | ; other sections of your applications that are not included below. |
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28 | ; We use separate ORDER statements below to distinguish the two memory |
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29 | ; regions used. The text section is bound to ROM memory region, and the |
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30 | ; data region to RAM memory space. |
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31 | ; MAKE SURE to order the BSS section at the very end. This is because the |
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32 | ; BSS section size could get adjusted after linking with raminit.o (produced |
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33 | ; by romcoff utility) or other initialization routines. This change in size |
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34 | ; could affect the offsets used by the program to refer to the remaining data |
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35 | ; sections that follow BSS. |
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36 | ALIGN ProcInit=16 |
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37 | ORDER Reset=0x0 |
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38 | ORDER ProcInit,OsbText,.text,!text |
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39 | ORDER .lit,!lit |
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40 | ORDER vectable=0x40000000 |
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41 | ORDER msg_data=0x40000400 |
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42 | ORDER .data,!data |
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43 | ORDER OsbBss,dbg_030,dbg_bss,cfg_bss,.bss,!bss |
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44 | ORDER HeapBase |
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45 | ORDER .comment |
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46 | ; For Stand-Alone application out of ROM use the ORDER statements below: |
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47 | ; For Stand-Alone application out of RAM use the ORDER statement below: |
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48 | ;ORDER Reset=0x40010000,ProcInit,OsbText,.text,!text,.lit,!lit,.data,!data,msg_data,dbg_dat,.bss,!bss,HeapBase,.comment |
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49 | ; |
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50 | ; definitions of link time constants used in code. |
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51 | ; |
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52 | ; Definition of the initial value of CPS register. |
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53 | ; The value below is for an Am29200 processor. It sets TU, SM,DI, DA,IM fields |
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54 | ; bits in the register. You may modify it to suit your target environment. |
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55 | ; Like, changing the IM field for instance. IM is 0x11 by default enabling |
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56 | ; all INTR[0-3] lines. |
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57 | ;public _init_CPS=0x87F |
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58 | public _init_CPS=0x20813 |
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59 | ;public _init_CPS=0x2081F |
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60 | ;public _init_CPS=0x081F |
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61 | ; Define the memory map in general values. The code - except for simulators - |
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62 | ; configures the external RAM at run-time and updates the DMemSize value. |
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63 | ; DMemStart and DMemSize are the most important values below. DMemStart is |
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64 | ; used to initialize the vector base address register (VAB). And DMemSize |
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65 | ; is used to find the highest addressable data memory to place the register |
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66 | ; and memory stacks. Remember, DMemSize is configured at run-time for hardware |
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67 | ; targets and updated. |
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68 | public VectorBaseAddress=0x40000000 |
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69 | public IMemStart=0x0000000 |
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70 | public IMemSize=0xfffff |
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71 | public DMemStart=0x40000000 |
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72 | #public DMemStart=0x100000 |
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73 | public DMemSize=0xfffff |
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74 | #public DMemSize=0x17ffff |
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75 | #public DMemSize=0x3fffffff |
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76 | public RMemStart=0x0 |
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77 | public RMemSize=0xfffff |
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78 | public EnableDRAMSizing=1 |
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79 | ; |
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80 | ; For the 29K Microcontrollers, you need to define the ROM Control register |
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81 | ; value (RMCT_VALUE), the ROM Configuration register value (RMCF_VALUE), and |
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82 | ; the DRAM Control register value (DRCT_VALUE) based on DMemSize specified |
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83 | ; above. This could be overwritten in software targets such as the simulator. |
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84 | ; ROM and RAM Control registers. ROM COnfiguration. (not valid for Am2900X, |
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85 | ; Am29050, and Am2903X processors) |
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86 | ; The DRAM REFRATE value (in DRCT) must be specified here. To disable |
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87 | ; DRAM refreshing (on a system with no DRAM), set REFRATE field in DRCT |
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88 | ; to zero. Otherwise, set it to the desired frequency. The default is 0xFF |
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89 | ; The default values in this file are for Am2920X processors. |
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90 | ;public RMCT_VALUE=0x03030303 |
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91 | ;public DRCT_VALUE=0x888800FF |
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92 | ;public RMCF_VALUE=0x00f8f8f8 |
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93 | ; |
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94 | public RMCT_VALUE=0x4a424300 |
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95 | public DRCT_VALUE=0xccc000f0 |
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96 | public RMCF_VALUE=0x011121ff |
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97 | ; |
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98 | ; |
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99 | ; Execute trap handlers from ROM? If your trap handlers are in ROM space, |
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100 | ; then set _TRAPINROM to TWO (0x2). It is used to modify the tarp vector |
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101 | ; address installed to set the R bit when fetched. If the trap handlers in |
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102 | ; ROM or if there is no ROM-space (no RE bit in CPS), set _TRAPINROM to ZERO. |
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103 | ; The default in this file is for SA29200 board and _TRAPINROM is set to ZERO. |
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104 | public _TRAPINROM=0 |
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105 | ; |
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106 | ; Define the processor clock frequencies. These values are used by the HIF |
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107 | ; kernel to provide some HIF services. |
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108 | public TicksPerMillisecond=16000 |
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109 | public ClockFrequency=16000000 |
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110 | ; |
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111 | ; There are some C functions which are not leaf functions. However, they are |
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112 | ; no expected to spill or fill registers. We ensure that by setting up a |
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113 | ; pseudo register stack before calling those functions. The code generated |
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114 | ; for those functions however do have the prologue and epilogue which refer |
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115 | ; to the symbols V_SPILL and V_FILL. The linker does not know about these |
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116 | ; symbols. So we define it here so that it does not complain. |
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117 | ; If you use the hc29 compiler driver to link the objects it will warn that |
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118 | ; the definitions here are already internally defined. You |
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119 | ; can use hc29 with -nocrt0 option to do the linking for linear memory spaces. |
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120 | ; public V_SPILL=64 |
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121 | ; public V_FILL=65 |
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122 | ; |
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123 | ; Set the UART debug/monitor port serial communications baud rate. |
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124 | ; |
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125 | public UCLK=32000000 |
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126 | ; INITBAUD defines the cold start baud rate. This is the baud rate |
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127 | ; the monitor would use when powered up. This can be overridden by |
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128 | ; defining BAUDRATE on the assembler/compiler command line. |
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129 | public INITBAUD=9600 |
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130 | ; |
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131 | ; Is there a SCC 8530 on the target? |
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132 | ; If there is an 8530 SC on target, define the symbols below appropriately. |
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133 | ; The routines in scc8530.s use these values to access the registers of |
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134 | ; SCC and program it. The default values are for EZ030 target. |
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135 | ; Baudrate can be specified on the command-line to override the default |
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136 | ; baud rate defined in scc8530.s. |
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137 | ; scc channel A control |
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138 | ;public SCC8530_CHA_CONTROL=0xC0000007 |
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139 | ; scc channel B control |
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140 | ;public SCC8530_CHB_CONTROL=0xC0000003 |
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141 | ; scc channel A data |
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142 | ;public SCC8530_CHA_DATA=0xC000000F |
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143 | ; scc channel B data |
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144 | ;public SCC8530_CHB_DATA=0xC000000B |
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145 | ; scc baud clock generator |
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146 | ;public SCC8530_BAUD_CLK_ENBL=3 |
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