source: rtems/c/src/lib/libbsp/a29k/portsw/startup/romlink @ 0836603
Last change on this file since 0836603 was 0836603, checked in by Joel Sherrill <joel.sherrill@…>, on 09/18/96 at 21:13:10

new files submitted by Craig Lebakken (lebakken@…) and Derrick Ostertag

  • Property mode set to 100644
File size: 6.4 KB
2;  $Id$
6;# SID          = @(#)sa29200.lnk       4.1;    DLU=95/09/14-11:05:57
7;# Q            = @(#)  Copyright (C) 1995 Advanced Micro Devices, Inc.
8;# Module Type  = @(#)  OSBOOT/DBG_CORE absolute liker file (AMD-EPD-29K, AMIR)
9;# SCCS Path    = %P\%
10;# SCCS File    = %F\%
11;# FileName     = sa29200.lnk
12;# SCCS ID      = 4.1
13;# Date Update  = 14 Sep 1995, (DLU=95/09/14-11:05:57)
14;# Date Extract = 12 Oct 1995, (DLE=95/10/12-16:27:31)
16; @(#)sa29200.lnk       3.6 94/08/22 11:58:54, Srini, AMD.
17; This is the linker command file used to bind the inrementally linked
18; osboot.o module to a memory map. This also defines some link-time constants
19; used in the code. These constants are genral for all 29K family members.
20; You only need to customize, if necessary, the definitions that affect
21; your target processor, and leave the rest alone.
22; The default values in this file are for binding osboot.o for use with
23; SA29200 stand-alone board with the -29200/-29205 option.
25; Order the code segments according to the memory map structure.
26; The defaul OSBOOT has only .text and .bss sections. You need to ORDER
27; other sections of your applications that are not included below.
28; We use separate ORDER statements below to distinguish the two memory
29; regions used. The text section is bound to ROM memory region, and the
30; data region to RAM memory space.
31; MAKE SURE to order the BSS section at the very end. This is because the
32; BSS section size could get adjusted after linking with raminit.o (produced
33; by romcoff utility) or other initialization routines. This change in size
34; could affect the offsets used by the program to refer to the remaining data
35; sections that follow BSS.
36ALIGN   ProcInit=16
37ORDER   Reset=0x0
38ORDER   ProcInit,OsbText,.text,!text
39ORDER   .lit,!lit
40ORDER   vectable=0x40000000
41ORDER   msg_data=0x40000400
42ORDER   .data,!data
43ORDER   OsbBss,dbg_030,dbg_bss,cfg_bss,.bss,!bss
44ORDER   HeapBase
45ORDER   .comment
46; For Stand-Alone application out of ROM use the ORDER statements below:
47; For Stand-Alone application out of RAM use the ORDER statement below:
48;ORDER  Reset=0x40010000,ProcInit,OsbText,.text,!text,.lit,!lit,.data,!data,msg_data,dbg_dat,.bss,!bss,HeapBase,.comment
50; definitions of link time constants used in code.
52; Definition of the initial value of CPS register.
53; The value below is for an Am29200 processor. It sets TU, SM,DI, DA,IM fields
54; bits in the register. You may modify it to suit your target environment.
55; Like, changing the IM field for instance. IM is 0x11 by default enabling
56; all INTR[0-3] lines.
57;public _init_CPS=0x87F
58public  _init_CPS=0x20813
59;public  _init_CPS=0x2081F
60;public  _init_CPS=0x081F
61; Define the memory map in general values. The code - except for simulators -
62; configures the external RAM at run-time and updates the DMemSize value.
63; DMemStart and DMemSize are the most important values below. DMemStart is
64; used to initialize the vector base address register (VAB). And DMemSize
65; is used to find the highest addressable data memory to place the register
66; and memory stacks. Remember, DMemSize is configured at run-time for hardware
67; targets and updated.
68public  VectorBaseAddress=0x40000000
69public  IMemStart=0x0000000
70public  IMemSize=0xfffff
71public  DMemStart=0x40000000
72#public DMemStart=0x100000
73public  DMemSize=0xfffff
74#public DMemSize=0x17ffff
75#public DMemSize=0x3fffffff
76public  RMemStart=0x0
77public  RMemSize=0xfffff
78public  EnableDRAMSizing=1
80; For the 29K Microcontrollers, you need to define the ROM Control register
81; value (RMCT_VALUE), the ROM Configuration register value (RMCF_VALUE), and
82; the DRAM Control register value (DRCT_VALUE) based on DMemSize specified
83; above. This could be overwritten in software targets such as the simulator.
84; ROM and RAM Control registers. ROM COnfiguration. (not valid for Am2900X,
85; Am29050, and Am2903X processors)
86; The DRAM REFRATE value (in DRCT) must be specified here. To disable
87; DRAM refreshing (on a system with no DRAM), set REFRATE field in DRCT
88; to zero. Otherwise, set it to the desired frequency. The default is 0xFF
89; The default values in this file are for Am2920X processors.
90;public RMCT_VALUE=0x03030303
91;public DRCT_VALUE=0x888800FF
92;public RMCF_VALUE=0x00f8f8f8
94public  RMCT_VALUE=0x4a424300
95public  DRCT_VALUE=0xccc000f0
96public  RMCF_VALUE=0x011121ff
99; Execute trap handlers from ROM? If your trap handlers are in ROM space,
100; then set _TRAPINROM to TWO (0x2). It is used to modify the tarp vector
101; address installed to set the R bit when fetched. If the trap handlers in
102; ROM or if there is no ROM-space (no RE bit in CPS), set _TRAPINROM to ZERO.
103; The default in this file is for SA29200 board and _TRAPINROM is set to ZERO.
104public  _TRAPINROM=0
106; Define the processor clock frequencies. These values are used by the HIF
107; kernel to provide some HIF services.
108public  TicksPerMillisecond=16000
109public  ClockFrequency=16000000
111; There are some C functions which are not leaf functions. However, they are
112; no expected to spill or fill registers. We ensure that by setting up a
113; pseudo register stack before calling those functions. The code generated
114; for those functions however do have the prologue and epilogue which refer
115; to the symbols V_SPILL and V_FILL. The linker does not know about these
116; symbols. So we define it here so that it does not complain.
117; If you use the hc29 compiler driver to link the objects it will warn that
118; the definitions here are already internally defined. You
119; can use hc29 with -nocrt0 option to do the linking for linear memory spaces.
120; public        V_SPILL=64
121; public        V_FILL=65
123; Set the UART debug/monitor port serial communications baud rate.
125public UCLK=32000000
126; INITBAUD defines the cold start baud rate. This is the baud rate
127; the monitor would use when powered up. This can be overridden by
128; defining BAUDRATE on the assembler/compiler command line.
129public INITBAUD=9600
131; Is there a SCC 8530 on the target?
132; If there is an 8530 SC on target, define the symbols below appropriately.
133; The routines in scc8530.s use these values to access the registers of
134; SCC and program it. The default values are for EZ030 target.
135; Baudrate can be specified on the command-line to override the default
136; baud rate defined in scc8530.s.
137; scc channel A control
138;public SCC8530_CHA_CONTROL=0xC0000007
139; scc channel B control
140;public SCC8530_CHB_CONTROL=0xC0000003
141; scc channel A data
142;public SCC8530_CHA_DATA=0xC000000F
143; scc channel B data
144;public SCC8530_CHB_DATA=0xC000000B
145; scc baud clock generator
146;public SCC8530_BAUD_CLK_ENBL=3
Note: See TracBrowser for help on using the repository browser.