source: rtems/c/src/lib/include/zilog/z8036.h @ 4e36a2f

4.104.114.84.95
Last change on this file since 4e36a2f was 08311cc3, checked in by Joel Sherrill <joel.sherrill@…>, on 11/17/99 at 17:51:34

Updated copyright notice.

  • Property mode set to 100644
File size: 4.8 KB
Line 
1/*  z8036.h
2 *
3 *  This include file defines information related to a Zilog Z8036
4 *  Counter/Timer/IO Chip.  It is a memory mapped part.
5 *
6 *  Input parameters:  NONE
7 *
8 *  Output parameters:  NONE
9 *
10 *  NOTE: This file shares as much as possible with the include
11 *        file for the Z8536 via z8x36.h.
12 *
13 *  COPYRIGHT (c) 1989-1999.
14 *  On-Line Applications Research Corporation (OAR).
15 *
16 *  The license and distribution terms for this file may be
17 *  found in the file LICENSE in this distribution or at
18 *  http://www.OARcorp.com/rtems/license.html.
19 *
20 *  $Id$
21 */
22
23#ifndef __Z8036_h
24#define __Z8036_h
25
26#ifdef __cplusplus
27extern "C" {
28#endif
29
30/* macros */
31
32#define Z8036( ptr ) ((volatile struct z8036_map *)(ptr))
33
34#define Z8x36_STATE0 ( z8036 ) \
35  { /*char *garbage = *(Z8036(z8036))->???; */ }
36
37
38#define Z8x36_WRITE( z8036, reg, data ) \
39   (Z8036(z8036))->reg = (data)
40
41
42#define Z8x36_READ( z8036, reg, data ) \
43   (Z8036(z8036))->reg = (data)
44
45/* structures */
46
47struct z8036_map {
48/* MAIN CONTROL REGISTERS (0x00-0x07) */
49  rtems_unsigned8 MASTER_INTR;           /* Master Interrupt Ctl Reg */
50  rtems_unsigned8 MASTER_CFG;            /* Master Configuration Ctl Reg */
51  rtems_unsigned8 PORTA_VECTOR;          /* Port A - Interrupt Vector */
52  rtems_unsigned8 PORTB_VECTOR;          /* Port B - Interrupt Vector */
53  rtems_unsigned8 CNT_TMR_VECTOR;        /* Counter/Timer Interrupt Vector */
54  rtems_unsigned8 PORTC_DATA_POLARITY;   /* Port C - Data Path Polarity */
55  rtems_unsigned8 PORTC_DIRECTION;       /* Port C - Data Direction */
56  rtems_unsigned8 PORTC_SPECIAL_IO_CTL;  /* Port C - Special IO Control */
57/* MOST OFTEN ACCESSED REGISTERS (0x08 - 0x0f) */
58  rtems_unsigned8 PORTA_CMD_STATUS;      /* Port A - Command Status Reg */
59  rtems_unsigned8 PORTB_CMD_STATUS;      /* Port B - Command Status Reg */
60  rtems_unsigned8 CT1_CMD_STATUS;        /* Ctr/Timer 1 - Command Status Reg */
61  rtems_unsigned8 CT2_CMD_STATUS;        /* Ctr/Timer 2 - Command Status Reg */
62  rtems_unsigned8 CT3_CMD_STATUS;        /* Ctr/Timer 3 - Command Status Reg */
63  rtems_unsigned8 PORTA_DATA;            /* Port A - Data */
64  rtems_unsigned8 PORTB_DATA;            /* Port B - Data */
65  rtems_unsigned8 PORTC_DATA;            /* Port C - Data */
66/* COUNTER/TIMER RELATED REGISTERS (0x10-0x1f) */
67  rtems_unsigned8 CT1_CUR_CNT_MSB;       /* Ctr/Timer 1 - Current Count (MSB) */
68  rtems_unsigned8 CT1_CUR_CNT_LSB;       /* Ctr/Timer 1 - Current Count (LSB) */
69  rtems_unsigned8 CT2_CUR_CNT_MSB;       /* Ctr/Timer 2 - Current Count (MSB) */
70  rtems_unsigned8 CT2_CUR_CNT_LSB;       /* Ctr/Timer 2 - Current Count (LSB) */
71  rtems_unsigned8 CT3_CUR_CNT_MSB;       /* Ctr/Timer 3 - Current Count (MSB) */
72  rtems_unsigned8 CT3_CUR_CNT_LSB;       /* Ctr/Timer 3 - Current Count (LSB) */
73  rtems_unsigned8 CT1_TIME_CONST_MSB;    /* Ctr/Timer 1 - Time Constant (MSB) */
74  rtems_unsigned8 CT1_TIME_CONST_LSB;    /* Ctr/Timer 1 - Time Constant (LSB) */
75  rtems_unsigned8 CT2_TIME_CONST_MSB;    /* Ctr/Timer 2 - Time Constant (MSB) */
76  rtems_unsigned8 CT2_TIME_CONST_LSB;    /* Ctr/Timer 2 - Time Constant (LSB) */
77  rtems_unsigned8 CT3_TIME_CONST_MSB;    /* Ctr/Timer 3 - Time Constant (MSB) */
78  rtems_unsigned8 CT3_TIME_CONST_LSB;    /* Ctr/Timer 3 - Time Constant (LSB) */
79  rtems_unsigned8 CT1_MODE_SPEC;         /* Ctr/Timer 1 - Mode Specification  */
80  rtems_unsigned8 CT2_MODE_SPEC;         /* Ctr/Timer 2 - Mode Specification  */
81  rtems_unsigned8 CT3_MODE_SPEC;         /* Ctr/Timer 3 - Mode Specification  */
82  rtems_unsigned8 CURRENT_VECTOR;        /* Current Vector */
83/* PORT A SPECIFICATION REGISTERS (0x20 -0x27) */
84  rtems_unsigned8 PORTA_MODE;            /* Port A - Mode Specification  */
85  rtems_unsigned8 PORTA_HANDSHAKE;       /* Port A - Handshake Specification  */
86  rtems_unsigned8 PORTA_DATA_POLARITY;   /* Port A - Data Path Polarity */
87  rtems_unsigned8 PORTA_DIRECTION;       /* Port A - Data Direction */
88  rtems_unsigned8 PORTA_SPECIAL_IO_CTL;  /* Port A - Special IO Control */
89  rtems_unsigned8 PORTA_PATT_POLARITY;   /* Port A - Pattern Polarity */
90  rtems_unsigned8 PORTA_PATT_TRANS;      /* Port A - Pattern Transition */
91  rtems_unsigned8 PORTA_PATT_MASK;       /* Port A - Pattern Mask */
92/* PORT B SPECIFICATION REGISTERS (0x28-0x2f) */
93  rtems_unsigned8 PORTB_MODE;            /* Port B - Mode Specification  */
94  rtems_unsigned8 PORTB_HANDSHAKE;       /* Port B - Handshake Specification  */
95  rtems_unsigned8 PORTB_DATA_POLARITY;   /* Port B - Data Path Polarity */
96  rtems_unsigned8 PORTB_DIRECTION;       /* Port B - Data Direction */
97  rtems_unsigned8 PORTB_SPECIAL_IO_CTL;  /* Port B - Special IO Control */
98  rtems_unsigned8 PORTB_PATT_POLARITY;   /* Port B - Pattern Polarity */
99  rtems_unsigned8 PORTB_PATT_TRANS;      /* Port B - Pattern Transition */
100  rtems_unsigned8 PORTB_PATT_MASK;       /* Port B - Pattern Mask */
101};
102
103#ifdef __cplusplus
104}
105#endif
106
107#endif
108
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