1 | /* |
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2 | * mc68681-duart.h -- Low level support code for the Motorola mc68681 |
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3 | * DUART. |
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4 | * |
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5 | * Originally written by rob@cygnus.com (Rob Savoye) for the libgloss |
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6 | * IDP support. |
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7 | * |
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8 | * $Id$ |
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9 | */ |
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10 | |
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11 | #ifndef __MC68681_H__ |
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12 | #define __MC68681_H__ |
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13 | |
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14 | /* |
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15 | * In the dark ages when this controller was designed, it was actually |
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16 | * possible to access data on unaligned byte boundaries with no penalty. |
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17 | * Now we find this chip in configurations in which the registers are |
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18 | * at 16-bit, 32-bit, and 64-bit boundaries at the whim of the board |
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19 | * designer. If the registers are not at byte addresses, then |
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20 | * set this multiplier before including this file to correct the offsets. |
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21 | */ |
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22 | |
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23 | #ifndef MC68681_OFFSET_MULTIPLIER |
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24 | #define MC68681_OFFSET_MULTIPLIER 1 |
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25 | #endif |
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26 | |
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27 | #define __MC68681_REG(_R) ((_R) * MC68681_OFFSET_MULTIPLIER) |
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28 | |
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29 | /* |
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30 | * mc68681 register offsets Read/Write Addresses |
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31 | */ |
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32 | #define MC68681_MODE_REG_1A __MC68681_REG(0) /* MR1A-MR Prior to Read */ |
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33 | #define MC68681_MODE_REG_2A __MC68681_REG(0) /* MR2A-MR After Read */ |
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34 | |
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35 | #define MC68681_COUNT_MODE_CURRENT_MSB __MC68681_REG(6) /* CTU */ |
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36 | #define MC68681_COUNTER_TIMER_UPPER_REG __MC68681_REG(6) /* CTU */ |
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37 | #define MC68681_COUNT_MODE_CURRENT_LSB __MC68681_REG(7) /* CTL */ |
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38 | #define MC68681_COUNTER_TIMER_LOWER_REG __MC68681_REG(7) /* CTL */ |
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39 | #define MC68681_INTERRUPT_VECTOR_REG __MC68681_REG(12) /* IVR */ |
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40 | |
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41 | #define MC68681_MODE_REG_1B __MC68681_REG(8) /* MR1B-MR Prior to Read */ |
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42 | #define MC68681_MODE_REG_2B __MC68681_REG(8) /* MR2BA-MR After Read */ |
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43 | |
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44 | /* |
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45 | * mc68681 register offsets Read Only Addresses |
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46 | */ |
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47 | #define MC68681_STATUS_REG_A __MC68681_REG(1) /* SRA */ |
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48 | #define MC68681_MASK_ISR_REG __MC68681_REG(2) /* MISR */ |
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49 | #define MC68681_RECEIVE_BUFFER_A __MC68681_REG(3) /* RHRA */ |
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50 | #define MC68681_INPUT_PORT_CHANGE_REG __MC68681_REG(4) /* IPCR */ |
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51 | #define MC68681_INTERRUPT_STATUS_REG __MC68681_REG(5) /* ISR */ |
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52 | #define MC68681_STATUS_REG_B __MC68681_REG(9) /* SRB */ |
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53 | #define MC68681_RECEIVE_BUFFER_B __MC68681_REG(11) /* RHRB */ |
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54 | #define MC68681_INPUT_PORT __MC68681_REG(13) /* IP */ |
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55 | #define MC68681_START_COUNT_CMD __MC68681_REG(14) /* SCC */ |
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56 | #define MC68681_STOP_COUNT_CMD __MC68681_REG(15) /* STC */ |
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57 | |
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58 | /* |
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59 | * mc68681 register offsets Write Only Addresses |
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60 | */ |
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61 | #define MC68681_CLOCK_SELECT_REG_A __MC68681_REG(1) /* CSRA */ |
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62 | #define MC68681_COMMAND_REG_A __MC68681_REG(2) /* CRA */ |
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63 | #define MC68681_TRANSMIT_BUFFER_A __MC68681_REG(3) /* THRA */ |
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64 | #define MC68681_AUX_CTRL_REG __MC68681_REG(4) /* ACR */ |
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65 | #define MC68681_INTERRUPT_MASK_REG __MC68681_REG(5) /* IMR */ |
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66 | #define MC68681_CLOCK_SELECT_REG_B __MC68681_REG(9) /* CSRB */ |
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67 | #define MC68681_COMMAND_REG_B __MC68681_REG(10) /* CRB */ |
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68 | #define MC68681_TRANSMIT_BUFFER_B __MC68681_REG(11) /* THRB */ |
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69 | #define MC68681_OUTPUT_PORT_CONFIG_REG __MC68681_REG(13) /* OPCR */ |
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70 | #define MC68681_OUTPUT_PORT_SET_REG __MC68681_REG(14) /* SOPBC */ |
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71 | #define MC68681_OUTPUT_PORT_RESET_BITS __MC68681_REG(15) /* COPBC */ |
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72 | |
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73 | |
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74 | #ifndef MC6681_VOL |
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75 | #define MC6681_VOL( ptr ) ((volatile unsigned char *)(ptr)) |
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76 | #endif |
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77 | |
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78 | #define MC68681_WRITE( _base, _reg, _data ) \ |
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79 | *((volatile unsigned char *)_base+_reg) = (_data) |
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80 | |
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81 | #define MC68681_READ( _base, _reg ) \ |
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82 | *(((volatile unsigned char *)_base+_reg)) |
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83 | |
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84 | |
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85 | |
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86 | #define MC68681_CLEAR 0x00 |
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87 | |
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88 | #define MC68681_PORT_A 0 |
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89 | #define MC68681_PORT_B 1 |
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90 | |
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91 | /* |
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92 | * DUART Command Register Definitions: |
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93 | * |
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94 | * MC68681_COMMAND_REG_A,MC68681_COMMAND_REG_B |
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95 | */ |
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96 | #define MC68681_MODE_REG_ENABLE_RX 0x01 |
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97 | #define MC68681_MODE_REG_DISABLE_RX 0x02 |
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98 | #define MC68681_MODE_REG_ENABLE_TX 0x04 |
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99 | #define MC68681_MODE_REG_DISABLE_TX 0x08 |
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100 | #define MC68681_MODE_REG_RESET_MR_PTR 0x10 |
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101 | #define MC68681_MODE_REG_RESET_RX 0x20 |
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102 | #define MC68681_MODE_REG_RESET_TX 0x30 |
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103 | #define MC68681_MODE_REG_RESET_ERROR 0x40 |
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104 | #define MC68681_MODE_REG_RESET_BREAK 0x50 |
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105 | #define MC68681_MODE_REG_START_BREAK 0x60 |
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106 | #define MC68681_MODE_REG_STOP_BREAK 0x70 |
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107 | #define MC68681_MODE_REG_SET_RX_BRG 0x80 |
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108 | #define MC68681_MODE_REG_CLEAR_RX_BRG 0x90 |
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109 | #define MC68681_MODE_REG_SET_TX_BRG 0xa0 |
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110 | #define MC68681_MODE_REG_CLEAR_TX_BRG 0xb0 |
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111 | #define MC68681_MODE_REG_SET_STANDBY 0xc0 |
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112 | #define MC68681_MODE_REG_SET_ACTIVE 0xd0 |
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113 | |
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114 | /* |
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115 | * Mode Register Definitions |
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116 | * |
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117 | * MC68681_MODE_REG_1A |
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118 | * MC68681_MODE_REG_1B |
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119 | */ |
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120 | #define MC68681_5BIT_CHARS 0x00 |
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121 | #define MC68681_6BIT_CHARS 0x01 |
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122 | #define MC68681_7BIT_CHARS 0x02 |
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123 | #define MC68681_8BIT_CHARS 0x03 |
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124 | |
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125 | #define MC68681_ODD_PARITY 0x00 |
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126 | #define MC68681_EVEN_PARITY 0x04 |
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127 | |
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128 | #define MC68681_WITH_PARITY 0x00 |
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129 | #define MC68681_FORCE_PARITY 0x08 |
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130 | #define MC68681_NO_PARITY 0x10 |
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131 | #define MC68681_MULTI_DROP 0x18 |
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132 | |
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133 | #define MC68681_ERR_MODE_CHAR 0x00 |
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134 | #define MC68681_ERR_MODE_BLOCK 0x20 |
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135 | |
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136 | #define MC68681_RX_INTR_RX_READY 0x00 |
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137 | #define MC68681_RX_INTR_FFULL 0x40 |
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138 | |
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139 | #define MC68681_NO_RX_RTS_CTL 0x00 |
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140 | #define MC68681_RX_RTS_CTRL 0x80 |
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141 | |
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142 | |
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143 | /* |
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144 | * Mode Register Definitions |
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145 | * |
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146 | * MC68681_MODE_REG_2A |
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147 | * MC68681_MODE_REG_2B |
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148 | */ |
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149 | #define MC68681_STOP_BIT_LENGTH__563 0x00 |
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150 | #define MC68681_STOP_BIT_LENGTH__625 0x01 |
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151 | #define MC68681_STOP_BIT_LENGTH__688 0x02 |
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152 | #define MC68681_STOP_BIT_LENGTH__75 0x03 |
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153 | #define MC68681_STOP_BIT_LENGTH__813 0x04 |
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154 | #define MC68681_STOP_BIT_LENGTH__875 0x05 |
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155 | #define MC68681_STOP_BIT_LENGTH__938 0x06 |
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156 | #define MC68681_STOP_BIT_LENGTH_1 0x07 |
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157 | #define MC68681_STOP_BIT_LENGTH_1_563 0x08 |
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158 | #define MC68681_STOP_BIT_LENGTH_1_625 0x09 |
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159 | #define MC68681_STOP_BIT_LENGTH_1_688 0x0a |
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160 | #define MC68681_STOP_BIT_LENGTH_1_75 0x0b |
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161 | #define MC68681_STOP_BIT_LENGTH_1_813 0x0c |
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162 | #define MC68681_STOP_BIT_LENGTH_1_875 0x0d |
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163 | #define MC68681_STOP_BIT_LENGTH_1_938 0x0e |
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164 | #define MC68681_STOP_BIT_LENGTH_2 0x0f |
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165 | |
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166 | #define MC68681_CTS_ENABLE_TX 0x10 |
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167 | #define MC68681_TX_RTS_CTRL 0x20 |
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168 | |
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169 | #define MC68681_CHANNEL_MODE_NORMAL 0x00 |
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170 | #define MC68681_CHANNEL_MODE_ECHO 0x40 |
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171 | #define MC68681_CHANNEL_MODE_LOCAL_LOOP 0x80 |
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172 | #define MC68681_CHANNEL_MODE_REMOTE_LOOP 0xc0 |
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173 | |
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174 | /* |
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175 | * Status Register Definitions |
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176 | * |
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177 | * MC68681_STATUS_REG_A, MC68681_STATUS_REG_B |
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178 | */ |
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179 | #define MC68681_RX_READY 0x01 |
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180 | #define MC68681_FFULL 0x02 |
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181 | #define MC68681_TX_READY 0x04 |
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182 | #define MC68681_TX_EMPTY 0x08 |
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183 | #define MC68681_OVERRUN_ERROR 0x10 |
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184 | #define MC68681_PARITY_ERROR 0x20 |
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185 | #define MC68681_FRAMING_ERROR 0x40 |
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186 | #define MC68681_RECEIVED_BREAK 0x80 |
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187 | |
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188 | |
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189 | /* |
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190 | * Interupt Status Register Definitions. |
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191 | * |
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192 | * MC68681_INTERRUPT_STATUS_REG |
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193 | */ |
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194 | |
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195 | |
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196 | /* |
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197 | * Interupt Mask Register Definitions |
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198 | * |
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199 | * MC68681_INTERRUPT_MASK_REG |
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200 | */ |
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201 | #define MC68681_IR_TX_READY_A 0x01 |
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202 | #define MC68681_IR_RX_READY_A 0x02 |
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203 | #define MC68681_IR_BREAK_A 0x04 |
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204 | #define MC68681_IR_COUNTER_READY 0x08 |
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205 | #define MC68681_IR_TX_READY_B 0x10 |
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206 | #define MC68681_IR_RX_READY_B 0x20 |
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207 | #define MC68681_IR_BREAK_B 0x40 |
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208 | #define MC68681_IR_INPUT_PORT_CHANGE 0x80 |
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209 | |
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210 | /* |
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211 | * Status Register Definitions. |
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212 | * |
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213 | * MC68681_STATUS_REG_A,MC68681_STATUS_REG_B |
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214 | */ |
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215 | #define MC68681_STATUS_RXRDY 0x01 |
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216 | #define MC68681_STATUS_FFULL 0x02 |
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217 | #define MC68681_STATUS_TXRDY 0x04 |
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218 | #define MC68681_STATUS_TXEMT 0x08 |
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219 | #define MC68681_STATUS_OVERRUN_ERROR 0x10 |
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220 | #define MC68681_STATUS_PARITY_ERROR 0x20 |
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221 | #define MC68681_STATUS_FRAMING_ERROR 0x40 |
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222 | #define MC68681_STATUS_RECEIVED_BREAK 0x80 |
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223 | |
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224 | /* |
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225 | * Definitions for the Interrupt Vector Register: |
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226 | * |
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227 | * MC68681_INTERRUPT_VECTOR_REG |
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228 | */ |
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229 | #define MC68681_INTERRUPT_VECTOR_INIT 0x0f |
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230 | |
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231 | /* |
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232 | * Definitions for the Auxiliary Control Register |
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233 | * |
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234 | * MC68681_AUX_CTRL_REG |
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235 | */ |
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236 | #define MC68681_AUX_BRG_SET1 0x00 |
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237 | #define MC68681_AUX_BRG_SET2 0x80 |
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238 | |
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239 | |
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240 | /* |
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241 | * The following Baud rates assume the X1 clock pin is driven with a |
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242 | * 3.6864 MHz signal. If a different frequency is used the DUART channel |
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243 | * is running at the follwoing baud rate: |
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244 | * ((Table Baud Rate)*frequency)/3.6864 MHz |
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245 | */ |
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246 | |
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247 | /* |
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248 | * Definitions for the Clock Select Register: |
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249 | * |
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250 | * MC68681_CLOCK_SELECT_REG_A,MC68681_CLOCK_SELECT_REG_A |
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251 | * |
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252 | * Note: ACR[7] is the MSB of the Auxiliary Control register |
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253 | * X is the extend bit. |
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254 | * CRA - 0x08 Set Rx BRG Select Extend Bit (X=1) |
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255 | * CRA - 0x09 Clear Rx BRG Select Extend Bit (X=0) |
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256 | * CRB - 0x0a Set Tx BRG Select Extend Bit (X=1) |
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257 | * CRB - 0x0b Clear Tx BRG Select Extend Bit (x=1) |
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258 | */ |
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259 | #define MC68681_BAUD_RATE_MASK_50 0x00 /* ACR[7]=0,X=0 */ |
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260 | /* ARC[7]=1,X=1 */ |
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261 | #define MC68681_BAUD_RATE_MASK_75 0x00 /* ACR[7]=0,X=0 */ |
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262 | /* ARC[7]=1,X=1 */ |
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263 | #define MC68681_BAUD_RATE_MASK_110 0x01 |
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264 | #define MC68681_BAUD_RATE_MASK_134_5 0x02 |
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265 | #define MC68681_BAUD_RATE_MASK_150 0x03 /* ACR[7]=0,X=0 */ |
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266 | /* ARC[7]=1,X=1 */ |
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267 | #define MC68681_BAUD_RATE_MASK_200 0x03 /* ACR[7]=0,X=0 */ |
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268 | /* ARC[7]=1,X=1 */ |
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269 | #define MC68681_BAUD_RATE_MASK_300 0x04 /* ACR[7]=0,X=0 */ |
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270 | /* ARC[7]=1,X=1 */ |
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271 | #define MC68681_BAUD_RATE_MASK_600 0x05 /* ACR[7]=0,X=0 */ |
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272 | /* ARC[7]=1,X=1 */ |
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273 | #define MC68681_BAUD_RATE_MASK_1050 0x07 /* ACR[7]=0,X=0 */ |
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274 | /* ARC[7]=1,X=1 */ |
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275 | #define MC68681_BAUD_RATE_MASK_1200 0x06 /* ACR[7]=0,X=0 */ |
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276 | /* ARC[7]=1,X=1 */ |
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277 | #define MC68681_BAUD_RATE_MASK_1800 0x0a /* ACR[7]=0,X=0 */ |
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278 | /* ARC[7]=1,X=1 */ |
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279 | #define MC68681_BAUD_RATE_MASK_2400 0x08 /* ACR[7]=0,X=0 */ |
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280 | /* ARC[7]=1,X=1 */ |
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281 | #define MC68681_BAUD_RATE_MASK_3600 0x04 /* ACR[7]=0,X=0 */ |
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282 | /* ARC[7]=1,X=1 */ |
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283 | #define MC68681_BAUD_RATE_MASK_4800 0x09 |
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284 | #define MC68681_BAUD_RATE_MASK_7200 0x0a /* ACR[7]=0,X=0 */ |
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285 | /* ARC[7]=1,X=1 */ |
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286 | #define MC68681_BAUD_RATE_MASK_9600 0xbb |
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287 | |
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288 | #define MC68681_BAUD_RATE_MASK_14_4K 0x05 /* ACR[7]=0,X=0 */ |
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289 | /* ARC[7]=1,X=1 */ |
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290 | #define MC68681_BAUD_RATE_MASK_19_2K 0xcc /* ACR[7]=1,X=0 */ |
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291 | /* ARC[7]=0,X=1 */ |
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292 | #define MC68681_BAUD_RATE_MASK_28_8K 0x06 /* ACR[7]=0,X=0 */ |
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293 | /* ARC[7]=1,X=1 */ |
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294 | #define MC68681_BAUD_RATE_MASK_38_4K 0xcc /* ACR[7]=0,X=0 */ |
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295 | /* ARC[7]=1,X=1 */ |
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296 | #define MC68681_BAUD_RATE_MASK_57_6K 0x07 /* ACR[7]=0,X=0 */ |
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297 | /* ARC[7]=1,X=1 */ |
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298 | #define MC68681_BAUD_RATE_MASK_115_5K 0x08 |
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299 | #define MC68681_BAUD_RATE_MASK_TIMER 0xdd |
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300 | #define MC68681_BAUD_RATE_MASK_TIMER_16X 0xee |
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301 | #define MC68681_BAUD_RATE_MASK_TIMER_1X 0xff |
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302 | |
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303 | #endif |
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304 | |
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305 | |
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306 | |
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