1 | /* |
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2 | * mc68681-duart.h -- Low level support code for the Motorola mc68681 |
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3 | * DUART. This one is one the mc68ec0x0 board. |
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4 | * Written by rob@cygnus.com (Rob Savoye) |
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5 | * |
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6 | * $Id$ |
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7 | */ |
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8 | |
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9 | #ifndef __MC68681_H__ |
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10 | #define __MC68681_H__ |
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11 | #define DUART_ADDR 0xb00003 /* base address of the DUART */ |
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12 | |
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13 | /* |
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14 | * mc68681 register offsets |
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15 | */ |
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16 | #define DUART_MR1A 0x00 /* Mode Register A */ |
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17 | #define DUART_MR2A 0x00 /* Mode Register A */ |
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18 | #define DUART_SRA 0x04 /* Status Register A */ |
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19 | #define DUART_CSRA 0x04 /* Clock-Select Register A */ |
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20 | #define DUART_CRA 0x08 /* Command Register A */ |
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21 | #define DUART_RBA 0x0c /* Receive Buffer A */ |
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22 | #define DUART_TBA 0x0c /* Transmit Buffer A */ |
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23 | #define DUART_IPCR 0x10 /* Input Port Change Register */ |
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24 | #define DUART_ACR 0x10 /* Auxiliary Control Register */ |
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25 | #define DUART_ISR 0x14 /* Interrupt Status Register */ |
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26 | #define DUART_IMR 0x14 /* Interrupt Mask Register */ |
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27 | #define DUART_CUR 0x18 /* Counter Mode: current MSB */ |
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28 | #define DUART_CTUR 0x18 /* Counter/Timer upper reg */ |
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29 | #define DUART_CLR 0x1c /* Counter Mode: current LSB */ |
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30 | #define DUART_CTLR 0x1c /* Counter/Timer lower reg */ |
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31 | #define DUART_MR1B 0x20 /* Mode Register B */ |
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32 | #define DUART_MR2B 0x20 /* Mode Register B */ |
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33 | #define DUART_SRB 0x24 /* Status Register B */ |
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34 | #define DUART_CSRB 0x24 /* Clock-Select Register B */ |
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35 | #define DUART_CRB 0x28 /* Command Register B */ |
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36 | #define DUART_RBB 0x2c /* Receive Buffer B */ |
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37 | #define DUART_TBB 0x2c /* Transmit Buffer A */ |
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38 | #define DUART_IVR 0x30 /* Interrupt Vector Register */ |
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39 | #define DUART_IP 0x34 /* Input Port */ |
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40 | #define DUART_OPCR 0x34 /* Output Port Configuration Reg. */ |
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41 | #define DUART_STRTCC 0x38 /* Start-Counter command */ |
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42 | #define DUART_OPRSET 0x38 /* Output Port Reg, SET bits */ |
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43 | #define DUART_STOPCC 0x3c /* Stop-Counter command */ |
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44 | #define DUART_OPRRST 0x3c /* Output Port Reg, ReSeT bits */ |
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45 | |
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46 | /* this is just if you want a copy of the chip's registers */ |
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47 | struct duart_regs { |
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48 | unsigned char mr1a_reg; /* Mode Register A */ |
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49 | unsigned char mr2a_reg; /* Mode Register A */ |
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50 | unsigned char sra_reg; /* Status Register A */ |
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51 | unsigned char csra_reg; /* Clock-Select Register A */ |
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52 | unsigned char cra_reg; /* Command Register A */ |
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53 | unsigned char ipcr_reg; /* Input Port Change Register */ |
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54 | unsigned char acr_reg; /* Auxiliary Control Register */ |
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55 | unsigned char isr_reg; /* Interrupt Status Register */ |
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56 | unsigned char imr_reg; /* Interrupt Mask Register */ |
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57 | unsigned char cur_reg; /* Counter Mode: current MSB */ |
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58 | unsigned char ctur_reg; /* Counter/Timer upper reg */ |
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59 | unsigned char clr_reg; /* Counter Mode: current LSB */ |
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60 | unsigned char ctlr_reg; /* Counter/Timer lower reg */ |
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61 | unsigned char mr1b_reg; /* Mode Register B */ |
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62 | unsigned char mr2b_reg; /* Mode Register B */ |
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63 | unsigned char srb_reg; /* Status Register B */ |
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64 | unsigned char csrb_reg; /* Clock-Select Register B */ |
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65 | unsigned char crb_reg; /* Command Register B */ |
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66 | unsigned char ivr_reg; /* Interrupt Vector Register */ |
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67 | unsigned char ip_reg; /* Input Port */ |
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68 | unsigned char opcr_reg; /* Output Port Configuration Reg. */ |
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69 | unsigned char oprset_reg; /* Output Port Reg; bit SET */ |
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70 | unsigned char strtcc_reg; /* Start-Counter command */ |
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71 | unsigned char oprrst_reg; /* Output Port Reg; bit ReSeT */ |
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72 | unsigned char stopcc_reg; /* Stop-Counter command */ |
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73 | unsigned char pad; |
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74 | }; |
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75 | |
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76 | /* Some RTEMS style defines: */ |
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77 | #ifndef VOL8 |
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78 | #define VOL8( ptr ) ((volatile rtems_unsigned8 *)(ptr)) |
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79 | #endif |
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80 | |
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81 | #define MC68681_WRITE( reg, data ) \ |
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82 | *(VOL8(DUART_ADDR+reg)) = (data) |
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83 | |
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84 | #define MC68681_READ( reg, data ) \ |
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85 | (data) = *(VOL8(DUART_ADDR+reg)) |
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86 | |
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87 | #endif |
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