source: rtems/c/src/exec/score/include/rtems/score/thread.h @ ba46ffa6

4.104.114.84.95
Last change on this file since ba46ffa6 was ba46ffa6, checked in by Joel Sherrill <joel.sherrill@…>, on 06/14/99 at 16:51:13

This is a large patch from Eric Valette <valette@…> that was
described in the message following this paragraph. This patch also includes
a mcp750 BSP.

From valette@… Mon Jun 14 10:03:08 1999
Date: Tue, 18 May 1999 01:30:14 +0200 (CEST)
From: VALETTE Eric <valette@…>
To: joel@…
Cc: raguet@…, rtems-snapshots@…, valette@…
Subject: Questions/Suggestion? regarding RTEMS PowerPC code (long)

Dear knowledgeable RTEMS powerpc users,

As some of you may know, I'm currently finalizing a port
of RTEMS on a MCP750 Motorola board. I have done most
of it but have some questions to ask before submitting
the port.

In order to understand some of the changes I have made
or would like to make, maybe it is worth describing the
MCP750 Motorola board.

the MCP750 is a COMPACT PCI powerpc board with :

1) a MPC750 233 MHz processor,
2) a raven bus bridge/PCI controller that
implement an OPENPIC compliant interrupt controller,
3) a VIA 82C586 PCI/ISA bridge that offers a PC
compliant IO for keyboard, serial line, IDE, and
the well known PC 8259 cascaded PIC interrupt
architecture model,
4) a DEC 21140 Ethernet controller,
5) the PPCBUG Motorola firmware in flash,
6) A DEC PCI bridge,

This architecture is common to most Motorola 60x/7xx
board except that :

1) on VME board, the DEC PCI bridge is replaced by
a VME chipset,
2) the VIA 82C586 PCI/ISA bridge is replaced by
another bridge that is almost fully compatible
with the via bridge...

So the port should be a rather close basis for many
60x/7xx motorola board...

On this board, I already have ported Linux 2.2.3 and
use it both as a development and target board.

Now the questions/suggestions I have :

1) EXCEPTION CODE


As far as I know exceptions on PPC are handled like
interrupts. I dislike this very much as :

a) Except for the decrementer exception (and
maybe some other on mpc8xx), exceptions are
not recoverable and the handler just need to print
the full context and go to the firmware or debugger...
b) The interrupt switch is only necessary for the
decrementer and external interrupt (at least on
6xx,7xx).
c) The full context for exception is never saved and
thus cannot be used by debugger... I do understand
the most important for interrupts low level code
is to save the minimal context enabling to call C
code for performance reasons. On non recoverable
exception on the other hand, the most important is
to save the maximum information concerning proc status
in order to analyze the reason of the fault. At
least we will need this in order to implement the
port of RGDB on PPC

==> I wrote an API for connecting raw exceptions (and thus
raw interrupts) for mpc750. It should be valid for most
powerpc processors... I hope to find a way to make this coexist
with actual code layout. The code is actually located
in lib/libcpu/powerpc/mpc750 and is thus optional
(provided I write my own version of exec/score/cpu/powerpc/cpu.c ...)

See remark about files/directory layout organization in 4)

2) Current Implementation of ISR low level code


I do not understand why the MSR EE flags is cleared
again in exec/score/cpu/powerpc/irq_stubs.S

#if (PPC_USE_SPRG)

mfmsr r5
mfspr r6, sprg2

#else

lwz r6,msr_initial(r11)
lis r5,~PPC_MSR_DISABLE_MASK@ha
ori r5,r5,~PPC_MSR_DISABLE_MASK@l
and r6,r6,r5
mfmsr r5

#endif

Reading the doc, when a decrementer interrupt or an
external interrupt is active, the MSR EE flag is already
cleared. BTW if exception/interrupt could occur, it would
trash SRR0 and SRR1. In fact the code may be useful to set
MSR[RI] that re-enables exception processing. BTW I will need
to set other value in MSR to handle interrupts :

a) I want the MSR[IR] and MSR[DR] to be set for
performance reasons and also because I need DBAT
support to have access to PCI memory space as the
interrupt controller is in the PCI space.

Reading the code, I see others have the same kind of request :

/* SCE 980217

*

  • We need address translation ON when we call our ISR routine

mtmsr r5

*/

This is just another prof that even the lowest level
IRQ code is fundamentally board dependent and
not simply processor dependent especially when
the processor use external interrupt controller
because it has a single interrupt request line...

Note that if you look at the PPC code high level interrupt
handling code, as the "set_vector" routine that really connects
the interrupt is in the BSP/startup/genpvec.c,
the fact that IRQ handling is BSP specific is DE-FACTO
acknowledged.

I know I have already expressed this and understand that this
would require some heavy change in the code but believe
me you will reach a point where you will not be able
to find a compatible while optimum implementation for low level
interrupt handling code...) In my case this is already true...

So please consider removing low level IRQ handling from
exec/score/cpu/* and only let there exception handling code...
Exceptions are usually only processor dependent and do
not depend on external hardware mechanism to be masked or
acknowledged or re-enabled (there are probably exception but ...)

I have already done this for pc386 bsp but need to make it again.
This time I will even propose an API.

3) R2/R13 manipulation for EABI implementation


I do not understand the handling of r2 and r13 in the
EABI case. The specification for r2 says pointer to sdata2,
sbss2 section => constant. However I do not see -ffixed-r2
passed to any compilation system in make/custom/*
(for info linux does this on PPC).

So either this is a default compiler option when choosing
powerpc-rtems and thus we do not need to do anything with
this register as all the code is compiled with this compiler
and linked together OR this register may be used by rtems code
and then we do not need any special initialization or
handling.

The specification for r13 says pointer to the small data
area. r13 argumentation is the same except that as far
as I know the usage of the small data area requires
specific compiler support so that access to variables is
compiled via loading the LSB in a register and then
using r13 to get full address... It is like a small
memory model and it was present in IBM C compilers.

=> I propose to suppress any specific code for r2 and
r13 in the EABI case.

4) Code layout organization (yes again :-))


I think there are a number of design flaws in the way
the code is for ppc organized and I will try to point them out.
I have been beaten by this again on this new port, and
was beaten last year while modifying code for pc386.

a) exec/score/cpu/* vs lib/libcpu/cpu/*.

I think that too many things are put in exec/score/cpu that
have nothing to do with RTEMS internals but are rather
related to CPU feature.

This include at least :

a) registers access routine (e.g GET_MSR_Value),
b) interrupt masking/unmasking routines,
c) cache_mngt_routine,
d) mmu_mngt_routine,
e) Routines to connect the raw_exception, raw_interrupt
handler,

b) lib/libcpu/cpu/powerpc/*

With a processor family as exuberant as the powerpc family,
and their well known subtle differences (604 vs 750) or
unfortunately majors (8xx vs 60x) the directory structure
is fine (except maybe the names that are not homogeneous)

powerpc

ppc421 mpc821 ...

I only needed to add mpc750. But the fact that libcpu.a was not
produced was a pain and the fact that this organization may
duplicates code is also problematic.

So, except if the support of automake provides a better solution
I would like to propose something like this :

powerpc

mpc421 mpc821 ... mpc750 shared wrapup

with the following rules :

a) "shared" would act as a source container for sources that may
be shared among processors. Needed files would be compiled inside
the processor specific directory using the vpath Makefile
mechanism. "shared" may also contain compilation code
for routine that are really shared and not worth to inline...
(did not found many things so far as registers access routine
ARE WORTH INLINING)... In the case something is compiled there,
it should create libcpushared.a

b) layout under processor specific directory is free provided
that

1)the result of the compilation process exports :

libcpu/powerpc/"PROC"/*.h in $(PROJECT_INCLUDE)/libcpu

2) each processor specific directory creates
a library called libcpuspecific.a

Note that this organization enables to have a file that
is nearly the same than in shared but that must differ
because of processor differences...

c) "wrapup" should create libcpu.a using libcpushared.a
libcpuspecific.a and export it $(PROJECT_INCLUDE)/libcpu

The only thing I have no ideal solution is the way to put shared
definitions in "shared" and only processor specific definition
in "proc". To give a concrete example, most MSR bit definition
are shared among PPC processors and only some differs. if we create
a single msr.h in shared it will have ifdef. If in msr.h we
include libcpu/msr_c.h we will need to have it in each prowerpc
specific directory (even empty). Opinions are welcomed ...

Note that a similar mechanism exist in libbsp/i386 that also
contains a shared directory that is used by several bsp
like pc386 and i386ex and a similar wrapup mechanism...

NB: I have done this for mpc750 and other processors could just use
similar Makefiles...

c) The exec/score/cpu/powerpc directory layout.

I think the directory layout should be the same than the
libcpu/powerpc. As it is not, there are a lot of ifdefs
inside the code... And of course low level interrupt handling
code should be removed...

Besides that I do not understand why

1) things are compiled in the wrap directory,
2) some includes are moved to rtems/score,

I think the "preinstall" mechanism enables to put
everything in the current directory (or better in a per processor
directory),

5) Interrupt handling API


Again :-). But I think that using all the features the PIC
offers is a MUST for RT system. I already explained in the
prologue of this (long and probably boring) mail that the MCP750
boards offers an OPENPIC compliant architecture and that
the VIA 82586 PCI/ISA bridge offers a PC compatible IO and
PIC mapping. Here is a logical view of the RAVEN/VIA 82586
interrupt mapping :


| OPEN | <-----|8259|
| PIC | | | 2 ------
|(RAVEN)| | | <-----|8259|
| | | | | | 11
| | | | | | <----
| | | | | |
| | | | | |


------
| VIA PCI/ISA bridge
| x
-------- PCI interrupts

OPENPIC offers interrupt priorities among PCI interrupts
and interrupt selective masking. The 8259 offers the same kind
of feature. With actual powerpc interrupt code :

1) there is no way to specify priorities among
interrupts handler. This is REALLY a bad thing.
For me it is as importnat as having priorities
for threads...
2) for my implementation, each ISR should
contain the code that acknowledge the RAVEN
and 8259 cascade, modify interrupt mask on both
chips, and reenable interrupt at processor level,
..., restore then on interrupt return,.... This code
is actually similar to code located in some
genpvec.c powerpc files,
3) I must update _ISR_Nesting_level because
irq.inl use it...
4) the libchip code connects the ISR via set_vector
but the libchip handler code does not contain any code to
manipulate external interrupt controller hardware
in order to acknoledge the interrupt or re-enable
them (except for the target hardware of course)
So this code is broken unless set_vector adds an
additionnal prologue/epilogue before calling/returning
from in order to acknoledge/mask the raven and the
8259 PICS... => Anyway already EACH BSP MUST REWRITE
PART OF INTERRUPT HANDLING CODE TO CORRECTLY IMPLEMENT
SET_VECTOR.

I would rather offer an API similar to the one provided
in libbsp/i386/shared/irq/irq.h so that :

1) Once the driver supplied methods is called the
only things the ISR has to do is to worry about the
external hardware that triggered the interrupt.
Everything on openpic/VIA/processor would have been
done by the low levels (same things as set-vector)
2) The caller will need to supply the on/off/isOn
routine that are fundamental to correctly implements
debuggers/performance monitoring is a portable way
3) A globally configurable interrupt priorities
mechanism...

I have nothing against providing a compatible
set_vector just to make libchip happy but
as I have already explained in other
mails (months ago), I really think that the ISR
connection should be handled by the BSP and that no
code containing irq connection should exist the
rtems generic layers... Thus I really dislike
libchip on this aspect because in a long term
it will force to adopt the less reach API
for interrupt handling that exists (set_vector).

Additional note : I think the _ISR_Is_in_progress()
inline routine should be :

1) Put in a processor specific section,
2) Should not rely on a global variable,

As :

a) on symmetric MP, there is one interrupt level
per CPU,
b) On processor that have an ISP (e,g 68040),
this variable is useless (MSR bit testing could
be used)
c) On PPC, instead of using the address of the
variable via CPU_IRQ_info.Nest_level a dedicated
SPR could be used.

NOTE: most of this is also true for _Thread_Dispatch_disable_level

END NOTE


Please do not take what I said in the mail as a criticism for
anyone who submitted ppc code. Any code present helped me
a lot understanding PPC behavior. I just wanted by this
mail to :

1) try to better understand the actual code,
2) propose concrete ways of enhancing current code
by providing an alternative implementation for MCP750. I
will make my best effort to try to brake nothing but this
is actually hard due to the file layout organisation.
3) make understandable some changes I will probably make
if joel let me do them :-)

Any comments/objections are welcomed as usual.

--


/ ` Eric Valette

/-- o _. Canon CRF

(_, / (_(_( Rue de la touche lambert

35517 Cesson-Sevigne Cedex
FRANCE

Tel: +33 (0)2 99 87 68 91 Fax: +33 (0)2 99 84 11 30
E-mail: valette@…

  • Property mode set to 100644
File size: 16.5 KB
Line 
1/*  thread.h
2 *
3 *  This include file contains all constants and structures associated
4 *  with the thread control block.
5 *
6 *  COPYRIGHT (c) 1989-1998.
7 *  On-Line Applications Research Corporation (OAR).
8 *  Copyright assigned to U.S. Government, 1994.
9 *
10 *  The license and distribution terms for this file may be
11 *  found in the file LICENSE in this distribution or at
12 *  http://www.OARcorp.com/rtems/license.html.
13 *
14 *  $Id$
15 */
16
17#ifndef __THREAD_h
18#define __THREAD_h
19
20#ifdef __cplusplus
21extern "C" {
22#endif
23
24#include <rtems/score/context.h>
25#include <rtems/score/cpu.h>
26#if defined(RTEMS_MULTIPROCESSING)
27#include <rtems/score/mppkt.h>
28#endif
29#include <rtems/score/object.h>
30#include <rtems/score/priority.h>
31#include <rtems/score/stack.h>
32#include <rtems/score/states.h>
33#include <rtems/score/tod.h>
34#include <rtems/score/tqdata.h>
35#include <rtems/score/watchdog.h>
36
37/*
38 *  The following defines the "return type" of a thread.
39 */
40
41typedef void Thread;
42
43/*
44 *  The following defines the ways in which the entry point for a
45 *  thread can be invoked.  Basically, it can be passed any
46 *  combination/permutation of a pointer and an unsigned32 value.
47 *
48 *  NOTE: For now, we are ignoring the return type.
49 */
50
51typedef enum {
52  THREAD_START_NUMERIC,
53  THREAD_START_POINTER,
54  THREAD_START_BOTH_POINTER_FIRST,
55  THREAD_START_BOTH_NUMERIC_FIRST
56} Thread_Start_types;
57
58typedef Thread ( *Thread_Entry )();   /* basic type */
59
60typedef Thread ( *Thread_Entry_numeric )( unsigned32 );
61typedef Thread ( *Thread_Entry_pointer )( void * );
62typedef Thread ( *Thread_Entry_both_pointer_first )( void *, unsigned32 );
63typedef Thread ( *Thread_Entry_both_numeric_first )( unsigned32, void * );
64
65/*
66 *  The following lists the algorithms used to manage the thread cpu budget.
67 *
68 *  Reset Timeslice:   At each context switch, reset the time quantum.
69 *  Exhaust Timeslice: Only reset the quantum once it is consumed.
70 *  Callout:           Execute routine when budget is consumed.
71 */
72
73typedef enum {
74  THREAD_CPU_BUDGET_ALGORITHM_NONE,
75  THREAD_CPU_BUDGET_ALGORITHM_RESET_TIMESLICE,
76  THREAD_CPU_BUDGET_ALGORITHM_EXHAUST_TIMESLICE,
77  THREAD_CPU_BUDGET_ALGORITHM_CALLOUT
78}  Thread_CPU_budget_algorithms;
79
80typedef struct Thread_Control_struct Thread_Control;
81
82typedef void (*Thread_CPU_budget_algorithm_callout )( Thread_Control * );
83
84/*
85 *  The following structure contains the information which defines
86 *  the starting state of a thread.
87 */
88
89typedef struct {
90  Thread_Entry         entry_point;      /* starting thread address         */
91  Thread_Start_types   prototype;        /* how task is invoked             */
92  void                *pointer_argument; /* pointer argument                */
93  unsigned32           numeric_argument; /* numeric argument                */
94                                         /* initial execution modes         */
95  boolean              is_preemptible;
96  Thread_CPU_budget_algorithms          budget_algorithm;
97  Thread_CPU_budget_algorithm_callout   budget_callout;
98  unsigned32           isr_level;
99  Priority_Control     initial_priority; /* initial priority                */
100  boolean              core_allocated_stack;
101  Stack_Control        Initial_stack;    /* stack information               */
102  void                *fp_context;       /* initial FP context area address */
103  void                *stack;            /* initial stack area address      */
104}   Thread_Start_information;
105
106/*
107 *  The following structure contains the information necessary to manage
108 *  a thread which it is  waiting for a resource.
109 */
110
111#define THREAD_STATUS_PROXY_BLOCKING 0x1111111
112
113typedef struct {
114  Objects_Id            id;              /* waiting on this object       */
115  unsigned32            count;           /* "generic" fields to be used */
116  void                 *return_argument; /*   when blocking */
117  void                 *return_argument_1;
118  unsigned32            option;
119
120  /*
121   *  NOTE: The following assumes that all API return codes can be
122   *        treated as an unsigned32. 
123   */
124  unsigned32            return_code;     /* status for thread awakened   */
125
126  Chain_Control         Block2n;         /* 2 - n priority blocked chain */
127  Thread_queue_Control *queue;           /* pointer to thread queue      */
128}   Thread_Wait_information;
129
130/*
131 *  The following defines the control block used to manage
132 *  each thread proxy.
133 *
134 *  NOTE: It is critical that proxies and threads have identical
135 *        memory images for the shared part.
136 */
137
138typedef struct {
139  Objects_Control          Object;
140  States_Control           current_state;
141  Priority_Control         current_priority;
142  Priority_Control         real_priority;
143  unsigned32               resource_count;
144  Thread_Wait_information  Wait;
145  Watchdog_Control         Timer;
146#if defined(RTEMS_MULTIPROCESSING)
147  MP_packet_Prefix        *receive_packet;
148#endif
149     /****************** end of common block ********************/
150  Chain_Node               Active;
151}   Thread_Proxy_control;
152
153
154/*
155 *  The following record defines the control block used
156 *  to manage each thread.
157 *
158 *  NOTE: It is critical that proxies and threads have identical
159 *        memory images for the shared part.
160 */
161
162typedef enum {
163  THREAD_API_RTEMS,
164  THREAD_API_POSIX
165}  Thread_APIs;
166
167#define THREAD_API_FIRST THREAD_API_RTEMS
168#define THREAD_API_LAST  THREAD_API_POSIX
169
170struct Thread_Control_struct {
171  Objects_Control                       Object;
172  States_Control                        current_state;
173  Priority_Control                      current_priority;
174  Priority_Control                      real_priority;
175  unsigned32                            resource_count;
176  Thread_Wait_information               Wait;
177  Watchdog_Control                      Timer;
178#if defined(RTEMS_MULTIPROCESSING)
179  MP_packet_Prefix                     *receive_packet;
180#endif
181     /****************** end of common block ********************/
182  boolean                               is_global;
183  boolean                               do_post_task_switch_extension;
184
185  boolean                               is_preemptible;
186  void                                 *rtems_ada_self;
187  unsigned32                            cpu_time_budget;
188  Thread_CPU_budget_algorithms          budget_algorithm;
189  Thread_CPU_budget_algorithm_callout   budget_callout;
190
191  unsigned32                            ticks_executed;
192  Chain_Control                        *ready;
193  Priority_Information                  Priority_map;
194  Thread_Start_information              Start;
195  Context_Control                       Registers;
196  void                                 *fp_context;
197  void                                 *API_Extensions[ THREAD_API_LAST + 1 ];
198  void                                **extensions;
199};
200
201/*
202 *  Self for the GNU Ada Run-Time
203 */
204
205SCORE_EXTERN void *rtems_ada_self;
206 
207/*
208 *  The following defines the information control block used to
209 *  manage this class of objects.
210 */
211 
212SCORE_EXTERN Objects_Information _Thread_Internal_information;
213 
214/*
215 *  The following define the thread control pointers used to access
216 *  and manipulate the idle thread.
217 */
218 
219SCORE_EXTERN Thread_Control *_Thread_Idle;
220
221/*
222 *  The following context area contains the context of the "thread"
223 *  which invoked the start multitasking routine.  This context is
224 *  restored as the last action of the stop multitasking routine.  Thus
225 *  control of the processor can be returned to the environment
226 *  which initiated the system.
227 */
228 
229SCORE_EXTERN Context_Control _Thread_BSP_context;
230 
231/*
232 *  The following declares the dispatch critical section nesting
233 *  counter which is used to prevent context switches at inopportune
234 *  moments.
235 */
236
237SCORE_EXTERN volatile unsigned32 _Thread_Dispatch_disable_level;
238
239/*
240 *  If this is non-zero, then the post-task switch extension
241 *  is run regardless of the state of the per thread flag.
242 */
243
244SCORE_EXTERN unsigned32 _Thread_Do_post_task_switch_extension;
245
246/*
247 *  The following holds how many user extensions are in the system.  This
248 *  is used to determine how many user extension data areas to allocate
249 *  per thread.
250 */
251
252SCORE_EXTERN unsigned32 _Thread_Maximum_extensions;
253
254/*
255 *  The following is used to manage the length of a timeslice quantum.
256 */
257
258SCORE_EXTERN unsigned32 _Thread_Ticks_per_timeslice;
259
260/*
261 *  The following points to the array of FIFOs used to manage the
262 *  set of ready threads.
263 */
264
265SCORE_EXTERN Chain_Control *_Thread_Ready_chain;
266
267/*
268 *  The following points to the thread which is currently executing.
269 *  This thread is implicitly manipulated by numerous directives.
270 */
271
272SCORE_EXTERN Thread_Control *_Thread_Executing;
273
274/*
275 *  The following points to the highest priority ready thread
276 *  in the system.  Unless the current thread is not preemptibl,
277 *  then this thread will be context switched to when the next
278 *  dispatch occurs.
279 */
280
281SCORE_EXTERN Thread_Control *_Thread_Heir;
282
283/*
284 *  The following points to the thread whose floating point
285 *  context is currently loaded.
286 */
287
288SCORE_EXTERN Thread_Control *_Thread_Allocated_fp;
289
290/*
291 *  _Thread_Handler_initialization
292 *
293 *  DESCRIPTION:
294 *
295 *  This routine performs the initialization necessary for this handler.
296 */
297
298void _Thread_Handler_initialization (
299  unsigned32   ticks_per_timeslice,
300  unsigned32   maximum_extensions,
301  unsigned32   maximum_proxies
302);
303
304/*
305 *  _Thread_Create_idle
306 *
307 *  DESCRIPTION:
308 *
309 *  This routine creates the idle thread.
310 *
311 *  WARNING!! No thread should be created before this one.
312 */
313 
314void _Thread_Create_idle( void );
315
316/*
317 *  _Thread_Start_multitasking
318 *
319 *  DESCRIPTION:
320 *
321 *  This routine initiates multitasking.  It is invoked only as
322 *  part of initialization and its invocation is the last act of
323 *  the non-multitasking part of the system initialization.
324 */
325
326void _Thread_Start_multitasking( void );
327
328/*
329 *  _Thread_Dispatch
330 *
331 *  DESCRIPTION:
332 *
333 *  This routine is responsible for transferring control of the
334 *  processor from the executing thread to the heir thread.  As part
335 *  of this process, it is responsible for the following actions:
336 *
337 *     + saving the context of the executing thread
338 *     + restoring the context of the heir thread
339 *     + dispatching any signals for the resulting executing thread
340 */
341
342void _Thread_Dispatch( void );
343
344/*
345 *  _Thread_Stack_Allocate
346 * 
347 *  DESCRIPTION:
348 *
349 *  Allocate the requested stack space for the thread.
350 *  return the actual size allocated after any adjustment
351 *  or return zero if the allocation failed.
352 *  Set the Start.stack field to the address of the stack
353 *
354 *  NOTES: NONE
355 *
356 */
357
358unsigned32 _Thread_Stack_Allocate(
359  Thread_Control *the_thread,
360  unsigned32 stack_size
361);
362
363/*
364 *  _Thread_Stack_Free
365 *
366 *  DESCRIPTION:
367 *
368 *  Deallocate the Thread's stack.
369 *  NOTES: NONE
370 *
371 */
372
373void _Thread_Stack_Free(
374  Thread_Control *the_thread
375);
376
377/*
378 *  _Thread_Initialize
379 *
380 *  DESCRIPTION:
381 *
382 *  XXX
383 *
384 *  NOTES:
385 *
386 *  If stack_area is NULL, it is allocated from the workspace.
387 *
388 *  If the stack is allocated from the workspace, then it is guaranteed to be
389 *  of at least minimum size.
390 */
391
392boolean _Thread_Initialize(
393  Objects_Information                  *information,
394  Thread_Control                       *the_thread,
395  void                                 *stack_area,
396  unsigned32                            stack_size,
397  boolean                               is_fp,
398  Priority_Control                      priority,
399  boolean                               is_preemptible,
400  Thread_CPU_budget_algorithms          budget_algorithm,
401  Thread_CPU_budget_algorithm_callout   budget_callout,
402  unsigned32                            isr_level,
403  Objects_Name                          name
404);
405
406/*
407 *  _Thread_Start
408 *
409 *  DESCRIPTION:
410 *
411 *  XXX
412 */
413 
414boolean _Thread_Start(
415  Thread_Control           *the_thread,
416  Thread_Start_types        the_prototype,
417  void                     *entry_point,
418  void                     *pointer_argument,
419  unsigned32                numeric_argument
420);
421
422/*
423 *  _Thread_Restart
424 *
425 *  DESCRIPTION:
426 *
427 *  XXX
428 */
429 
430/* XXX multiple task arg profiles */
431 
432boolean _Thread_Restart(
433  Thread_Control           *the_thread,
434  void                     *pointer_argument,
435  unsigned32                numeric_argument
436);
437
438/*
439 *  _Thread_Close
440 *
441 *  DESCRIPTION:
442 *
443 *  XXX
444 */
445 
446void _Thread_Close(
447  Objects_Information  *information,
448  Thread_Control       *the_thread
449);
450
451/*
452 *  _Thread_Ready
453 *
454 *  DESCRIPTION:
455 *
456 *  This routine removes any set states for the_thread.  It performs
457 *  any necessary scheduling operations including the selection of
458 *  a new heir thread.
459 */
460
461void _Thread_Ready(
462  Thread_Control *the_thread
463);
464
465/*
466 *  _Thread_Clear_state
467 *
468 *  DESCRIPTION:
469 *
470 *  This routine clears the indicated STATES for the_thread.  It performs
471 *  any necessary scheduling operations including the selection of
472 *  a new heir thread.
473 */
474
475void _Thread_Clear_state(
476  Thread_Control *the_thread,
477  States_Control  state
478);
479
480/*
481 *  _Thread_Set_state
482 *
483 *  DESCRIPTION:
484 *
485 *  This routine sets the indicated states for the_thread.  It performs
486 *  any necessary scheduling operations including the selection of
487 *  a new heir thread.
488 *
489 */
490
491void _Thread_Set_state(
492  Thread_Control *the_thread,
493  States_Control  state
494);
495
496/*
497 *  _Thread_Set_transient
498 *
499 *  DESCRIPTION:
500 *
501 *  This routine sets the TRANSIENT state for the_thread.  It performs
502 *  any necessary scheduling operations including the selection of
503 *  a new heir thread.
504 */
505
506void _Thread_Set_transient(
507  Thread_Control *the_thread
508);
509
510/*
511 *  _Thread_Reset_timeslice
512 *
513 *  DESCRIPTION:
514 *
515 *  This routine is invoked upon expiration of the currently
516 *  executing thread's timeslice.  If no other thread's are ready
517 *  at the priority of the currently executing thread, then the
518 *  executing thread's timeslice is reset.  Otherwise, the
519 *  currently executing thread is placed at the rear of the
520 *  FIFO for this priority and a new heir is selected.
521 */
522
523void _Thread_Reset_timeslice( void );
524
525/*
526 *  _Thread_Tickle_timeslice
527 *
528 *  DESCRIPTION:
529 *
530 *  This routine is invoked as part of processing each clock tick.
531 *  It is responsible for determining if the current thread allows
532 *  timeslicing and, if so, when its timeslice expires.
533 */
534
535void _Thread_Tickle_timeslice( void );
536
537/*
538 *  _Thread_Yield_processor
539 *
540 *  DESCRIPTION:
541 *
542 *  This routine is invoked when a thread wishes to voluntarily
543 *  transfer control of the processor to another thread of equal
544 *  or greater priority.
545 */
546
547void _Thread_Yield_processor( void );
548
549/*
550 *  _Thread_Load_environment
551 *
552 *  DESCRIPTION:
553 *
554 *  This routine initializes the context of the_thread to its
555 *  appropriate starting state.
556 */
557
558void _Thread_Load_environment(
559  Thread_Control *the_thread
560);
561
562/*
563 *  _Thread_Handler
564 *
565 *  DESCRIPTION:
566 *
567 *  This routine is the wrapper function for all threads.  It is
568 *  the starting point for all threads.  The user provided thread
569 *  entry point is invoked by this routine.  Operations
570 *  which must be performed immediately before and after the user's
571 *  thread executes are found here.
572 */
573
574void _Thread_Handler( void );
575
576/*
577 *  _Thread_Delay_ended
578 *
579 *  DESCRIPTION:
580 *
581 *  This routine is invoked when a thread must be unblocked at the
582 *  end of a time based delay (i.e. wake after or wake when).
583 */
584
585void _Thread_Delay_ended(
586  Objects_Id  id,
587  void       *ignored
588);
589
590/*
591 *  _Thread_Change_priority
592 *
593 *  DESCRIPTION:
594 *
595 *  This routine changes the current priority of the_thread to
596 *  new_priority.  It performs any necessary scheduling operations
597 *  including the selection of a new heir thread.
598 */
599
600void _Thread_Change_priority (
601  Thread_Control   *the_thread,
602  Priority_Control  new_priority,
603  boolean           prepend_it
604);
605
606/*
607 *  _Thread_Set_priority
608 *
609 *  DESCRIPTION:
610 *
611 *  This routine updates the priority related fields in the_thread
612 *  control block to indicate the current priority is now new_priority.
613 */
614
615void _Thread_Set_priority(
616  Thread_Control   *the_thread,
617  Priority_Control  new_priority
618);
619
620/*
621 *  _Thread_Evaluate_mode
622 *
623 *  DESCRIPTION:
624 *
625 *  This routine XXX
626 */
627
628boolean _Thread_Evaluate_mode( void );
629
630/*
631 *  _Thread_Get
632 *
633 *  NOTE:  If we are not using static inlines, this must be a real
634 *         subroutine call.
635 */
636 
637#ifndef USE_INLINES
638Thread_Control *_Thread_Get (
639  Objects_Id           id,
640  Objects_Locations   *location
641);
642#endif
643
644/*
645 *  _Thread_Idle_body
646 *
647 *  DESCRIPTION:
648 *
649 *  This routine is the body of the system idle thread.
650 */
651 
652#if (CPU_PROVIDES_IDLE_THREAD_BODY == FALSE)
653Thread _Thread_Idle_body(
654  unsigned32 ignored
655);
656#endif
657
658#ifndef __RTEMS_APPLICATION__
659#include <rtems/score/thread.inl>
660#endif
661#if defined(RTEMS_MULTIPROCESSING)
662#include <rtems/score/threadmp.h>
663#endif
664
665#ifdef __cplusplus
666}
667#endif
668
669#endif
670/* end of include file */
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