source: rtems/c/src/exec/score/include/rtems/score/isr.h @ 937a6f3c

4.104.114.84.95
Last change on this file since 937a6f3c was 937a6f3c, checked in by Joel Sherrill <joel.sherrill@…>, on 06/03/98 at 19:00:17

Added CPU_ISR_PASSES_FRAME_POINTER so some ports could pass just the
vector number to user ISR's and other ports could pass both the vector
number and a pointer to the ISF.

  • Property mode set to 100644
File size: 5.9 KB
Line 
1/*  isr.h
2 *
3 *  This include file contains all the constants and structures associated
4 *  with the management of processor interrupt levels.  This handler
5 *  supports interrupt critical sections, vectoring of user interrupt
6 *  handlers, nesting of interrupts, and manipulating interrupt levels.
7 *
8 *  COPYRIGHT (c) 1989-1998.
9 *  On-Line Applications Research Corporation (OAR).
10 *  Copyright assigned to U.S. Government, 1994.
11 *
12 *  The license and distribution terms for this file may be
13 *  found in the file LICENSE in this distribution or at
14 *  http://www.OARcorp.com/rtems/license.html.
15 *
16 *  $Id$
17 */
18
19#ifndef __ISR_h
20#define __ISR_h
21
22#ifdef __cplusplus
23extern "C" {
24#endif
25
26/*
27 *  The following type defines the control block used to manage
28 *  the interrupt level portion of the status register.
29 */
30
31typedef unsigned32 ISR_Level;
32
33/*
34 *  The following type defines the type used to manage the vectors.
35 */
36
37typedef unsigned32 ISR_Vector_number;
38
39/*
40 *  Return type for ISR Handler
41 */
42
43typedef void ISR_Handler;
44
45/*
46 *  Pointer to an ISR Handler
47 */
48
49#if (CPU_ISR_PASSES_FRAME_POINTER == 1)
50typedef ISR_Handler ( *ISR_Handler_entry )(
51                 ISR_Vector_number,
52                 CPU_Interrupt_frame *
53             );
54#else
55typedef ISR_Handler ( *ISR_Handler_entry )(
56                 ISR_Vector_number
57             );
58#endif
59/*
60 *  This constant promotes out the number of vectors truly supported by
61 *  the current CPU being used.  This is usually the number of distinct vectors
62 *  the cpu can vector.
63 */
64 
65#define ISR_NUMBER_OF_VECTORS                CPU_INTERRUPT_NUMBER_OF_VECTORS
66
67/*
68 *  This constant promotes out the highest valid interrupt vector number.
69 */
70
71#define ISR_INTERRUPT_MAXIMUM_VECTOR_NUMBER  CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER
72
73/*
74 *  The following is TRUE if signals have been sent to the currently
75 *  executing thread by an ISR handler.
76 */
77
78SCORE_EXTERN boolean    _ISR_Signals_to_thread_executing;
79
80/*
81 *  The following contains the interrupt service routine nest level.
82 *  When this variable is zero, a thread is executing.
83 */
84
85SCORE_EXTERN unsigned32 _ISR_Nest_level;
86
87/*
88 *  The following declares the Vector Table.  Application
89 *  interrupt service routines are vectored by the ISR Handler via this table.
90 */
91
92SCORE_EXTERN ISR_Handler_entry _ISR_Vector_table[ ISR_NUMBER_OF_VECTORS ];
93
94/*
95 *  _ISR_Handler_initialization
96 *
97 *  DESCRIPTION:
98 *
99 *  This routine performs the initialization necessary for this handler.
100 */
101
102void _ISR_Handler_initialization ( void );
103
104/*
105 *  _ISR_Disable
106 *
107 *  DESCRIPTION:
108 *
109 *  This routine disables all interrupts so that a critical section
110 *  of code can be executing without being interrupted.  Upon return,
111 *  the argument _level will contain the previous interrupt mask level.
112 */
113
114#define _ISR_Disable( _level ) \
115        _CPU_ISR_Disable( _level )
116
117/*
118 *  _ISR_Enable
119 *
120 *  DESCRIPTION:
121 *
122 *  This routine enables interrupts to the previous interrupt mask
123 *  LEVEL.  It is used at the end of a critical section of code to
124 *  enable interrupts so they can be processed again.
125 */
126
127#define _ISR_Enable( _level ) \
128        _CPU_ISR_Enable( _level )
129
130/*
131 *  _ISR_Flash
132 *
133 *  DESCRIPTION:
134 *
135 *  This routine temporarily enables interrupts to the previous
136 *  interrupt mask level and then disables all interrupts so that
137 *  the caller can continue into the second part of a critical
138 *  section.  This routine is used to temporarily enable interrupts
139 *  during a long critical section.  It is used in long sections of
140 *  critical code when a point is reached at which interrupts can
141 *  be temporarily enabled.  Deciding where to flash interrupts
142 *  in a long critical section is often difficult and the point
143 *  must be selected with care to insure that the critical section
144 *  properly protects itself.
145 */
146
147#define _ISR_Flash( _level ) \
148        _CPU_ISR_Flash( _level )
149
150/*
151 *  _ISR_Install_vector
152 *
153 *  DESCRIPTION:
154 *
155 *  This routine installs new_handler as the interrupt service routine
156 *  for the specified vector.  The previous interrupt service routine is
157 *  returned as old_handler.
158 */
159
160#define _ISR_Install_vector( _vector, _new_handler, _old_handler ) \
161  _CPU_ISR_install_vector( _vector, _new_handler, _old_handler )
162
163/*
164 *  _ISR_Get_level
165 *
166 *  DESCRIPTION:
167 *
168 *  This routine returns the current interrupt level.
169 */
170 
171#define _ISR_Get_level() \
172        _CPU_ISR_Get_level()
173 
174/*
175 *  _ISR_Set_level
176 *
177 *  DESCRIPTION:
178 *
179 *  This routine sets the current interrupt level to that specified
180 *  by new_level.  The new interrupt level is effective when the
181 *  routine exits.
182 */
183
184#define _ISR_Set_level( _new_level ) \
185        _CPU_ISR_Set_level( _new_level )
186
187/*
188 *  _ISR_Handler
189 *
190 *  DESCRIPTION:
191 *
192 *  This routine is the interrupt dispatcher.  ALL interrupts
193 *  are vectored to this routine so that minimal context can be saved
194 *  and setup performed before the application's high-level language
195 *  interrupt service routine is invoked.   After the application's
196 *  interrupt service routine returns control to this routine, it
197 *  will determine if a thread dispatch is necessary.  If so, it will
198 *  insure that the necessary thread scheduling operations are
199 *  performed when the outermost interrupt service routine exits.
200 *
201 *  NOTE:  Implemented in assembly language.
202 */
203
204void _ISR_Handler( void );
205
206/*
207 *  _ISR_Dispatch
208 *
209 *  DESCRIPTION:
210 *
211 *  This routine provides a wrapper so that the routine
212 *  _Thread_Dispatch can be invoked when a reschedule is necessary
213 *  at the end of the outermost interrupt service routine.  This
214 *  wrapper is necessary to establish the processor context needed
215 *  by _Thread_Dispatch and to save the processor context which is
216 *  corrupted by _Thread_Dispatch.  This context typically consists
217 *  of registers which are not preserved across routine invocations.
218 *
219 *  NOTE:  Implemented in assembly language.
220 */
221
222void _ISR_Dispatch( void );
223
224#include <rtems/score/isr.inl>
225
226#ifdef __cplusplus
227}
228#endif
229
230#endif
231/* end of include file */
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