1 | /* isr.h |
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2 | * |
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3 | * This include file contains all the constants and structures associated |
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4 | * with the management of processor interrupt levels. This handler |
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5 | * supports interrupt critical sections, vectoring of user interrupt |
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6 | * handlers, nesting of interrupts, and manipulating interrupt levels. |
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7 | * |
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8 | * COPYRIGHT (c) 1989-1998. |
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9 | * On-Line Applications Research Corporation (OAR). |
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10 | * Copyright assigned to U.S. Government, 1994. |
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11 | * |
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12 | * The license and distribution terms for this file may be |
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13 | * found in the file LICENSE in this distribution or at |
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14 | * http://www.OARcorp.com/rtems/license.html. |
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15 | * |
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16 | * $Id$ |
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17 | */ |
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18 | |
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19 | #ifndef __ISR_h |
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20 | #define __ISR_h |
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21 | |
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22 | #ifdef __cplusplus |
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23 | extern "C" { |
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24 | #endif |
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25 | |
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26 | /* |
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27 | * The following type defines the control block used to manage |
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28 | * the interrupt level portion of the status register. |
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29 | */ |
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30 | |
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31 | typedef unsigned32 ISR_Level; |
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32 | |
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33 | /* |
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34 | * The following type defines the type used to manage the vectors. |
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35 | */ |
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36 | |
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37 | typedef unsigned32 ISR_Vector_number; |
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38 | |
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39 | /* |
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40 | * Return type for ISR Handler |
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41 | */ |
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42 | |
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43 | typedef void ISR_Handler; |
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44 | |
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45 | /* |
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46 | * Pointer to an ISR Handler |
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47 | */ |
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48 | |
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49 | typedef ISR_Handler ( *ISR_Handler_entry )( |
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50 | ISR_Vector_number |
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51 | ); |
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52 | /* |
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53 | * This constant promotes out the number of vectors truly supported by |
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54 | * the current CPU being used. This is usually the number of distinct vectors |
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55 | * the cpu can vector. |
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56 | */ |
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57 | |
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58 | #define ISR_NUMBER_OF_VECTORS CPU_INTERRUPT_NUMBER_OF_VECTORS |
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59 | |
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60 | /* |
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61 | * This constant promotes out the highest valid interrupt vector number. |
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62 | */ |
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63 | |
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64 | #define ISR_INTERRUPT_MAXIMUM_VECTOR_NUMBER CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER |
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65 | |
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66 | /* |
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67 | * The following is TRUE if signals have been sent to the currently |
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68 | * executing thread by an ISR handler. |
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69 | */ |
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70 | |
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71 | SCORE_EXTERN boolean _ISR_Signals_to_thread_executing; |
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72 | |
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73 | /* |
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74 | * The following contains the interrupt service routine nest level. |
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75 | * When this variable is zero, a thread is executing. |
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76 | */ |
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77 | |
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78 | SCORE_EXTERN unsigned32 _ISR_Nest_level; |
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79 | |
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80 | /* |
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81 | * The following declares the Vector Table. Application |
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82 | * interrupt service routines are vectored by the ISR Handler via this table. |
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83 | */ |
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84 | |
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85 | SCORE_EXTERN ISR_Handler_entry _ISR_Vector_table[ ISR_NUMBER_OF_VECTORS ]; |
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86 | |
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87 | /* |
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88 | * _ISR_Handler_initialization |
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89 | * |
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90 | * DESCRIPTION: |
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91 | * |
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92 | * This routine performs the initialization necessary for this handler. |
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93 | */ |
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94 | |
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95 | void _ISR_Handler_initialization ( void ); |
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96 | |
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97 | /* |
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98 | * _ISR_Disable |
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99 | * |
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100 | * DESCRIPTION: |
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101 | * |
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102 | * This routine disables all interrupts so that a critical section |
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103 | * of code can be executing without being interrupted. Upon return, |
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104 | * the argument _level will contain the previous interrupt mask level. |
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105 | */ |
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106 | |
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107 | #define _ISR_Disable( _level ) \ |
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108 | _CPU_ISR_Disable( _level ) |
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109 | |
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110 | /* |
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111 | * _ISR_Enable |
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112 | * |
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113 | * DESCRIPTION: |
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114 | * |
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115 | * This routine enables interrupts to the previous interrupt mask |
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116 | * LEVEL. It is used at the end of a critical section of code to |
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117 | * enable interrupts so they can be processed again. |
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118 | */ |
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119 | |
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120 | #define _ISR_Enable( _level ) \ |
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121 | _CPU_ISR_Enable( _level ) |
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122 | |
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123 | /* |
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124 | * _ISR_Flash |
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125 | * |
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126 | * DESCRIPTION: |
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127 | * |
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128 | * This routine temporarily enables interrupts to the previous |
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129 | * interrupt mask level and then disables all interrupts so that |
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130 | * the caller can continue into the second part of a critical |
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131 | * section. This routine is used to temporarily enable interrupts |
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132 | * during a long critical section. It is used in long sections of |
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133 | * critical code when a point is reached at which interrupts can |
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134 | * be temporarily enabled. Deciding where to flash interrupts |
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135 | * in a long critical section is often difficult and the point |
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136 | * must be selected with care to insure that the critical section |
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137 | * properly protects itself. |
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138 | */ |
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139 | |
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140 | #define _ISR_Flash( _level ) \ |
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141 | _CPU_ISR_Flash( _level ) |
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142 | |
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143 | /* |
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144 | * _ISR_Install_vector |
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145 | * |
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146 | * DESCRIPTION: |
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147 | * |
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148 | * This routine installs new_handler as the interrupt service routine |
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149 | * for the specified vector. The previous interrupt service routine is |
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150 | * returned as old_handler. |
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151 | */ |
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152 | |
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153 | #define _ISR_Install_vector( _vector, _new_handler, _old_handler ) \ |
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154 | _CPU_ISR_install_vector( _vector, _new_handler, _old_handler ) |
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155 | |
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156 | /* |
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157 | * _ISR_Get_level |
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158 | * |
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159 | * DESCRIPTION: |
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160 | * |
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161 | * This routine returns the current interrupt level. |
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162 | */ |
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163 | |
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164 | #define _ISR_Get_level() \ |
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165 | _CPU_ISR_Get_level() |
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166 | |
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167 | /* |
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168 | * _ISR_Set_level |
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169 | * |
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170 | * DESCRIPTION: |
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171 | * |
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172 | * This routine sets the current interrupt level to that specified |
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173 | * by new_level. The new interrupt level is effective when the |
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174 | * routine exits. |
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175 | */ |
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176 | |
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177 | #define _ISR_Set_level( _new_level ) \ |
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178 | _CPU_ISR_Set_level( _new_level ) |
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179 | |
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180 | /* |
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181 | * _ISR_Handler |
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182 | * |
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183 | * DESCRIPTION: |
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184 | * |
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185 | * This routine is the interrupt dispatcher. ALL interrupts |
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186 | * are vectored to this routine so that minimal context can be saved |
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187 | * and setup performed before the application's high-level language |
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188 | * interrupt service routine is invoked. After the application's |
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189 | * interrupt service routine returns control to this routine, it |
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190 | * will determine if a thread dispatch is necessary. If so, it will |
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191 | * insure that the necessary thread scheduling operations are |
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192 | * performed when the outermost interrupt service routine exits. |
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193 | * |
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194 | * NOTE: Implemented in assembly language. |
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195 | */ |
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196 | |
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197 | void _ISR_Handler( void ); |
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198 | |
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199 | /* |
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200 | * _ISR_Dispatch |
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201 | * |
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202 | * DESCRIPTION: |
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203 | * |
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204 | * This routine provides a wrapper so that the routine |
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205 | * _Thread_Dispatch can be invoked when a reschedule is necessary |
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206 | * at the end of the outermost interrupt service routine. This |
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207 | * wrapper is necessary to establish the processor context needed |
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208 | * by _Thread_Dispatch and to save the processor context which is |
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209 | * corrupted by _Thread_Dispatch. This context typically consists |
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210 | * of registers which are not preserved across routine invocations. |
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211 | * |
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212 | * NOTE: Implemented in assembly language. |
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213 | */ |
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214 | |
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215 | void _ISR_Dispatch( void ); |
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216 | |
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217 | #include <rtems/score/isr.inl> |
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218 | |
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219 | #ifdef __cplusplus |
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220 | } |
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221 | #endif |
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222 | |
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223 | #endif |
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224 | /* end of include file */ |
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