source: rtems/c/src/exec/score/headers/isr.h @ 1a8fde6c

4.104.114.84.95
Last change on this file since 1a8fde6c was 1a8fde6c, checked in by Joel Sherrill <joel.sherrill@…>, on 03/06/96 at 21:34:57

Removed prototyes for static inline routines and moved the comments into
the inline implementation. The impetus for this was twofold. First,
it is incorrect to have static inline prototypes when using the macro
implementation. Second, this reduced the number of lines in the include
files seen by rtems.h by about 2000 lines.

Next we restricted visibility for the inline routines to inside the
executive itself EXCEPT for a handful of objects. This reduced the
number of include files included by rtems.h by 40 files and reduced
the lines in the include files seen by rtems.h by about 6000 lines.

In total, these reduced the compile time of the entire RTEMS tree by 20%.
This results in about 8 minutes savings on the SparcStation? 10 morgana.

  • Property mode set to 100644
File size: 5.8 KB
Line 
1/*  isr.h
2 *
3 *  This include file contains all the constants and structures associated
4 *  with the management of processor interrupt levels.  This handler
5 *  supports interrupt critical sections, vectoring of user interrupt
6 *  handlers, nesting of interrupts, and manipulating interrupt levels.
7 *
8 *  COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994.
9 *  On-Line Applications Research Corporation (OAR).
10 *  All rights assigned to U.S. Government, 1994.
11 *
12 *  This material may be reproduced by or for the U.S. Government pursuant
13 *  to the copyright license under the clause at DFARS 252.227-7013.  This
14 *  notice must appear in all copies of this file and its derivatives.
15 *
16 *  $Id$
17 */
18
19#ifndef __ISR_h
20#define __ISR_h
21
22#ifdef __cplusplus
23extern "C" {
24#endif
25
26/*
27 *  The following type defines the control block used to manage
28 *  the interrupt level portion of the status register.
29 */
30
31typedef unsigned32 ISR_Level;
32
33/*
34 *  The following type defines the type used to manage the vectors.
35 */
36
37typedef unsigned32 ISR_Vector_number;
38
39/*
40 *  Return type for ISR Handler
41 */
42
43typedef void ISR_Handler;
44
45/*
46 *  Pointer to an ISR Handler
47 */
48
49typedef ISR_Handler ( *ISR_Handler_entry )(
50                 ISR_Vector_number
51             );
52/*
53 *  This constant promotes out the number of vectors truly supported by
54 *  the current CPU being used.  This is usually the number of distinct vectors
55 *  the cpu can vector.
56 */
57 
58#define ISR_NUMBER_OF_VECTORS                CPU_INTERRUPT_NUMBER_OF_VECTORS
59
60/*
61 *  This constant promotes out the highest valid interrupt vector number.
62 */
63
64#define ISR_INTERRUPT_MAXIMUM_VECTOR_NUMBER  CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER
65
66/*
67 *  The following is TRUE if signals have been sent to the currently
68 *  executing thread by an ISR handler.
69 */
70
71EXTERN boolean    _ISR_Signals_to_thread_executing;
72
73/*
74 *  The following contains the interrupt service routine nest level.
75 *  When this variable is zero, a thread is executing.
76 */
77
78EXTERN unsigned32 _ISR_Nest_level;
79
80/*
81 *  The following declares the Vector Table.  Application
82 *  interrupt service routines are vectored by the ISR Handler via this table.
83 */
84
85EXTERN ISR_Handler_entry _ISR_Vector_table[ ISR_NUMBER_OF_VECTORS ];
86
87/*
88 *  _ISR_Handler_initialization
89 *
90 *  DESCRIPTION:
91 *
92 *  This routine performs the initialization necessary for this handler.
93 */
94
95void _ISR_Handler_initialization ( void );
96
97/*
98 *  _ISR_Disable
99 *
100 *  DESCRIPTION:
101 *
102 *  This routine disables all interrupts so that a critical section
103 *  of code can be executing without being interrupted.  Upon return,
104 *  the argument _level will contain the previous interrupt mask level.
105 */
106
107#define _ISR_Disable( _level ) \
108        _CPU_ISR_Disable( _level )
109
110/*
111 *  _ISR_Enable
112 *
113 *  DESCRIPTION:
114 *
115 *  This routine enables interrupts to the previous interrupt mask
116 *  LEVEL.  It is used at the end of a critical section of code to
117 *  enable interrupts so they can be processed again.
118 */
119
120#define _ISR_Enable( _level ) \
121        _CPU_ISR_Enable( _level )
122
123/*
124 *  _ISR_Flash
125 *
126 *  DESCRIPTION:
127 *
128 *  This routine temporarily enables interrupts to the previous
129 *  interrupt mask level and then disables all interrupts so that
130 *  the caller can continue into the second part of a critical
131 *  section.  This routine is used to temporarily enable interrupts
132 *  during a long critical section.  It is used in long sections of
133 *  critical code when a point is reached at which interrupts can
134 *  be temporarily enabled.  Deciding where to flash interrupts
135 *  in a long critical section is often difficult and the point
136 *  must be selected with care to insure that the critical section
137 *  properly protects itself.
138 */
139
140#define _ISR_Flash( _level ) \
141        _CPU_ISR_Flash( _level )
142
143/*
144 *  _ISR_Install_vector
145 *
146 *  DESCRIPTION:
147 *
148 *  This routine installs new_handler as the interrupt service routine
149 *  for the specified vector.  The previous interrupt service routine is
150 *  returned as old_handler.
151 */
152
153#define _ISR_Install_vector( _vector, _new_handler, _old_handler ) \
154  _CPU_ISR_install_vector( _vector, _new_handler, _old_handler )
155
156/*
157 *  _ISR_Get_level
158 *
159 *  DESCRIPTION:
160 *
161 *  This routine returns the current interrupt level.
162 */
163 
164#define _ISR_Get_level() \
165        _CPU_ISR_Get_level()
166 
167/*
168 *  _ISR_Set_level
169 *
170 *  DESCRIPTION:
171 *
172 *  This routine sets the current interrupt level to that specified
173 *  by new_level.  The new interrupt level is effective when the
174 *  routine exits.
175 */
176
177#define _ISR_Set_level( _new_level ) \
178        _CPU_ISR_Set_level( _new_level )
179
180/*
181 *  _ISR_Handler
182 *
183 *  DESCRIPTION:
184 *
185 *  This routine is the interrupt dispatcher.  ALL interrupts
186 *  are vectored to this routine so that minimal context can be saved
187 *  and setup performed before the application's high-level language
188 *  interrupt service routine is invoked.   After the application's
189 *  interrupt service routine returns control to this routine, it
190 *  will determine if a thread dispatch is necessary.  If so, it will
191 *  insure that the necessary thread scheduling operations are
192 *  performed when the outermost interrupt service routine exits.
193 *
194 *  NOTE:  Implemented in assembly language.
195 */
196
197void _ISR_Handler( void );
198
199/*
200 *  _ISR_Dispatch
201 *
202 *  DESCRIPTION:
203 *
204 *  This routine provides a wrapper so that the routine
205 *  _Thread_Dispatch can be invoked when a reschedule is necessary
206 *  at the end of the outermost interrupt service routine.  This
207 *  wrapper is necessary to establish the processor context needed
208 *  by _Thread_Dispatch and to save the processor context which is
209 *  corrupted by _Thread_Dispatch.  This context typically consists
210 *  of registers which are not preserved across routine invocations.
211 *
212 *  NOTE:  Implemented in assembly language.
213 */
214
215void _ISR_Dispatch( void );
216
217#ifndef __RTEMS_APPLICATION__
218#include <rtems/score/isr.inl>
219#endif
220
221#ifdef __cplusplus
222}
223#endif
224
225#endif
226/* end of include file */
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