source: rtems/c/src/exec/score/cpu/unix/rtems/score/cpu.h @ 6ce466d

4.104.114.84.95
Last change on this file since 6ce466d was 6ce466d, checked in by Joel Sherrill <joel.sherrill@…>, on May 8, 2001 at 10:58:08 PM

2001-05-07 Ralf Corsepius <corsepiu@…>

  • rtems/score/cpu.h: Remove #undef STRICT_ANSI.
  • Property mode set to 100644
File size: 32.4 KB
Line 
1/*  cpu.h
2 *
3 *  This include file contains information pertaining to the HP
4 *  PA-RISC processor (Level 1.1).
5 *
6 *  COPYRIGHT (c) 1994 by Division Incorporated
7 *
8 *  The license and distribution terms for this file may be
9 *  found in the file LICENSE in this distribution or at
10 *  http://www.OARcorp.com/rtems/license.html.
11 *
12 *  $Id$
13 */
14
15#ifndef __CPU_h
16#define __CPU_h
17
18#ifdef __cplusplus
19extern "C" {
20#endif
21
22#include <rtems/score/unix.h>              /* pick up machine definitions */
23#ifndef ASM
24#include <rtems/score/unixtypes.h>
25#endif
26
27#include <rtems/score/unixsize.h>
28
29#if defined(solaris2)
30#undef  _POSIX_C_SOURCE
31#define _POSIX_C_SOURCE 3
32#endif
33
34#if defined(linux)
35#define MALLOC_0_RETURNS_NULL
36#endif
37
38/* conditional compilation parameters */
39
40/*
41 *  Should the calls to _Thread_Enable_dispatch be inlined?
42 *
43 *  If TRUE, then they are inlined.
44 *  If FALSE, then a subroutine call is made.
45 *
46 *  Basically this is an example of the classic trade-off of size
47 *  versus speed.  Inlining the call (TRUE) typically increases the
48 *  size of RTEMS while speeding up the enabling of dispatching.
49 *  [NOTE: In general, the _Thread_Dispatch_disable_level will
50 *  only be 0 or 1 unless you are in an interrupt handler and that
51 *  interrupt handler invokes the executive.]  When not inlined
52 *  something calls _Thread_Enable_dispatch which in turns calls
53 *  _Thread_Dispatch.  If the enable dispatch is inlined, then
54 *  one subroutine call is avoided entirely.]
55 */
56
57#define CPU_INLINE_ENABLE_DISPATCH       FALSE
58
59/*
60 *  Should the body of the search loops in _Thread_queue_Enqueue_priority
61 *  be unrolled one time?  In unrolled each iteration of the loop examines
62 *  two "nodes" on the chain being searched.  Otherwise, only one node
63 *  is examined per iteration.
64 *
65 *  If TRUE, then the loops are unrolled.
66 *  If FALSE, then the loops are not unrolled.
67 *
68 *  The primary factor in making this decision is the cost of disabling
69 *  and enabling interrupts (_ISR_Flash) versus the cost of rest of the
70 *  body of the loop.  On some CPUs, the flash is more expensive than
71 *  one iteration of the loop body.  In this case, it might be desirable
72 *  to unroll the loop.  It is important to note that on some CPUs, this
73 *  code is the longest interrupt disable period in RTEMS.  So it is
74 *  necessary to strike a balance when setting this parameter.
75 */
76
77#define CPU_UNROLL_ENQUEUE_PRIORITY      TRUE
78
79/*
80 *  Does RTEMS manage a dedicated interrupt stack in software?
81 *
82 *  If TRUE, then a stack is allocated in _ISR_Handler_initialization.
83 *  If FALSE, nothing is done.
84 *
85 *  If the CPU supports a dedicated interrupt stack in hardware,
86 *  then it is generally the responsibility of the BSP to allocate it
87 *  and set it up.
88 *
89 *  If the CPU does not support a dedicated interrupt stack, then
90 *  the porter has two options: (1) execute interrupts on the
91 *  stack of the interrupted task, and (2) have RTEMS manage a dedicated
92 *  interrupt stack.
93 *
94 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
95 *
96 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
97 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
98 *  possible that both are FALSE for a particular CPU.  Although it
99 *  is unclear what that would imply about the interrupt processing
100 *  procedure on that CPU.
101 */
102
103#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE
104
105/*
106 *  Does this CPU have hardware support for a dedicated interrupt stack?
107 *
108 *  If TRUE, then it must be installed during initialization.
109 *  If FALSE, then no installation is performed.
110 *
111 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
112 *
113 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
114 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
115 *  possible that both are FALSE for a particular CPU.  Although it
116 *  is unclear what that would imply about the interrupt processing
117 *  procedure on that CPU.
118 */
119
120#define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE
121
122/*
123 *  Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
124 *
125 *  If TRUE, then the memory is allocated during initialization.
126 *  If FALSE, then the memory is allocated during initialization.
127 *
128 *  This should be TRUE if CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE
129 *  or CPU_INSTALL_HARDWARE_INTERRUPT_STACK is TRUE.
130 */
131
132#define CPU_ALLOCATE_INTERRUPT_STACK FALSE
133
134/*
135 *  Does the RTEMS invoke the user's ISR with the vector number and
136 *  a pointer to the saved interrupt frame (1) or just the vector
137 *  number (0)?
138 */
139
140#define CPU_ISR_PASSES_FRAME_POINTER 0
141
142/*
143 *  Does the CPU have hardware floating point?
144 *
145 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
146 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
147 *
148 *  If there is a FP coprocessor such as the i387 or mc68881, then
149 *  the answer is TRUE.
150 *
151 *  The macro name "NO_CPU_HAS_FPU" should be made CPU specific.
152 *  It indicates whether or not this CPU model has FP support.  For
153 *  example, it would be possible to have an i386_nofp CPU model
154 *  which set this to false to indicate that you have an i386 without
155 *  an i387 and wish to leave floating point support out of RTEMS.
156 */
157
158#define CPU_HARDWARE_FP     TRUE
159#define CPU_SOFTWARE_FP     FALSE
160
161/*
162 *  Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
163 *
164 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
165 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
166 *
167 *  So far, the only CPU in which this option has been used is the
168 *  HP PA-RISC.  The HP C compiler and gcc both implicitly use the
169 *  floating point registers to perform integer multiplies.  If
170 *  a function which you would not think utilize the FP unit DOES,
171 *  then one can not easily predict which tasks will use the FP hardware.
172 *  In this case, this option should be TRUE.
173 *
174 *  If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
175 */
176
177#define CPU_ALL_TASKS_ARE_FP     FALSE
178
179/*
180 *  Should the IDLE task have a floating point context?
181 *
182 *  If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
183 *  and it has a floating point context which is switched in and out.
184 *  If FALSE, then the IDLE task does not have a floating point context.
185 *
186 *  Setting this to TRUE negatively impacts the time required to preempt
187 *  the IDLE task from an interrupt because the floating point context
188 *  must be saved as part of the preemption.
189 */
190
191#define CPU_IDLE_TASK_IS_FP      FALSE
192
193/*
194 *  Should the saving of the floating point registers be deferred
195 *  until a context switch is made to another different floating point
196 *  task?
197 *
198 *  If TRUE, then the floating point context will not be stored until
199 *  necessary.  It will remain in the floating point registers and not
200 *  disturned until another floating point task is switched to.
201 *
202 *  If FALSE, then the floating point context is saved when a floating
203 *  point task is switched out and restored when the next floating point
204 *  task is restored.  The state of the floating point registers between
205 *  those two operations is not specified.
206 *
207 *  If the floating point context does NOT have to be saved as part of
208 *  interrupt dispatching, then it should be safe to set this to TRUE.
209 *
210 *  Setting this flag to TRUE results in using a different algorithm
211 *  for deciding when to save and restore the floating point context.
212 *  The deferred FP switch algorithm minimizes the number of times
213 *  the FP context is saved and restored.  The FP context is not saved
214 *  until a context switch is made to another, different FP task.
215 *  Thus in a system with only one FP task, the FP context will never
216 *  be saved or restored.
217 */
218
219#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
220
221/*
222 *  Does this port provide a CPU dependent IDLE task implementation?
223 *
224 *  If TRUE, then the routine _CPU_Thread_Idle_body
225 *  must be provided and is the default IDLE thread body instead of
226 *  _CPU_Thread_Idle_body.
227 *
228 *  If FALSE, then use the generic IDLE thread body if the BSP does
229 *  not provide one.
230 *
231 *  This is intended to allow for supporting processors which have
232 *  a low power or idle mode.  When the IDLE thread is executed, then
233 *  the CPU can be powered down.
234 *
235 *  The order of precedence for selecting the IDLE thread body is:
236 *
237 *    1.  BSP provided
238 *    2.  CPU dependent (if provided)
239 *    3.  generic (if no BSP and no CPU dependent)
240 */
241
242#define CPU_PROVIDES_IDLE_THREAD_BODY    TRUE
243
244/*
245 *  Does the stack grow up (toward higher addresses) or down
246 *  (toward lower addresses)?
247 *
248 *  If TRUE, then the grows upward.
249 *  If FALSE, then the grows toward smaller addresses.
250 */
251
252#if defined(__hppa__)
253#define CPU_STACK_GROWS_UP               TRUE
254#elif defined(__sparc__) || defined(__i386__)
255#define CPU_STACK_GROWS_UP               FALSE
256#else
257#error "unknown CPU!!"
258#endif
259
260
261/*
262 *  The following is the variable attribute used to force alignment
263 *  of critical RTEMS structures.  On some processors it may make
264 *  sense to have these aligned on tighter boundaries than
265 *  the minimum requirements of the compiler in order to have as
266 *  much of the critical data area as possible in a cache line.
267 *
268 *  The placement of this macro in the declaration of the variables
269 *  is based on the syntactically requirements of the GNU C
270 *  "__attribute__" extension.  For example with GNU C, use
271 *  the following to force a structures to a 32 byte boundary.
272 *
273 *      __attribute__ ((aligned (32)))
274 *
275 *  NOTE:  Currently only the Priority Bit Map table uses this feature.
276 *         To benefit from using this, the data must be heavily
277 *         used so it will stay in the cache and used frequently enough
278 *         in the executive to justify turning this on.
279 */
280
281#ifdef __GNUC__
282#define CPU_STRUCTURE_ALIGNMENT          __attribute__ ((aligned (32)))
283#else
284#define CPU_STRUCTURE_ALIGNMENT
285#endif
286
287/*
288 *  Define what is required to specify how the network to host conversion
289 *  routines are handled.
290 */
291
292#if defined(__hppa__) || defined(__sparc__)
293#define CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES     FALSE
294#define CPU_BIG_ENDIAN                           TRUE
295#define CPU_LITTLE_ENDIAN                        FALSE
296#elif defined(__i386__)
297#define CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES     FALSE
298#define CPU_BIG_ENDIAN                           FALSE
299#define CPU_LITTLE_ENDIAN                        TRUE
300#else
301#error "Unknown CPU!!!"
302#endif
303
304/*
305 *  The following defines the number of bits actually used in the
306 *  interrupt field of the task mode.  How those bits map to the
307 *  CPU interrupt levels is defined by the routine _CPU_ISR_Set_level().
308 */
309
310#define CPU_MODES_INTERRUPT_MASK   0x00000001
311
312#define CPU_NAME "UNIX"
313
314/*
315 *  Processor defined structures
316 *
317 *  Examples structures include the descriptor tables from the i386
318 *  and the processor control structure on the i960ca.
319 */
320
321/* may need to put some structures here.  */
322
323#if defined(__hppa__)
324/*
325 * Word indices within a jmp_buf structure
326 */
327
328#ifdef RTEMS_NEWLIB_SETJMP
329#define RP_OFF       6
330#define SP_OFF       2
331#define R3_OFF      10
332#define R4_OFF      11
333#define R5_OFF      12
334#define R6_OFF      13
335#define R7_OFF      14
336#define R8_OFF      15
337#define R9_OFF      16
338#define R10_OFF     17
339#define R11_OFF     18
340#define R12_OFF     19
341#define R13_OFF     20
342#define R14_OFF     21
343#define R15_OFF     22
344#define R16_OFF     23
345#define R17_OFF     24
346#define R18_OFF     25
347#define DP_OFF      26
348#endif
349
350#ifdef RTEMS_UNIXLIB_SETJMP
351#define RP_OFF       0
352#define SP_OFF       1
353#define R3_OFF       4
354#define R4_OFF       5
355#define R5_OFF       6
356#define R6_OFF       7
357#define R7_OFF       8
358#define R8_OFF       9
359#define R9_OFF      10
360#define R10_OFF     11
361#define R11_OFF     12
362#define R12_OFF     13
363#define R13_OFF     14
364#define R14_OFF     15
365#define R15_OFF     16
366#define R16_OFF     17
367#define R17_OFF     18
368#define R18_OFF     19
369#define DP_OFF      20
370#endif
371#endif
372
373#if defined(__i386__)
374 
375#ifdef RTEMS_NEWLIB
376#error "Newlib not installed"
377#endif
378 
379/*
380 *  For i386 targets
381 */
382 
383#ifdef RTEMS_UNIXLIB
384#if defined(__FreeBSD__)
385#define RET_OFF    0
386#define EBX_OFF    1
387#define EBP_OFF    2
388#define ESP_OFF    3
389#define ESI_OFF    4
390#define EDI_OFF    5
391#elif defined(__CYGWIN__)
392#define EAX_OFF    0
393#define EBX_OFF    1
394#define ECX_OFF    2
395#define EDX_OFF    3
396#define ESI_OFF    4
397#define EDI_OFF    5
398#define EBP_OFF    6
399#define ESP_OFF    7
400#define RET_OFF    8
401#else
402/* Linux */
403#define EBX_OFF    0
404#define ESI_OFF    1
405#define EDI_OFF    2
406#define EBP_OFF    3
407#define ESP_OFF    4
408#define RET_OFF    5
409#endif
410#endif
411 
412#endif
413 
414#if defined(__sparc__)
415
416/*
417 *  Word indices within a jmp_buf structure
418 */
419 
420#ifdef RTEMS_NEWLIB
421#define ADDR_ADJ_OFFSET -8
422#define SP_OFF    0
423#define RP_OFF    1
424#define FP_OFF    2
425#endif
426
427#ifdef RTEMS_UNIXLIB
428#define ADDR_ADJ_OFFSET 0
429#define G0_OFF    0
430#define SP_OFF    1
431#define RP_OFF    2   
432#define FP_OFF    3
433#define I7_OFF    4
434#endif
435
436#endif
437
438/*
439 * Contexts
440 *
441 *  Generally there are 2 types of context to save.
442 *     1. Interrupt registers to save
443 *     2. Task level registers to save
444 *
445 *  This means we have the following 3 context items:
446 *     1. task level context stuff::  Context_Control
447 *     2. floating point task stuff:: Context_Control_fp
448 *     3. special interrupt level context :: Context_Control_interrupt
449 *
450 *  On some processors, it is cost-effective to save only the callee
451 *  preserved registers during a task context switch.  This means
452 *  that the ISR code needs to save those registers which do not
453 *  persist across function calls.  It is not mandatory to make this
454 *  distinctions between the caller/callee saves registers for the
455 *  purpose of minimizing context saved during task switch and on interrupts.
456 *  If the cost of saving extra registers is minimal, simplicity is the
457 *  choice.  Save the same context on interrupt entry as for tasks in
458 *  this case.
459 *
460 *  Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
461 *  care should be used in designing the context area.
462 *
463 *  On some CPUs with hardware floating point support, the Context_Control_fp
464 *  structure will not be used or it simply consist of an array of a
465 *  fixed number of bytes.   This is done when the floating point context
466 *  is dumped by a "FP save context" type instruction and the format
467 *  is not really defined by the CPU.  In this case, there is no need
468 *  to figure out the exact format -- only the size.  Of course, although
469 *  this is enough information for RTEMS, it is probably not enough for
470 *  a debugger such as gdb.  But that is another problem.
471 */
472
473/*
474 *  This is really just the area for the following fields.
475 *
476 *    jmp_buf    regs;
477 *    unsigned32 isr_level;
478 *
479 *  Doing it this way avoids conflicts between the native stuff and the
480 *  RTEMS stuff.
481 *
482 *  NOTE:
483 *      hpux9 setjmp is optimized for the case where the setjmp buffer
484 *      is 8 byte aligned.  In a RISC world, this seems likely to enable
485 *      8 byte copies, especially for the float registers.
486 *      So we always align them on 8 byte boundaries.
487 */
488
489#ifdef __GNUC__
490#define CONTEXT_STRUCTURE_ALIGNMENT          __attribute__ ((aligned (8)))
491#else
492#define CONTEXT_STRUCTURE_ALIGNMENT
493#endif
494
495typedef struct {
496  char      Area[ CPU_CONTEXT_SIZE_IN_BYTES ] CONTEXT_STRUCTURE_ALIGNMENT;
497} Context_Control;
498
499typedef struct {
500} Context_Control_fp;
501
502typedef struct {
503} CPU_Interrupt_frame;
504
505
506/*
507 *  The following table contains the information required to configure
508 *  the UNIX Simulator specific parameters.
509 */
510
511typedef struct {
512  void       (*pretasking_hook)( void );
513  void       (*predriver_hook)( void );
514  void       (*postdriver_hook)( void );
515  void       (*idle_task)( void );
516  boolean      do_zero_of_workspace;
517  unsigned32   idle_task_stack_size;
518  unsigned32   interrupt_stack_size;
519  unsigned32   extra_mpci_receive_server_stack;
520  void *     (*stack_allocate_hook)( unsigned32 );
521  void       (*stack_free_hook)( void* );
522  /* end of required fields */
523}   rtems_cpu_table;
524
525/*
526 *  Macros to access required entires in the CPU Table are in
527 *  the file rtems/system.h.
528 */
529
530/*
531 *  Macros to access UNIX specific additions to the CPU Table
532 */
533
534/* There are no CPU specific additions to the CPU Table for this port. */
535
536/*
537 *  This variable is optional.  It is used on CPUs on which it is difficult
538 *  to generate an "uninitialized" FP context.  It is filled in by
539 *  _CPU_Initialize and copied into the task's FP context area during
540 *  _CPU_Context_Initialize.
541 */
542
543SCORE_EXTERN Context_Control_fp  _CPU_Null_fp_context;
544
545/*
546 *  On some CPUs, RTEMS supports a software managed interrupt stack.
547 *  This stack is allocated by the Interrupt Manager and the switch
548 *  is performed in _ISR_Handler.  These variables contain pointers
549 *  to the lowest and highest addresses in the chunk of memory allocated
550 *  for the interrupt stack.  Since it is unknown whether the stack
551 *  grows up or down (in general), this give the CPU dependent
552 *  code the option of picking the version it wants to use.
553 *
554 *  NOTE: These two variables are required if the macro
555 *        CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
556 */
557
558SCORE_EXTERN void               *_CPU_Interrupt_stack_low;
559SCORE_EXTERN void               *_CPU_Interrupt_stack_high;
560
561/*
562 *  With some compilation systems, it is difficult if not impossible to
563 *  call a high-level language routine from assembly language.  This
564 *  is especially true of commercial Ada compilers and name mangling
565 *  C++ ones.  This variable can be optionally defined by the CPU porter
566 *  and contains the address of the routine _Thread_Dispatch.  This
567 *  can make it easier to invoke that routine at the end of the interrupt
568 *  sequence (if a dispatch is necessary).
569 */
570
571SCORE_EXTERN void           (*_CPU_Thread_dispatch_pointer)();
572
573/*
574 *  Nothing prevents the porter from declaring more CPU specific variables.
575 */
576
577/* XXX: if needed, put more variables here */
578
579/*
580 *  The size of the floating point context area.  On some CPUs this
581 *  will not be a "sizeof" because the format of the floating point
582 *  area is not defined -- only the size is.  This is usually on
583 *  CPUs with a "floating point save context" instruction.
584 */
585
586#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
587
588/*
589 * The size of a frame on the stack
590 */
591
592#if defined(__hppa__)
593#define CPU_FRAME_SIZE  (32 * 4)
594#elif defined(__sparc__)
595#define CPU_FRAME_SIZE  (112)   /* based on disassembled test code */
596#elif defined(__i386__)
597#define CPU_FRAME_SIZE  (24)  /* return address, sp, and bp pushed plus fudge */
598#else
599#error "Unknown CPU!!!"
600#endif
601
602/*
603 *  Amount of extra stack (above minimum stack size) required by
604 *  MPCI receive server thread.  Remember that in a multiprocessor
605 *  system this thread must exist and be able to process all directives.
606 */
607
608#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
609
610/*
611 *  This defines the number of entries in the ISR_Vector_table managed
612 *  by RTEMS.
613 */
614
615#define CPU_INTERRUPT_NUMBER_OF_VECTORS      64
616#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
617
618/*
619 *  Should be large enough to run all RTEMS tests.  This insures
620 *  that a "reasonable" small application should not have any problems.
621 */
622
623#define CPU_STACK_MINIMUM_SIZE          (16 * 1024)
624
625/*
626 *  CPU's worst alignment requirement for data types on a byte boundary.  This
627 *  alignment does not take into account the requirements for the stack.
628 */
629
630#define CPU_ALIGNMENT              8
631
632/*
633 *  This number corresponds to the byte alignment requirement for the
634 *  heap handler.  This alignment requirement may be stricter than that
635 *  for the data types alignment specified by CPU_ALIGNMENT.  It is
636 *  common for the heap to follow the same alignment requirement as
637 *  CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict enough for the heap,
638 *  then this should be set to CPU_ALIGNMENT.
639 *
640 *  NOTE:  This does not have to be a power of 2.  It does have to
641 *         be greater or equal to than CPU_ALIGNMENT.
642 */
643
644#define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT
645
646/*
647 *  This number corresponds to the byte alignment requirement for memory
648 *  buffers allocated by the partition manager.  This alignment requirement
649 *  may be stricter than that for the data types alignment specified by
650 *  CPU_ALIGNMENT.  It is common for the partition to follow the same
651 *  alignment requirement as CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict
652 *  enough for the partition, then this should be set to CPU_ALIGNMENT.
653 *
654 *  NOTE:  This does not have to be a power of 2.  It does have to
655 *         be greater or equal to than CPU_ALIGNMENT.
656 */
657
658#define CPU_PARTITION_ALIGNMENT    CPU_ALIGNMENT
659
660/*
661 *  This number corresponds to the byte alignment requirement for the
662 *  stack.  This alignment requirement may be stricter than that for the
663 *  data types alignment specified by CPU_ALIGNMENT.  If the CPU_ALIGNMENT
664 *  is strict enough for the stack, then this should be set to 0.
665 *
666 *  NOTE:  This must be a power of 2 either 0 or greater than CPU_ALIGNMENT.
667 */
668
669#define CPU_STACK_ALIGNMENT        64
670
671/*
672 *  ISR handler macros
673 */
674
675/*
676 *  Support routine to initialize the RTEMS vector table after it is allocated.
677 */
678
679void _CPU_Initialize_vectors(void);
680
681/*
682 *  Disable all interrupts for an RTEMS critical section.  The previous
683 *  level is returned in _level.
684 */
685
686extern unsigned32 _CPU_ISR_Disable_support(void);
687
688#define _CPU_ISR_Disable( _level ) \
689    do { \
690      (_level) = _CPU_ISR_Disable_support(); \
691    } while ( 0 )
692
693/*
694 *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
695 *  This indicates the end of an RTEMS critical section.  The parameter
696 *  _level is not modified.
697 */
698
699void _CPU_ISR_Enable(unsigned32 level);
700
701/*
702 *  This temporarily restores the interrupt to _level before immediately
703 *  disabling them again.  This is used to divide long RTEMS critical
704 *  sections into two or more parts.  The parameter _level is not
705 * modified.
706 */
707
708#define _CPU_ISR_Flash( _level ) \
709  do { \
710      register unsigned32 _ignored = 0; \
711      _CPU_ISR_Enable( (_level) ); \
712      _CPU_ISR_Disable( _ignored ); \
713  } while ( 0 )
714
715/*
716 *  Map interrupt level in task mode onto the hardware that the CPU
717 *  actually provides.  Currently, interrupt levels which do not
718 *  map onto the CPU in a generic fashion are undefined.  Someday,
719 *  it would be nice if these were "mapped" by the application
720 *  via a callout.  For example, m68k has 8 levels 0 - 7, levels
721 *  8 - 255 would be available for bsp/application specific meaning.
722 *  This could be used to manage a programmable interrupt controller
723 *  via the rtems_task_mode directive.
724 */
725
726#define _CPU_ISR_Set_level( new_level ) \
727  { \
728    if ( new_level == 0 ) _CPU_ISR_Enable( 0 ); \
729    else                  _CPU_ISR_Enable( 1 ); \
730  }
731
732unsigned32 _CPU_ISR_Get_level( void );
733
734/* end of ISR handler macros */
735
736/* Context handler macros */
737
738/*
739 *  This routine is responsible for somehow restarting the currently
740 *  executing task.  If you are lucky, then all that is necessary
741 *  is restoring the context.  Otherwise, there will need to be
742 *  a special assembly routine which does something special in this
743 *  case.  Context_Restore should work most of the time.  It will
744 *  not work if restarting self conflicts with the stack frame
745 *  assumptions of restoring a context.
746 */
747
748#define _CPU_Context_Restart_self( _the_context ) \
749   _CPU_Context_restore( (_the_context) );
750
751/*
752 *  The purpose of this macro is to allow the initial pointer into
753 *  a floating point context area (used to save the floating point
754 *  context) to be at an arbitrary place in the floating point
755 *  context area.
756 *
757 *  This is necessary because some FP units are designed to have
758 *  their context saved as a stack which grows into lower addresses.
759 *  Other FP units can be saved by simply moving registers into offsets
760 *  from the base of the context area.  Finally some FP units provide
761 *  a "dump context" instruction which could fill in from high to low
762 *  or low to high based on the whim of the CPU designers.
763 */
764
765#define _CPU_Context_Fp_start( _base, _offset ) \
766   ( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
767
768/*
769 *  This routine initializes the FP context area passed to it to.
770 *  There are a few standard ways in which to initialize the
771 *  floating point context.  The code included for this macro assumes
772 *  that this is a CPU in which a "initial" FP context was saved into
773 *  _CPU_Null_fp_context and it simply copies it to the destination
774 *  context passed to it.
775 *
776 *  Other models include (1) not doing anything, and (2) putting
777 *  a "null FP status word" in the correct place in the FP context.
778 */
779
780#define _CPU_Context_Initialize_fp( _destination ) \
781  { \
782   *((Context_Control_fp *) *((void **) _destination)) = _CPU_Null_fp_context; \
783  }
784
785#define _CPU_Context_save_fp( _fp_context ) \
786    _CPU_Save_float_context( *(Context_Control_fp **)(_fp_context))
787
788#define _CPU_Context_restore_fp( _fp_context ) \
789    _CPU_Restore_float_context( *(Context_Control_fp **)(_fp_context))
790
791extern void _CPU_Context_Initialize(
792  Context_Control  *_the_context,
793  unsigned32       *_stack_base,
794  unsigned32        _size,
795  unsigned32        _new_level,
796  void             *_entry_point,
797  boolean           _is_fp
798);
799
800/* end of Context handler macros */
801
802/* Fatal Error manager macros */
803
804/*
805 *  This routine copies _error into a known place -- typically a stack
806 *  location or a register, optionally disables interrupts, and
807 *  halts/stops the CPU.
808 */
809
810#define _CPU_Fatal_halt( _error ) \
811    _CPU_Fatal_error( _error )
812
813/* end of Fatal Error manager macros */
814
815/* Bitfield handler macros */
816
817/*
818 *  This routine sets _output to the bit number of the first bit
819 *  set in _value.  _value is of CPU dependent type Priority_Bit_map_control.
820 *  This type may be either 16 or 32 bits wide although only the 16
821 *  least significant bits will be used.
822 *
823 *  There are a number of variables in using a "find first bit" type
824 *  instruction.
825 *
826 *    (1) What happens when run on a value of zero?
827 *    (2) Bits may be numbered from MSB to LSB or vice-versa.
828 *    (3) The numbering may be zero or one based.
829 *    (4) The "find first bit" instruction may search from MSB or LSB.
830 *
831 *  RTEMS guarantees that (1) will never happen so it is not a concern.
832 *  (2),(3), (4) are handled by the macros _CPU_Priority_mask() and
833 *  _CPU_Priority_bits_index().  These three form a set of routines
834 *  which must logically operate together.  Bits in the _value are
835 *  set and cleared based on masks built by _CPU_Priority_mask().
836 *  The basic major and minor values calculated by _Priority_Major()
837 *  and _Priority_Minor() are "massaged" by _CPU_Priority_bits_index()
838 *  to properly range between the values returned by the "find first bit"
839 *  instruction.  This makes it possible for _Priority_Get_highest() to
840 *  calculate the major and directly index into the minor table.
841 *  This mapping is necessary to ensure that 0 (a high priority major/minor)
842 *  is the first bit found.
843 *
844 *  This entire "find first bit" and mapping process depends heavily
845 *  on the manner in which a priority is broken into a major and minor
846 *  components with the major being the 4 MSB of a priority and minor
847 *  the 4 LSB.  Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
848 *  priority.  And (15 << 4) + 14 corresponds to priority 254 -- the next
849 *  to the lowest priority.
850 *
851 *  If your CPU does not have a "find first bit" instruction, then
852 *  there are ways to make do without it.  Here are a handful of ways
853 *  to implement this in software:
854 *
855 *    - a series of 16 bit test instructions
856 *    - a "binary search using if's"
857 *    - _number = 0
858 *      if _value > 0x00ff
859 *        _value >>=8
860 *        _number = 8;
861 *
862 *      if _value > 0x0000f
863 *        _value >=8
864 *        _number += 4
865 *
866 *      _number += bit_set_table[ _value ]
867 *
868 *    where bit_set_table[ 16 ] has values which indicate the first
869 *      bit set
870 */
871
872/*
873 *  The UNIX port uses the generic C algorithm for bitfield scan to avoid
874 *  dependencies on either a native bitscan instruction or an ffs() in the
875 *  C library.
876 */
877 
878#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
879#define CPU_USE_GENERIC_BITFIELD_DATA TRUE
880 
881/* end of Bitfield handler macros */
882 
883/* Priority handler handler macros */
884 
885/*
886 *  The UNIX port uses the generic C algorithm for bitfield scan to avoid
887 *  dependencies on either a native bitscan instruction or an ffs() in the
888 *  C library.
889 */
890 
891/* end of Priority handler macros */
892
893/* functions */
894
895/*
896 *  _CPU_Initialize
897 *
898 *  This routine performs CPU dependent initialization.
899 */
900
901void _CPU_Initialize(
902  rtems_cpu_table  *cpu_table,
903  void      (*thread_dispatch)
904);
905
906/*
907 *  _CPU_ISR_install_raw_handler
908 *
909 *  This routine installs a "raw" interrupt handler directly into the
910 *  processor's vector table.
911 */
912 
913void _CPU_ISR_install_raw_handler(
914  unsigned32  vector,
915  proc_ptr    new_handler,
916  proc_ptr   *old_handler
917);
918
919/*
920 *  _CPU_ISR_install_vector
921 *
922 *  This routine installs an interrupt vector.
923 */
924
925void _CPU_ISR_install_vector(
926  unsigned32  vector,
927  proc_ptr    new_handler,
928  proc_ptr   *old_handler
929);
930
931/*
932 *  _CPU_Install_interrupt_stack
933 *
934 *  This routine installs the hardware interrupt stack pointer.
935 *
936 *  NOTE:  It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK
937 *         is TRUE.
938 */
939
940void _CPU_Install_interrupt_stack( void );
941
942/*
943 *  _CPU_Thread_Idle_body
944 *
945 *  This routine is the CPU dependent IDLE thread body.
946 *
947 *  NOTE:  It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY
948 *         is TRUE.
949 */
950
951void _CPU_Thread_Idle_body( void );
952
953/*
954 *  _CPU_Context_switch
955 *
956 *  This routine switches from the run context to the heir context.
957 */
958
959void _CPU_Context_switch(
960  Context_Control  *run,
961  Context_Control  *heir
962);
963
964/*
965 *  _CPU_Context_restore
966 *
967 *  This routine is generally used only to restart self in an
968 *  efficient manner.  It may simply be a label in _CPU_Context_switch.
969 *
970 *  NOTE: May be unnecessary to reload some registers.
971 */
972
973void _CPU_Context_restore(
974  Context_Control *new_context
975);
976
977/*
978 *  _CPU_Save_float_context
979 *
980 *  This routine saves the floating point context passed to it.
981 */
982
983void _CPU_Save_float_context(
984  Context_Control_fp *fp_context_ptr
985);
986
987/*
988 *  _CPU_Restore_float_context
989 *
990 *  This routine restores the floating point context passed to it.
991 */
992
993void _CPU_Restore_float_context(
994  Context_Control_fp *fp_context_ptr
995);
996
997
998void _CPU_ISR_Set_signal_level(
999  unsigned32 level
1000);
1001
1002void _CPU_Fatal_error(
1003  unsigned32 _error
1004);
1005
1006/*  The following routine swaps the endian format of an unsigned int.
1007 *  It must be static because it is referenced indirectly.
1008 *
1009 *  This version will work on any processor, but if there is a better
1010 *  way for your CPU PLEASE use it.  The most common way to do this is to:
1011 *
1012 *     swap least significant two bytes with 16-bit rotate
1013 *     swap upper and lower 16-bits
1014 *     swap most significant two bytes with 16-bit rotate
1015 *
1016 *  Some CPUs have special instructions which swap a 32-bit quantity in
1017 *  a single instruction (e.g. i486).  It is probably best to avoid
1018 *  an "endian swapping control bit" in the CPU.  One good reason is
1019 *  that interrupts would probably have to be disabled to insure that
1020 *  an interrupt does not try to access the same "chunk" with the wrong
1021 *  endian.  Another good reason is that on some CPUs, the endian bit
1022 *  endianness for ALL fetches -- both code and data -- so the code
1023 *  will be fetched incorrectly.
1024 */
1025 
1026static inline unsigned int CPU_swap_u32(
1027  unsigned int value
1028)
1029{
1030  unsigned32 byte1, byte2, byte3, byte4, swapped;
1031 
1032  byte4 = (value >> 24) & 0xff;
1033  byte3 = (value >> 16) & 0xff;
1034  byte2 = (value >> 8)  & 0xff;
1035  byte1 =  value        & 0xff;
1036 
1037  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
1038  return( swapped );
1039}
1040
1041#define CPU_swap_u16( value ) \
1042  (((value&0xff) << 8) | ((value >> 8)&0xff))
1043
1044/*
1045 *  Special Purpose Routines to hide the use of UNIX system calls.
1046 */
1047
1048
1049/*
1050 *  Pointer to a sync io  Handler
1051 */
1052
1053typedef void ( *rtems_sync_io_handler )(
1054  int fd,
1055  boolean read,
1056  boolean wrtie,
1057  boolean except
1058);
1059
1060/* returns -1 if fd to large, 0 is successful */
1061int _CPU_Set_sync_io_handler(
1062  int fd,
1063  boolean read,
1064  boolean write,
1065  boolean except,
1066  rtems_sync_io_handler handler
1067);
1068
1069/* returns -1 if fd to large, o if successful */
1070int _CPU_Clear_sync_io_handler(
1071  int fd
1072);
1073
1074int _CPU_Get_clock_vector( void );
1075
1076void _CPU_Start_clock( 
1077  int microseconds
1078);
1079
1080void _CPU_Stop_clock( void );
1081
1082#if defined(RTEMS_MULTIPROCESSING)
1083
1084void _CPU_SHM_Init( 
1085  unsigned32   maximum_nodes,
1086  boolean      is_master_node,
1087  void       **shm_address,
1088  unsigned32  *shm_length
1089);
1090
1091int _CPU_Get_pid( void );
1092 
1093int _CPU_SHM_Get_vector( void );
1094 
1095void _CPU_SHM_Send_interrupt(
1096  int pid,
1097  int vector
1098);
1099 
1100void _CPU_SHM_Lock( 
1101  int semaphore
1102);
1103
1104void _CPU_SHM_Unlock(
1105  int semaphore
1106);
1107#endif
1108
1109#ifdef __cplusplus
1110}
1111#endif
1112
1113#endif
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