source: rtems/c/src/exec/score/cpu/unix/cpu.h @ 84ee59f5

4.104.114.84.95
Last change on this file since 84ee59f5 was 84ee59f5, checked in by Joel Sherrill <joel.sherrill@…>, on Sep 19, 1995 at 9:42:27 PM

Removed a section of code which was "#if 0"'ed.

  • Property mode set to 100644
File size: 29.8 KB
Line 
1/*  cpu.h
2 *
3 *  This include file contains information pertaining to the HP
4 *  PA-RISC processor (Level 1.1).
5 *
6 *  COPYRIGHT (c) 1994 by Division Incorporated
7 *
8 *  To anyone who acknowledges that this file is provided "AS IS"
9 *  without any express or implied warranty:
10 *      permission to use, copy, modify, and distribute this file
11 *      for any purpose is hereby granted without fee, provided that
12 *      the above copyright notice and this notice appears in all
13 *      copies, and that the name of Division Incorporated not be
14 *      used in advertising or publicity pertaining to distribution
15 *      of the software without specific, written prior permission.
16 *      Division Incorporated makes no representations about the
17 *      suitability of this software for any purpose.
18 *
19 *  $Id$
20 */
21
22#ifndef __CPU_h
23#define __CPU_h
24
25#ifdef __cplusplus
26extern "C" {
27#endif
28
29#include <rtems/core/unix.h>
30#ifndef ASM
31#include <rtems/core/unixtypes.h>
32#endif
33
34#if defined(solaris2)
35#undef  _POSIX_C_SOURCE
36#define _POSIX_C_SOURCE 3
37#undef  __STRICT_ANSI__
38#define __STRICT_ANSI__
39#endif
40
41#if defined(linux)
42#define MALLOC_0_RETURNS_NULL
43#endif
44
45#include <unistd.h>
46#include <setjmp.h>
47#include <signal.h>
48
49/* conditional compilation parameters */
50
51/*
52 *  Should the calls to _Thread_Enable_dispatch be inlined?
53 *
54 *  If TRUE, then they are inlined.
55 *  If FALSE, then a subroutine call is made.
56 *
57 *  Basically this is an example of the classic trade-off of size
58 *  versus speed.  Inlining the call (TRUE) typically increases the
59 *  size of RTEMS while speeding up the enabling of dispatching.
60 *  [NOTE: In general, the _Thread_Dispatch_disable_level will
61 *  only be 0 or 1 unless you are in an interrupt handler and that
62 *  interrupt handler invokes the executive.]  When not inlined
63 *  something calls _Thread_Enable_dispatch which in turns calls
64 *  _Thread_Dispatch.  If the enable dispatch is inlined, then
65 *  one subroutine call is avoided entirely.]
66 */
67
68#define CPU_INLINE_ENABLE_DISPATCH       FALSE
69
70/*
71 *  Should the body of the search loops in _Thread_queue_Enqueue_priority
72 *  be unrolled one time?  In unrolled each iteration of the loop examines
73 *  two "nodes" on the chain being searched.  Otherwise, only one node
74 *  is examined per iteration.
75 *
76 *  If TRUE, then the loops are unrolled.
77 *  If FALSE, then the loops are not unrolled.
78 *
79 *  The primary factor in making this decision is the cost of disabling
80 *  and enabling interrupts (_ISR_Flash) versus the cost of rest of the
81 *  body of the loop.  On some CPUs, the flash is more expensive than
82 *  one iteration of the loop body.  In this case, it might be desirable
83 *  to unroll the loop.  It is important to note that on some CPUs, this
84 *  code is the longest interrupt disable period in RTEMS.  So it is
85 *  necessary to strike a balance when setting this parameter.
86 */
87
88#define CPU_UNROLL_ENQUEUE_PRIORITY      TRUE
89
90/*
91 *  Does RTEMS manage a dedicated interrupt stack in software?
92 *
93 *  If TRUE, then a stack is allocated in _Interrupt_Manager_initialization.
94 *  If FALSE, nothing is done.
95 *
96 *  If the CPU supports a dedicated interrupt stack in hardware,
97 *  then it is generally the responsibility of the BSP to allocate it
98 *  and set it up.
99 *
100 *  If the CPU does not support a dedicated interrupt stack, then
101 *  the porter has two options: (1) execute interrupts on the
102 *  stack of the interrupted task, and (2) have RTEMS manage a dedicated
103 *  interrupt stack.
104 *
105 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
106 *
107 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
108 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
109 *  possible that both are FALSE for a particular CPU.  Although it
110 *  is unclear what that would imply about the interrupt processing
111 *  procedure on that CPU.
112 */
113
114#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE
115
116/*
117 *  Does this CPU have hardware support for a dedicated interrupt stack?
118 *
119 *  If TRUE, then it must be installed during initialization.
120 *  If FALSE, then no installation is performed.
121 *
122 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
123 *
124 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
125 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
126 *  possible that both are FALSE for a particular CPU.  Although it
127 *  is unclear what that would imply about the interrupt processing
128 *  procedure on that CPU.
129 */
130
131#define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE
132
133/*
134 *  Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
135 *
136 *  If TRUE, then the memory is allocated during initialization.
137 *  If FALSE, then the memory is allocated during initialization.
138 *
139 *  This should be TRUE if CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE
140 *  or CPU_INSTALL_HARDWARE_INTERRUPT_STACK is TRUE.
141 */
142
143#define CPU_ALLOCATE_INTERRUPT_STACK FALSE
144
145/*
146 *  Does the CPU have hardware floating point?
147 *
148 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
149 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
150 *
151 *  If there is a FP coprocessor such as the i387 or mc68881, then
152 *  the answer is TRUE.
153 *
154 *  The macro name "NO_CPU_HAS_FPU" should be made CPU specific.
155 *  It indicates whether or not this CPU model has FP support.  For
156 *  example, it would be possible to have an i386_nofp CPU model
157 *  which set this to false to indicate that you have an i386 without
158 *  an i387 and wish to leave floating point support out of RTEMS.
159 */
160
161#define CPU_HARDWARE_FP     TRUE
162
163/*
164 *  Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
165 *
166 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
167 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
168 *
169 *  So far, the only CPU in which this option has been used is the
170 *  HP PA-RISC.  The HP C compiler and gcc both implicitly use the
171 *  floating point registers to perform integer multiplies.  If
172 *  a function which you would not think utilize the FP unit DOES,
173 *  then one can not easily predict which tasks will use the FP hardware.
174 *  In this case, this option should be TRUE.
175 *
176 *  If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
177 */
178
179#define CPU_ALL_TASKS_ARE_FP     FALSE
180
181/*
182 *  Should the IDLE task have a floating point context?
183 *
184 *  If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
185 *  and it has a floating point context which is switched in and out.
186 *  If FALSE, then the IDLE task does not have a floating point context.
187 *
188 *  Setting this to TRUE negatively impacts the time required to preempt
189 *  the IDLE task from an interrupt because the floating point context
190 *  must be saved as part of the preemption.
191 */
192
193#define CPU_IDLE_TASK_IS_FP      FALSE
194
195/*
196 *  Should the saving of the floating point registers be deferred
197 *  until a context switch is made to another different floating point
198 *  task?
199 *
200 *  If TRUE, then the floating point context will not be stored until
201 *  necessary.  It will remain in the floating point registers and not
202 *  disturned until another floating point task is switched to.
203 *
204 *  If FALSE, then the floating point context is saved when a floating
205 *  point task is switched out and restored when the next floating point
206 *  task is restored.  The state of the floating point registers between
207 *  those two operations is not specified.
208 *
209 *  If the floating point context does NOT have to be saved as part of
210 *  interrupt dispatching, then it should be safe to set this to TRUE.
211 *
212 *  Setting this flag to TRUE results in using a different algorithm
213 *  for deciding when to save and restore the floating point context.
214 *  The deferred FP switch algorithm minimizes the number of times
215 *  the FP context is saved and restored.  The FP context is not saved
216 *  until a context switch is made to another, different FP task.
217 *  Thus in a system with only one FP task, the FP context will never
218 *  be saved or restored.
219 */
220
221#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
222
223/*
224 *  Does this port provide a CPU dependent IDLE task implementation?
225 *
226 *  If TRUE, then the routine _CPU_Internal_threads_Idle_thread_body
227 *  must be provided and is the default IDLE thread body instead of
228 *  _Internal_threads_Idle_thread_body.
229 *
230 *  If FALSE, then use the generic IDLE thread body if the BSP does
231 *  not provide one.
232 *
233 *  This is intended to allow for supporting processors which have
234 *  a low power or idle mode.  When the IDLE thread is executed, then
235 *  the CPU can be powered down.
236 *
237 *  The order of precedence for selecting the IDLE thread body is:
238 *
239 *    1.  BSP provided
240 *    2.  CPU dependent (if provided)
241 *    3.  generic (if no BSP and no CPU dependent)
242 */
243
244#define CPU_PROVIDES_IDLE_THREAD_BODY    TRUE
245
246/*
247 *  Does the stack grow up (toward higher addresses) or down
248 *  (toward lower addresses)?
249 *
250 *  If TRUE, then the grows upward.
251 *  If FALSE, then the grows toward smaller addresses.
252 */
253
254#if defined(hppa1_1)
255#define CPU_STACK_GROWS_UP               TRUE
256#elif defined(sparc) || defined(i386)
257#define CPU_STACK_GROWS_UP               FALSE
258#else
259#error "unknown CPU!!"
260#endif
261
262
263/*
264 *  The following is the variable attribute used to force alignment
265 *  of critical RTEMS structures.  On some processors it may make
266 *  sense to have these aligned on tighter boundaries than
267 *  the minimum requirements of the compiler in order to have as
268 *  much of the critical data area as possible in a cache line.
269 *
270 *  The placement of this macro in the declaration of the variables
271 *  is based on the syntactically requirements of the GNU C
272 *  "__attribute__" extension.  For example with GNU C, use
273 *  the following to force a structures to a 32 byte boundary.
274 *
275 *      __attribute__ ((aligned (32)))
276 *
277 *  NOTE:  Currently only the Priority Bit Map table uses this feature.
278 *         To benefit from using this, the data must be heavily
279 *         used so it will stay in the cache and used frequently enough
280 *         in the executive to justify turning this on.
281 */
282
283#define CPU_STRUCTURE_ALIGNMENT          __attribute__ ((aligned (32)))
284
285/*
286 *  The following defines the number of bits actually used in the
287 *  interrupt field of the task mode.  How those bits map to the
288 *  CPU interrupt levels is defined by the routine _CPU_ISR_Set_level().
289 */
290
291#define CPU_MODES_INTERRUPT_MASK   0x00000001
292
293#define CPU_NAME "UNIX"
294
295/*
296 *  Processor defined structures
297 *
298 *  Examples structures include the descriptor tables from the i386
299 *  and the processor control structure on the i960ca.
300 */
301
302/* may need to put some structures here.  */
303
304#if defined(hppa1_1)
305/*
306 * Word indices within a jmp_buf structure
307 */
308
309#ifdef RTEMS_NEWLIB_SETJMP
310#define RP_OFF       6
311#define SP_OFF       2
312#define R3_OFF      10
313#define R4_OFF      11
314#define R5_OFF      12
315#define R6_OFF      13
316#define R7_OFF      14
317#define R8_OFF      15
318#define R9_OFF      16
319#define R10_OFF     17
320#define R11_OFF     18
321#define R12_OFF     19
322#define R13_OFF     20
323#define R14_OFF     21
324#define R15_OFF     22
325#define R16_OFF     23
326#define R17_OFF     24
327#define R18_OFF     25
328#define DP_OFF      26
329#endif
330
331#ifdef RTEMS_UNIXLIB_SETJMP
332#define RP_OFF       0
333#define SP_OFF       1
334#define R3_OFF       4
335#define R4_OFF       5
336#define R5_OFF       6
337#define R6_OFF       7
338#define R7_OFF       8
339#define R8_OFF       9
340#define R9_OFF      10
341#define R10_OFF     11
342#define R11_OFF     12
343#define R12_OFF     13
344#define R13_OFF     14
345#define R14_OFF     15
346#define R15_OFF     16
347#define R16_OFF     17
348#define R17_OFF     18
349#define R18_OFF     19
350#define DP_OFF      20
351#endif
352#endif
353
354#if defined(i386)
355 
356#ifdef RTEMS_NEWLIB
357#error "Newlib not installed"
358#endif
359 
360/*
361 *  For Linux 1.1
362 */
363 
364#ifdef RTEMS_UNIXLIB
365#define EBX_OFF    0
366#define ESI_OFF    1
367#define EDI_OFF    2
368#define EBP_OFF    3
369#define ESP_OFF    4
370#define RET_OFF    5
371#endif
372 
373#endif
374 
375#if defined(sparc)
376
377/*
378 *  Word indices within a jmp_buf structure
379 */
380 
381#ifdef RTEMS_NEWLIB
382#define ADDR_ADJ_OFFSET -8
383#define SP_OFF    0
384#define RP_OFF    1
385#define FP_OFF    2
386#endif
387
388#ifdef RTEMS_UNIXLIB
389#define ADDR_ADJ_OFFSET 0
390#define G0_OFF    0
391#define SP_OFF    1
392#define RP_OFF    2   
393#define FP_OFF    3
394#define I7_OFF    4
395#endif
396
397#endif
398
399/*
400 * Contexts
401 *
402 *  Generally there are 2 types of context to save.
403 *     1. Interrupt registers to save
404 *     2. Task level registers to save
405 *
406 *  This means we have the following 3 context items:
407 *     1. task level context stuff::  Context_Control
408 *     2. floating point task stuff:: Context_Control_fp
409 *     3. special interrupt level context :: Context_Control_interrupt
410 *
411 *  On some processors, it is cost-effective to save only the callee
412 *  preserved registers during a task context switch.  This means
413 *  that the ISR code needs to save those registers which do not
414 *  persist across function calls.  It is not mandatory to make this
415 *  distinctions between the caller/callee saves registers for the
416 *  purpose of minimizing context saved during task switch and on interrupts.
417 *  If the cost of saving extra registers is minimal, simplicity is the
418 *  choice.  Save the same context on interrupt entry as for tasks in
419 *  this case.
420 *
421 *  Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
422 *  care should be used in designing the context area.
423 *
424 *  On some CPUs with hardware floating point support, the Context_Control_fp
425 *  structure will not be used or it simply consist of an array of a
426 *  fixed number of bytes.   This is done when the floating point context
427 *  is dumped by a "FP save context" type instruction and the format
428 *  is not really defined by the CPU.  In this case, there is no need
429 *  to figure out the exact format -- only the size.  Of course, although
430 *  this is enough information for RTEMS, it is probably not enough for
431 *  a debugger such as gdb.  But that is another problem.
432 */
433
434typedef struct {
435  jmp_buf   regs;
436  sigset_t  isr_level;
437} Context_Control;
438
439typedef struct {
440} Context_Control_fp;
441
442typedef struct {
443} CPU_Interrupt_frame;
444
445
446/*
447 *  The following table contains the information required to configure
448 *  the XXX processor specific parameters.
449 *
450 *  NOTE: The interrupt_stack_size field is required if
451 *        CPU_ALLOCATE_INTERRUPT_STACK is defined as TRUE.
452 *
453 *        The pretasking_hook, predriver_hook, and postdriver_hook,
454 *        and the do_zero_of_workspace fields are required on ALL CPUs.
455 */
456
457typedef struct {
458  void       (*pretasking_hook)( void );
459  void       (*predriver_hook)( void );
460  void       (*postdriver_hook)( void );
461  void       (*idle_task)( void );
462  boolean      do_zero_of_workspace;
463  unsigned32   interrupt_stack_size;
464  unsigned32   extra_system_initialization_stack;
465}   rtems_cpu_table;
466
467/*
468 *  This variable is optional.  It is used on CPUs on which it is difficult
469 *  to generate an "uninitialized" FP context.  It is filled in by
470 *  _CPU_Initialize and copied into the task's FP context area during
471 *  _CPU_Context_Initialize.
472 */
473
474EXTERN Context_Control_fp  _CPU_Null_fp_context;
475
476/*
477 *  On some CPUs, RTEMS supports a software managed interrupt stack.
478 *  This stack is allocated by the Interrupt Manager and the switch
479 *  is performed in _ISR_Handler.  These variables contain pointers
480 *  to the lowest and highest addresses in the chunk of memory allocated
481 *  for the interrupt stack.  Since it is unknown whether the stack
482 *  grows up or down (in general), this give the CPU dependent
483 *  code the option of picking the version it wants to use.
484 *
485 *  NOTE: These two variables are required if the macro
486 *        CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
487 */
488
489EXTERN void               *_CPU_Interrupt_stack_low;
490EXTERN void               *_CPU_Interrupt_stack_high;
491
492/*
493 *  With some compilation systems, it is difficult if not impossible to
494 *  call a high-level language routine from assembly language.  This
495 *  is especially true of commercial Ada compilers and name mangling
496 *  C++ ones.  This variable can be optionally defined by the CPU porter
497 *  and contains the address of the routine _Thread_Dispatch.  This
498 *  can make it easier to invoke that routine at the end of the interrupt
499 *  sequence (if a dispatch is necessary).
500 */
501
502EXTERN void           (*_CPU_Thread_dispatch_pointer)();
503
504/*
505 *  Nothing prevents the porter from declaring more CPU specific variables.
506 */
507
508/* XXX: if needed, put more variables here */
509
510/*
511 *  The size of the floating point context area.  On some CPUs this
512 *  will not be a "sizeof" because the format of the floating point
513 *  area is not defined -- only the size is.  This is usually on
514 *  CPUs with a "floating point save context" instruction.
515 */
516
517#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
518
519/*
520 * The size of a frame on the stack
521 */
522
523#if defined(hppa1_1)
524#define CPU_FRAME_SIZE  (32 * 4)
525#elif defined(sparc)
526#define CPU_FRAME_SIZE  (112)   /* based on disassembled test code */
527#elif defined(i386)
528#define CPU_FRAME_SIZE  (24)  /* return address, sp, and bp pushed plus fudge */
529#else
530#error "Unknown CPU!!!"
531#endif
532
533/*
534 *  Amount of extra stack (above minimum stack size) required by
535 *  system initialization thread.  Remember that in a multiprocessor
536 *  system the system intialization thread becomes the MP server thread.
537 */
538
539#define CPU_SYSTEM_INITIALIZATION_THREAD_EXTRA_STACK 0
540
541/*
542 *  This defines the number of entries in the ISR_Vector_table managed
543 *  by RTEMS.
544 */
545
546#define CPU_INTERRUPT_NUMBER_OF_VECTORS  64
547
548/*
549 *  Should be large enough to run all RTEMS tests.  This insures
550 *  that a "reasonable" small application should not have any problems.
551 */
552
553#define CPU_STACK_MINIMUM_SIZE          (16 * 1024)
554
555/*
556 *  CPU's worst alignment requirement for data types on a byte boundary.  This
557 *  alignment does not take into account the requirements for the stack.
558 */
559
560#define CPU_ALIGNMENT              8
561
562/*
563 *  This number corresponds to the byte alignment requirement for the
564 *  heap handler.  This alignment requirement may be stricter than that
565 *  for the data types alignment specified by CPU_ALIGNMENT.  It is
566 *  common for the heap to follow the same alignment requirement as
567 *  CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict enough for the heap,
568 *  then this should be set to CPU_ALIGNMENT.
569 *
570 *  NOTE:  This does not have to be a power of 2.  It does have to
571 *         be greater or equal to than CPU_ALIGNMENT.
572 */
573
574#define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT
575
576/*
577 *  This number corresponds to the byte alignment requirement for memory
578 *  buffers allocated by the partition manager.  This alignment requirement
579 *  may be stricter than that for the data types alignment specified by
580 *  CPU_ALIGNMENT.  It is common for the partition to follow the same
581 *  alignment requirement as CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict
582 *  enough for the partition, then this should be set to CPU_ALIGNMENT.
583 *
584 *  NOTE:  This does not have to be a power of 2.  It does have to
585 *         be greater or equal to than CPU_ALIGNMENT.
586 */
587
588#define CPU_PARTITION_ALIGNMENT    CPU_ALIGNMENT
589
590/*
591 *  This number corresponds to the byte alignment requirement for the
592 *  stack.  This alignment requirement may be stricter than that for the
593 *  data types alignment specified by CPU_ALIGNMENT.  If the CPU_ALIGNMENT
594 *  is strict enough for the stack, then this should be set to 0.
595 *
596 *  NOTE:  This must be a power of 2 either 0 or greater than CPU_ALIGNMENT.
597 */
598
599#define CPU_STACK_ALIGNMENT        64
600
601/* ISR handler macros */
602
603/*
604 *  Disable all interrupts for an RTEMS critical section.  The previous
605 *  level is returned in _level.
606 */
607
608extern unsigned32 _CPU_ISR_Disable_support(void);
609
610#define _CPU_ISR_Disable( _level ) \
611    do { \
612      (_level) = _CPU_ISR_Disable_support(); \
613    } while ( 0 )
614
615/*
616 *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
617 *  This indicates the end of an RTEMS critical section.  The parameter
618 *  _level is not modified.
619 */
620
621void _CPU_ISR_Enable(unsigned32 level);
622
623/*
624 *  This temporarily restores the interrupt to _level before immediately
625 *  disabling them again.  This is used to divide long RTEMS critical
626 *  sections into two or more parts.  The parameter _level is not
627 * modified.
628 */
629
630#define _CPU_ISR_Flash( _level ) \
631  do { \
632      register _ignored = 0; \
633      _CPU_ISR_Enable( (_level) ); \
634      _CPU_ISR_Disable( _ignored ); \
635  } while ( 0 )
636
637/*
638 *  Map interrupt level in task mode onto the hardware that the CPU
639 *  actually provides.  Currently, interrupt levels which do not
640 *  map onto the CPU in a generic fashion are undefined.  Someday,
641 *  it would be nice if these were "mapped" by the application
642 *  via a callout.  For example, m68k has 8 levels 0 - 7, levels
643 *  8 - 255 would be available for bsp/application specific meaning.
644 *  This could be used to manage a programmable interrupt controller
645 *  via the rtems_task_mode directive.
646 */
647
648#define _CPU_ISR_Set_level( new_level ) \
649  { \
650    if ( new_level == 0 ) _CPU_ISR_Enable( 0 ); \
651    else                  _CPU_ISR_Enable( 1 ); \
652  }
653
654unsigned32 _CPU_ISR_Get_level( void );
655
656/* end of ISR handler macros */
657
658/* Context handler macros */
659
660/*
661 *  This routine is responsible for somehow restarting the currently
662 *  executing task.  If you are lucky, then all that is necessary
663 *  is restoring the context.  Otherwise, there will need to be
664 *  a special assembly routine which does something special in this
665 *  case.  Context_Restore should work most of the time.  It will
666 *  not work if restarting self conflicts with the stack frame
667 *  assumptions of restoring a context.
668 */
669
670#define _CPU_Context_Restart_self( _the_context ) \
671   _CPU_Context_restore( (_the_context) );
672
673/*
674 *  The purpose of this macro is to allow the initial pointer into
675 *  a floating point context area (used to save the floating point
676 *  context) to be at an arbitrary place in the floating point
677 *  context area.
678 *
679 *  This is necessary because some FP units are designed to have
680 *  their context saved as a stack which grows into lower addresses.
681 *  Other FP units can be saved by simply moving registers into offsets
682 *  from the base of the context area.  Finally some FP units provide
683 *  a "dump context" instruction which could fill in from high to low
684 *  or low to high based on the whim of the CPU designers.
685 */
686
687#define _CPU_Context_Fp_start( _base, _offset ) \
688   ( (void *) (_base) + (_offset) )
689
690/*
691 *  This routine initializes the FP context area passed to it to.
692 *  There are a few standard ways in which to initialize the
693 *  floating point context.  The code included for this macro assumes
694 *  that this is a CPU in which a "initial" FP context was saved into
695 *  _CPU_Null_fp_context and it simply copies it to the destination
696 *  context passed to it.
697 *
698 *  Other models include (1) not doing anything, and (2) putting
699 *  a "null FP status word" in the correct place in the FP context.
700 */
701
702#define _CPU_Context_Initialize_fp( _destination ) \
703  { \
704   *((Context_Control_fp *) *((void **) _destination)) = _CPU_Null_fp_context; \
705  }
706
707#define _CPU_Context_save_fp( _fp_context ) \
708    _CPU_Save_float_context( *(Context_Control_fp **)(_fp_context))
709
710#define _CPU_Context_restore_fp( _fp_context ) \
711    _CPU_Restore_float_context( *(Context_Control_fp **)(_fp_context))
712
713extern void _CPU_Context_Initialize(
714  Context_Control  *_the_context,
715  unsigned32       *_stack_base,
716  unsigned32        _size,
717  unsigned32        _new_level,
718  void             *_entry_point
719);
720
721/* end of Context handler macros */
722
723/* Fatal Error manager macros */
724
725/*
726 *  This routine copies _error into a known place -- typically a stack
727 *  location or a register, optionally disables interrupts, and
728 *  halts/stops the CPU.
729 */
730
731#define _CPU_Fatal_halt( _error ) \
732    _CPU_Fatal_error( _error )
733
734/* end of Fatal Error manager macros */
735
736/* Bitfield handler macros */
737
738/*
739 *  This routine sets _output to the bit number of the first bit
740 *  set in _value.  _value is of CPU dependent type Priority_Bit_map_control.
741 *  This type may be either 16 or 32 bits wide although only the 16
742 *  least significant bits will be used.
743 *
744 *  There are a number of variables in using a "find first bit" type
745 *  instruction.
746 *
747 *    (1) What happens when run on a value of zero?
748 *    (2) Bits may be numbered from MSB to LSB or vice-versa.
749 *    (3) The numbering may be zero or one based.
750 *    (4) The "find first bit" instruction may search from MSB or LSB.
751 *
752 *  RTEMS guarantees that (1) will never happen so it is not a concern.
753 *  (2),(3), (4) are handled by the macros _CPU_Priority_mask() and
754 *  _CPU_Priority_Bits_index().  These three form a set of routines
755 *  which must logically operate together.  Bits in the _value are
756 *  set and cleared based on masks built by _CPU_Priority_mask().
757 *  The basic major and minor values calculated by _Priority_Major()
758 *  and _Priority_Minor() are "massaged" by _CPU_Priority_Bits_index()
759 *  to properly range between the values returned by the "find first bit"
760 *  instruction.  This makes it possible for _Priority_Get_highest() to
761 *  calculate the major and directly index into the minor table.
762 *  This mapping is necessary to ensure that 0 (a high priority major/minor)
763 *  is the first bit found.
764 *
765 *  This entire "find first bit" and mapping process depends heavily
766 *  on the manner in which a priority is broken into a major and minor
767 *  components with the major being the 4 MSB of a priority and minor
768 *  the 4 LSB.  Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
769 *  priority.  And (15 << 4) + 14 corresponds to priority 254 -- the next
770 *  to the lowest priority.
771 *
772 *  If your CPU does not have a "find first bit" instruction, then
773 *  there are ways to make do without it.  Here are a handful of ways
774 *  to implement this in software:
775 *
776 *    - a series of 16 bit test instructions
777 *    - a "binary search using if's"
778 *    - _number = 0
779 *      if _value > 0x00ff
780 *        _value >>=8
781 *        _number = 8;
782 *
783 *      if _value > 0x0000f
784 *        _value >=8
785 *        _number += 4
786 *
787 *      _number += bit_set_table[ _value ]
788 *
789 *    where bit_set_table[ 16 ] has values which indicate the first
790 *      bit set
791 */
792
793#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
794    _output = _CPU_ffs( _value )
795
796/* end of Bitfield handler macros */
797
798/*
799 *  This routine builds the mask which corresponds to the bit fields
800 *  as searched by _CPU_Bitfield_Find_first_bit().  See the discussion
801 *  for that routine.
802 */
803
804#define _CPU_Priority_Mask( _bit_number ) \
805  ( 1 << (_bit_number) )
806
807/*
808 *  This routine translates the bit numbers returned by
809 *  _CPU_Bitfield_Find_first_bit() into something suitable for use as
810 *  a major or minor component of a priority.  See the discussion
811 *  for that routine.
812 */
813
814#define _CPU_Priority_Bits_index( _priority ) \
815  (_priority)
816
817/* end of Priority handler macros */
818
819/* functions */
820
821/*
822 *  _CPU_Initialize
823 *
824 *  This routine performs CPU dependent initialization.
825 */
826
827void _CPU_Initialize(
828  rtems_cpu_table  *cpu_table,
829  void      (*thread_dispatch)
830);
831
832/*
833 *  _CPU_ISR_install_raw_handler
834 *
835 *  This routine installs a "raw" interrupt handler directly into the
836 *  processor's vector table.
837 */
838 
839void _CPU_ISR_install_raw_handler(
840  unsigned32  vector,
841  proc_ptr    new_handler,
842  proc_ptr   *old_handler
843);
844
845/*
846 *  _CPU_ISR_install_vector
847 *
848 *  This routine installs an interrupt vector.
849 */
850
851void _CPU_ISR_install_vector(
852  unsigned32  vector,
853  proc_ptr    new_handler,
854  proc_ptr   *old_handler
855);
856
857/*
858 *  _CPU_Install_interrupt_stack
859 *
860 *  This routine installs the hardware interrupt stack pointer.
861 *
862 *  NOTE:  It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK
863 *         is TRUE.
864 */
865
866void _CPU_Install_interrupt_stack( void );
867
868/*
869 *  _CPU_Internal_threads_Idle_thread_body
870 *
871 *  This routine is the CPU dependent IDLE thread body.
872 *
873 *  NOTE:  It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY
874 *         is TRUE.
875 */
876
877void _CPU_Internal_threads_Idle_thread_body( void );
878
879/*
880 *  _CPU_Context_switch
881 *
882 *  This routine switches from the run context to the heir context.
883 */
884
885void _CPU_Context_switch(
886  Context_Control  *run,
887  Context_Control  *heir
888);
889
890/*
891 *  _CPU_Context_restore
892 *
893 *  This routine is generallu used only to restart self in an
894 *  efficient manner.  It may simply be a label in _CPU_Context_switch.
895 *
896 *  NOTE: May be unnecessary to reload some registers.
897 */
898
899void _CPU_Context_restore(
900  Context_Control *new_context
901);
902
903/*
904 *  _CPU_Save_float_context
905 *
906 *  This routine saves the floating point context passed to it.
907 */
908
909void _CPU_Save_float_context(
910  Context_Control_fp *fp_context_ptr
911);
912
913/*
914 *  _CPU_Restore_float_context
915 *
916 *  This routine restores the floating point context passed to it.
917 */
918
919void _CPU_Restore_float_context(
920  Context_Control_fp *fp_context_ptr
921);
922
923
924void _CPU_ISR_Set_signal_level(
925  unsigned32 level
926);
927
928void _CPU_Fatal_error(
929  unsigned32 _error
930);
931
932int _CPU_ffs(
933  unsigned32 _value
934);
935
936/*  The following routine swaps the endian format of an unsigned int.
937 *  It must be static because it is referenced indirectly.
938 *
939 *  This version will work on any processor, but if there is a better
940 *  way for your CPU PLEASE use it.  The most common way to do this is to:
941 *
942 *     swap least significant two bytes with 16-bit rotate
943 *     swap upper and lower 16-bits
944 *     swap most significant two bytes with 16-bit rotate
945 *
946 *  Some CPUs have special instructions which swap a 32-bit quantity in
947 *  a single instruction (e.g. i486).  It is probably best to avoid
948 *  an "endian swapping control bit" in the CPU.  One good reason is
949 *  that interrupts would probably have to be disabled to insure that
950 *  an interrupt does not try to access the same "chunk" with the wrong
951 *  endian.  Another good reason is that on some CPUs, the endian bit
952 *  endianness for ALL fetches -- both code and data -- so the code
953 *  will be fetched incorrectly.
954 */
955 
956static inline unsigned int CPU_swap_u32(
957  unsigned int value
958)
959{
960  unsigned32 byte1, byte2, byte3, byte4, swapped;
961 
962  byte4 = (value >> 24) & 0xff;
963  byte3 = (value >> 16) & 0xff;
964  byte2 = (value >> 8)  & 0xff;
965  byte1 =  value        & 0xff;
966 
967  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
968  return( swapped );
969}
970
971#ifdef __cplusplus
972}
973#endif
974
975#endif
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