source: rtems/c/src/exec/score/cpu/unix/cpu.h @ 8044533

4.104.114.84.95
Last change on this file since 8044533 was 8044533, checked in by Joel Sherrill <joel.sherrill@…>, on Jul 18, 1995 at 7:27:50 PM

merged Linux UNIX simulator support (C)

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File size: 29.9 KB
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1/*  cpu.h
2 *
3 *  This include file contains information pertaining to the HP
4 *  PA-RISC processor (Level 1.1).
5 *
6 *  COPYRIGHT (c) 1994 by Division Incorporated
7 *
8 *  To anyone who acknowledges that this file is provided "AS IS"
9 *  without any express or implied warranty:
10 *      permission to use, copy, modify, and distribute this file
11 *      for any purpose is hereby granted without fee, provided that
12 *      the above copyright notice and this notice appears in all
13 *      copies, and that the name of Division Incorporated not be
14 *      used in advertising or publicity pertaining to distribution
15 *      of the software without specific, written prior permission.
16 *      Division Incorporated makes no representations about the
17 *      suitability of this software for any purpose.
18 *
19 *  $Id$
20 */
21
22#ifndef __CPU_h
23#define __CPU_h
24
25#ifdef __cplusplus
26extern "C" {
27#endif
28
29#include <rtems/unix.h>
30#ifndef ASM
31#include <rtems/unixtypes.h>
32#endif
33
34#if defined(solaris2)
35#undef  _POSIX_C_SOURCE
36#define _POSIX_C_SOURCE 3
37#undef  __STRICT_ANSI__
38#define __STRICT_ANSI__
39#endif
40
41#if 0
42
43/*
44 *  In order to get the types and prototypes used in this file under
45 *  Solaris 2.3, it is necessary to pull the following magic.
46 */
47
48#if defined(solaris2)
49#warning "Ignore the undefining __STDC__ warning"
50#undef __STDC__
51#define __STDC__ 0
52#undef  _POSIX_C_SOURCE
53#endif
54
55#endif
56
57#include <setjmp.h>
58#include <signal.h>
59
60/* conditional compilation parameters */
61
62/*
63 *  Should the calls to _Thread_Enable_dispatch be inlined?
64 *
65 *  If TRUE, then they are inlined.
66 *  If FALSE, then a subroutine call is made.
67 *
68 *  Basically this is an example of the classic trade-off of size
69 *  versus speed.  Inlining the call (TRUE) typically increases the
70 *  size of RTEMS while speeding up the enabling of dispatching.
71 *  [NOTE: In general, the _Thread_Dispatch_disable_level will
72 *  only be 0 or 1 unless you are in an interrupt handler and that
73 *  interrupt handler invokes the executive.]  When not inlined
74 *  something calls _Thread_Enable_dispatch which in turns calls
75 *  _Thread_Dispatch.  If the enable dispatch is inlined, then
76 *  one subroutine call is avoided entirely.]
77 */
78
79#define CPU_INLINE_ENABLE_DISPATCH       FALSE
80
81/*
82 *  Should the body of the search loops in _Thread_queue_Enqueue_priority
83 *  be unrolled one time?  In unrolled each iteration of the loop examines
84 *  two "nodes" on the chain being searched.  Otherwise, only one node
85 *  is examined per iteration.
86 *
87 *  If TRUE, then the loops are unrolled.
88 *  If FALSE, then the loops are not unrolled.
89 *
90 *  The primary factor in making this decision is the cost of disabling
91 *  and enabling interrupts (_ISR_Flash) versus the cost of rest of the
92 *  body of the loop.  On some CPUs, the flash is more expensive than
93 *  one iteration of the loop body.  In this case, it might be desirable
94 *  to unroll the loop.  It is important to note that on some CPUs, this
95 *  code is the longest interrupt disable period in RTEMS.  So it is
96 *  necessary to strike a balance when setting this parameter.
97 */
98
99#define CPU_UNROLL_ENQUEUE_PRIORITY      TRUE
100
101/*
102 *  Does RTEMS manage a dedicated interrupt stack in software?
103 *
104 *  If TRUE, then a stack is allocated in _Interrupt_Manager_initialization.
105 *  If FALSE, nothing is done.
106 *
107 *  If the CPU supports a dedicated interrupt stack in hardware,
108 *  then it is generally the responsibility of the BSP to allocate it
109 *  and set it up.
110 *
111 *  If the CPU does not support a dedicated interrupt stack, then
112 *  the porter has two options: (1) execute interrupts on the
113 *  stack of the interrupted task, and (2) have RTEMS manage a dedicated
114 *  interrupt stack.
115 *
116 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
117 *
118 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
119 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
120 *  possible that both are FALSE for a particular CPU.  Although it
121 *  is unclear what that would imply about the interrupt processing
122 *  procedure on that CPU.
123 */
124
125#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE
126
127/*
128 *  Does this CPU have hardware support for a dedicated interrupt stack?
129 *
130 *  If TRUE, then it must be installed during initialization.
131 *  If FALSE, then no installation is performed.
132 *
133 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
134 *
135 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
136 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
137 *  possible that both are FALSE for a particular CPU.  Although it
138 *  is unclear what that would imply about the interrupt processing
139 *  procedure on that CPU.
140 */
141
142#define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE
143
144/*
145 *  Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
146 *
147 *  If TRUE, then the memory is allocated during initialization.
148 *  If FALSE, then the memory is allocated during initialization.
149 *
150 *  This should be TRUE if CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE
151 *  or CPU_INSTALL_HARDWARE_INTERRUPT_STACK is TRUE.
152 */
153
154#define CPU_ALLOCATE_INTERRUPT_STACK FALSE
155
156/*
157 *  Does the CPU have hardware floating point?
158 *
159 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
160 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
161 *
162 *  If there is a FP coprocessor such as the i387 or mc68881, then
163 *  the answer is TRUE.
164 *
165 *  The macro name "NO_CPU_HAS_FPU" should be made CPU specific.
166 *  It indicates whether or not this CPU model has FP support.  For
167 *  example, it would be possible to have an i386_nofp CPU model
168 *  which set this to false to indicate that you have an i386 without
169 *  an i387 and wish to leave floating point support out of RTEMS.
170 */
171
172#define CPU_HARDWARE_FP     TRUE
173
174/*
175 *  Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
176 *
177 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
178 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
179 *
180 *  So far, the only CPU in which this option has been used is the
181 *  HP PA-RISC.  The HP C compiler and gcc both implicitly use the
182 *  floating point registers to perform integer multiplies.  If
183 *  a function which you would not think utilize the FP unit DOES,
184 *  then one can not easily predict which tasks will use the FP hardware.
185 *  In this case, this option should be TRUE.
186 *
187 *  If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
188 */
189
190#define CPU_ALL_TASKS_ARE_FP     FALSE
191
192/*
193 *  Should the IDLE task have a floating point context?
194 *
195 *  If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
196 *  and it has a floating point context which is switched in and out.
197 *  If FALSE, then the IDLE task does not have a floating point context.
198 *
199 *  Setting this to TRUE negatively impacts the time required to preempt
200 *  the IDLE task from an interrupt because the floating point context
201 *  must be saved as part of the preemption.
202 */
203
204#define CPU_IDLE_TASK_IS_FP      FALSE
205
206/*
207 *  Should the saving of the floating point registers be deferred
208 *  until a context switch is made to another different floating point
209 *  task?
210 *
211 *  If TRUE, then the floating point context will not be stored until
212 *  necessary.  It will remain in the floating point registers and not
213 *  disturned until another floating point task is switched to.
214 *
215 *  If FALSE, then the floating point context is saved when a floating
216 *  point task is switched out and restored when the next floating point
217 *  task is restored.  The state of the floating point registers between
218 *  those two operations is not specified.
219 *
220 *  If the floating point context does NOT have to be saved as part of
221 *  interrupt dispatching, then it should be safe to set this to TRUE.
222 *
223 *  Setting this flag to TRUE results in using a different algorithm
224 *  for deciding when to save and restore the floating point context.
225 *  The deferred FP switch algorithm minimizes the number of times
226 *  the FP context is saved and restored.  The FP context is not saved
227 *  until a context switch is made to another, different FP task.
228 *  Thus in a system with only one FP task, the FP context will never
229 *  be saved or restored.
230 */
231
232#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
233
234/*
235 *  Does this port provide a CPU dependent IDLE task implementation?
236 *
237 *  If TRUE, then the routine _CPU_Internal_threads_Idle_thread_body
238 *  must be provided and is the default IDLE thread body instead of
239 *  _Internal_threads_Idle_thread_body.
240 *
241 *  If FALSE, then use the generic IDLE thread body if the BSP does
242 *  not provide one.
243 *
244 *  This is intended to allow for supporting processors which have
245 *  a low power or idle mode.  When the IDLE thread is executed, then
246 *  the CPU can be powered down.
247 *
248 *  The order of precedence for selecting the IDLE thread body is:
249 *
250 *    1.  BSP provided
251 *    2.  CPU dependent (if provided)
252 *    3.  generic (if no BSP and no CPU dependent)
253 */
254
255#define CPU_PROVIDES_IDLE_THREAD_BODY    TRUE
256
257/*
258 *  Does the stack grow up (toward higher addresses) or down
259 *  (toward lower addresses)?
260 *
261 *  If TRUE, then the grows upward.
262 *  If FALSE, then the grows toward smaller addresses.
263 */
264
265#if defined(hppa1_1)
266#define CPU_STACK_GROWS_UP               TRUE
267#elif defined(sparc) || defined(i386)
268#define CPU_STACK_GROWS_UP               FALSE
269#else
270#error "unknown CPU!!"
271#endif
272
273
274/*
275 *  The following is the variable attribute used to force alignment
276 *  of critical RTEMS structures.  On some processors it may make
277 *  sense to have these aligned on tighter boundaries than
278 *  the minimum requirements of the compiler in order to have as
279 *  much of the critical data area as possible in a cache line.
280 *
281 *  The placement of this macro in the declaration of the variables
282 *  is based on the syntactically requirements of the GNU C
283 *  "__attribute__" extension.  For example with GNU C, use
284 *  the following to force a structures to a 32 byte boundary.
285 *
286 *      __attribute__ ((aligned (32)))
287 *
288 *  NOTE:  Currently only the Priority Bit Map table uses this feature.
289 *         To benefit from using this, the data must be heavily
290 *         used so it will stay in the cache and used frequently enough
291 *         in the executive to justify turning this on.
292 */
293
294#define CPU_STRUCTURE_ALIGNMENT          __attribute__ ((aligned (32)))
295
296/*
297 *  The following defines the number of bits actually used in the
298 *  interrupt field of the task mode.  How those bits map to the
299 *  CPU interrupt levels is defined by the routine _CPU_ISR_Set_level().
300 */
301
302#define CPU_MODES_INTERRUPT_MASK   0x00000001
303
304#define CPU_NAME "UNIX"
305
306/*
307 *  Processor defined structures
308 *
309 *  Examples structures include the descriptor tables from the i386
310 *  and the processor control structure on the i960ca.
311 */
312
313/* may need to put some structures here.  */
314
315#if defined(hppa1_1)
316/*
317 * Word indices within a jmp_buf structure
318 */
319
320#ifdef RTEMS_NEWLIB
321#define RP_OFF       6
322#define SP_OFF       2
323#define R3_OFF      10
324#define R4_OFF      11
325#define R5_OFF      12
326#define R6_OFF      13
327#define R7_OFF      14
328#define R8_OFF      15
329#define R9_OFF      16
330#define R10_OFF     17
331#define R11_OFF     18
332#define R12_OFF     19
333#define R13_OFF     20
334#define R14_OFF     21
335#define R15_OFF     22
336#define R16_OFF     23
337#define R17_OFF     24
338#define R18_OFF     25
339#define DP_OFF      26
340#endif
341
342#ifdef RTEMS_UNIXLIB
343#define RP_OFF       0
344#define SP_OFF       1
345#define R3_OFF       4
346#define R4_OFF       5
347#define R5_OFF       6
348#define R6_OFF       7
349#define R7_OFF       8
350#define R8_OFF       9
351#define R9_OFF      10
352#define R10_OFF     11
353#define R11_OFF     12
354#define R12_OFF     13
355#define R13_OFF     14
356#define R14_OFF     15
357#define R15_OFF     16
358#define R16_OFF     17
359#define R17_OFF     18
360#define R18_OFF     19
361#define DP_OFF      20
362#endif
363#endif
364
365#if defined(i386)
366 
367#ifdef RTEMS_NEWLIB
368#error "Newlib not installed"
369#endif
370 
371/*
372 *  For Linux 1.1
373 */
374 
375#ifdef RTEMS_UNIXLIB
376#define EBX_OFF    0
377#define ESI_OFF    1
378#define EDI_OFF    2
379#define EBP_OFF    3
380#define ESP_OFF    4
381#define RET_OFF    5
382#endif
383 
384#endif
385 
386#if defined(sparc)
387
388/*
389 *  Word indices within a jmp_buf structure
390 */
391 
392#ifdef RTEMS_NEWLIB
393#define ADDR_ADJ_OFFSET -8
394#define SP_OFF    0
395#define RP_OFF    1
396#define FP_OFF    2
397#endif
398
399#ifdef RTEMS_UNIXLIB
400#define ADDR_ADJ_OFFSET 0
401#define G0_OFF    0
402#define SP_OFF    1
403#define RP_OFF    2   
404#define FP_OFF    3
405#define I7_OFF    4
406#endif
407
408#endif
409
410/*
411 * Contexts
412 *
413 *  Generally there are 2 types of context to save.
414 *     1. Interrupt registers to save
415 *     2. Task level registers to save
416 *
417 *  This means we have the following 3 context items:
418 *     1. task level context stuff::  Context_Control
419 *     2. floating point task stuff:: Context_Control_fp
420 *     3. special interrupt level context :: Context_Control_interrupt
421 *
422 *  On some processors, it is cost-effective to save only the callee
423 *  preserved registers during a task context switch.  This means
424 *  that the ISR code needs to save those registers which do not
425 *  persist across function calls.  It is not mandatory to make this
426 *  distinctions between the caller/callee saves registers for the
427 *  purpose of minimizing context saved during task switch and on interrupts.
428 *  If the cost of saving extra registers is minimal, simplicity is the
429 *  choice.  Save the same context on interrupt entry as for tasks in
430 *  this case.
431 *
432 *  Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
433 *  care should be used in designing the context area.
434 *
435 *  On some CPUs with hardware floating point support, the Context_Control_fp
436 *  structure will not be used or it simply consist of an array of a
437 *  fixed number of bytes.   This is done when the floating point context
438 *  is dumped by a "FP save context" type instruction and the format
439 *  is not really defined by the CPU.  In this case, there is no need
440 *  to figure out the exact format -- only the size.  Of course, although
441 *  this is enough information for RTEMS, it is probably not enough for
442 *  a debugger such as gdb.  But that is another problem.
443 */
444
445typedef struct {
446  jmp_buf   regs;
447  sigset_t  isr_level;
448  int       junk;
449} Context_Control;
450
451typedef struct {
452} Context_Control_fp;
453
454typedef struct {
455} CPU_Interrupt_frame;
456
457
458/*
459 *  The following table contains the information required to configure
460 *  the XXX processor specific parameters.
461 *
462 *  NOTE: The interrupt_stack_size field is required if
463 *        CPU_ALLOCATE_INTERRUPT_STACK is defined as TRUE.
464 *
465 *        The pretasking_hook, predriver_hook, and postdriver_hook,
466 *        and the do_zero_of_workspace fields are required on ALL CPUs.
467 */
468
469typedef struct {
470  void       (*pretasking_hook)( void );
471  void       (*predriver_hook)( void );
472  void       (*postdriver_hook)( void );
473  void       (*idle_task)( void );
474  boolean      do_zero_of_workspace;
475  unsigned32   interrupt_stack_size;
476  unsigned32   extra_system_initialization_stack;
477}   rtems_cpu_table;
478
479/*
480 *  This variable is optional.  It is used on CPUs on which it is difficult
481 *  to generate an "uninitialized" FP context.  It is filled in by
482 *  _CPU_Initialize and copied into the task's FP context area during
483 *  _CPU_Context_Initialize.
484 */
485
486EXTERN Context_Control_fp  _CPU_Null_fp_context;
487
488/*
489 *  On some CPUs, RTEMS supports a software managed interrupt stack.
490 *  This stack is allocated by the Interrupt Manager and the switch
491 *  is performed in _ISR_Handler.  These variables contain pointers
492 *  to the lowest and highest addresses in the chunk of memory allocated
493 *  for the interrupt stack.  Since it is unknown whether the stack
494 *  grows up or down (in general), this give the CPU dependent
495 *  code the option of picking the version it wants to use.
496 *
497 *  NOTE: These two variables are required if the macro
498 *        CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
499 */
500
501EXTERN void               *_CPU_Interrupt_stack_low;
502EXTERN void               *_CPU_Interrupt_stack_high;
503
504/*
505 *  With some compilation systems, it is difficult if not impossible to
506 *  call a high-level language routine from assembly language.  This
507 *  is especially true of commercial Ada compilers and name mangling
508 *  C++ ones.  This variable can be optionally defined by the CPU porter
509 *  and contains the address of the routine _Thread_Dispatch.  This
510 *  can make it easier to invoke that routine at the end of the interrupt
511 *  sequence (if a dispatch is necessary).
512 */
513
514EXTERN void           (*_CPU_Thread_dispatch_pointer)();
515
516/*
517 *  Nothing prevents the porter from declaring more CPU specific variables.
518 */
519
520/* XXX: if needed, put more variables here */
521
522/*
523 *  The size of the floating point context area.  On some CPUs this
524 *  will not be a "sizeof" because the format of the floating point
525 *  area is not defined -- only the size is.  This is usually on
526 *  CPUs with a "floating point save context" instruction.
527 */
528
529#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
530
531/*
532 * The size of a frame on the stack
533 */
534
535#if defined(hppa1_1)
536#define CPU_FRAME_SIZE  (32 * 4)
537#elif defined(sparc)
538#define CPU_FRAME_SIZE  (112)   /* based on disassembled test code */
539#elif defined(i386)
540#define CPU_FRAME_SIZE  (24)  /* return address, sp, and bp pushed plus fudge */
541#else
542#error "Unknown CPU!!!"
543#endif
544
545/*
546 *  Amount of extra stack (above minimum stack size) required by
547 *  system initialization thread.  Remember that in a multiprocessor
548 *  system the system intialization thread becomes the MP server thread.
549 */
550
551#define CPU_SYSTEM_INITIALIZATION_THREAD_EXTRA_STACK 0
552
553/*
554 *  This defines the number of entries in the ISR_Vector_table managed
555 *  by RTEMS.
556 */
557
558#define CPU_INTERRUPT_NUMBER_OF_VECTORS  64
559
560/*
561 *  Should be large enough to run all RTEMS tests.  This insures
562 *  that a "reasonable" small application should not have any problems.
563 */
564
565#define CPU_STACK_MINIMUM_SIZE          (16 * 1024)
566
567/*
568 *  CPU's worst alignment requirement for data types on a byte boundary.  This
569 *  alignment does not take into account the requirements for the stack.
570 */
571
572#define CPU_ALIGNMENT              8
573
574/*
575 *  This number corresponds to the byte alignment requirement for the
576 *  heap handler.  This alignment requirement may be stricter than that
577 *  for the data types alignment specified by CPU_ALIGNMENT.  It is
578 *  common for the heap to follow the same alignment requirement as
579 *  CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict enough for the heap,
580 *  then this should be set to CPU_ALIGNMENT.
581 *
582 *  NOTE:  This does not have to be a power of 2.  It does have to
583 *         be greater or equal to than CPU_ALIGNMENT.
584 */
585
586#define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT
587
588/*
589 *  This number corresponds to the byte alignment requirement for memory
590 *  buffers allocated by the partition manager.  This alignment requirement
591 *  may be stricter than that for the data types alignment specified by
592 *  CPU_ALIGNMENT.  It is common for the partition to follow the same
593 *  alignment requirement as CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict
594 *  enough for the partition, then this should be set to CPU_ALIGNMENT.
595 *
596 *  NOTE:  This does not have to be a power of 2.  It does have to
597 *         be greater or equal to than CPU_ALIGNMENT.
598 */
599
600#define CPU_PARTITION_ALIGNMENT    CPU_ALIGNMENT
601
602/*
603 *  This number corresponds to the byte alignment requirement for the
604 *  stack.  This alignment requirement may be stricter than that for the
605 *  data types alignment specified by CPU_ALIGNMENT.  If the CPU_ALIGNMENT
606 *  is strict enough for the stack, then this should be set to 0.
607 *
608 *  NOTE:  This must be a power of 2 either 0 or greater than CPU_ALIGNMENT.
609 */
610
611#define CPU_STACK_ALIGNMENT        64
612
613/* ISR handler macros */
614
615/*
616 *  Disable all interrupts for an RTEMS critical section.  The previous
617 *  level is returned in _level.
618 */
619
620extern unsigned32 _CPU_ISR_Disable_support(void);
621
622#define _CPU_ISR_Disable( _level ) \
623    do { \
624      (_level) = _CPU_ISR_Disable_support(); \
625    } while ( 0 )
626
627/*
628 *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
629 *  This indicates the end of an RTEMS critical section.  The parameter
630 *  _level is not modified.
631 */
632
633void _CPU_ISR_Enable(unsigned32 level);
634
635/*
636 *  This temporarily restores the interrupt to _level before immediately
637 *  disabling them again.  This is used to divide long RTEMS critical
638 *  sections into two or more parts.  The parameter _level is not
639 * modified.
640 */
641
642#define _CPU_ISR_Flash( _level ) \
643  do { \
644      register _ignored = 0; \
645      _CPU_ISR_Enable( (_level) ); \
646      _CPU_ISR_Disable( _ignored ); \
647  } while ( 0 )
648
649/*
650 *  Map interrupt level in task mode onto the hardware that the CPU
651 *  actually provides.  Currently, interrupt levels which do not
652 *  map onto the CPU in a generic fashion are undefined.  Someday,
653 *  it would be nice if these were "mapped" by the application
654 *  via a callout.  For example, m68k has 8 levels 0 - 7, levels
655 *  8 - 255 would be available for bsp/application specific meaning.
656 *  This could be used to manage a programmable interrupt controller
657 *  via the rtems_task_mode directive.
658 */
659
660#define _CPU_ISR_Set_level( new_level ) \
661  { \
662    if ( new_level == 0 ) _CPU_ISR_Enable( 0 ); \
663    else                  _CPU_ISR_Enable( 1 ); \
664  }
665
666/* end of ISR handler macros */
667
668/* Context handler macros */
669
670/*
671 *  This routine is responsible for somehow restarting the currently
672 *  executing task.  If you are lucky, then all that is necessary
673 *  is restoring the context.  Otherwise, there will need to be
674 *  a special assembly routine which does something special in this
675 *  case.  Context_Restore should work most of the time.  It will
676 *  not work if restarting self conflicts with the stack frame
677 *  assumptions of restoring a context.
678 */
679
680#define _CPU_Context_Restart_self( _the_context ) \
681   _CPU_Context_restore( (_the_context) );
682
683/*
684 *  The purpose of this macro is to allow the initial pointer into
685 *  a floating point context area (used to save the floating point
686 *  context) to be at an arbitrary place in the floating point
687 *  context area.
688 *
689 *  This is necessary because some FP units are designed to have
690 *  their context saved as a stack which grows into lower addresses.
691 *  Other FP units can be saved by simply moving registers into offsets
692 *  from the base of the context area.  Finally some FP units provide
693 *  a "dump context" instruction which could fill in from high to low
694 *  or low to high based on the whim of the CPU designers.
695 */
696
697#define _CPU_Context_Fp_start( _base, _offset ) \
698   ( (void *) (_base) + (_offset) )
699
700/*
701 *  This routine initializes the FP context area passed to it to.
702 *  There are a few standard ways in which to initialize the
703 *  floating point context.  The code included for this macro assumes
704 *  that this is a CPU in which a "initial" FP context was saved into
705 *  _CPU_Null_fp_context and it simply copies it to the destination
706 *  context passed to it.
707 *
708 *  Other models include (1) not doing anything, and (2) putting
709 *  a "null FP status word" in the correct place in the FP context.
710 */
711
712#define _CPU_Context_Initialize_fp( _destination ) \
713  { \
714   *((Context_Control_fp *) *((void **) _destination)) = _CPU_Null_fp_context; \
715  }
716
717#define _CPU_Context_save_fp( _fp_context ) \
718    _CPU_Save_float_context( *(Context_Control_fp **)(_fp_context))
719
720#define _CPU_Context_restore_fp( _fp_context ) \
721    _CPU_Restore_float_context( *(Context_Control_fp **)(_fp_context))
722
723extern void _CPU_Context_Initialize(
724  Context_Control  *_the_context,
725  unsigned32       *_stack_base,
726  unsigned32        _size,
727  unsigned32        _new_level,
728  void             *_entry_point
729);
730
731/* end of Context handler macros */
732
733/* Fatal Error manager macros */
734
735/*
736 *  This routine copies _error into a known place -- typically a stack
737 *  location or a register, optionally disables interrupts, and
738 *  halts/stops the CPU.
739 */
740
741#define _CPU_Fatal_halt( _error ) \
742    _CPU_Fatal_error( _error )
743
744/* end of Fatal Error manager macros */
745
746/* Bitfield handler macros */
747
748/*
749 *  This routine sets _output to the bit number of the first bit
750 *  set in _value.  _value is of CPU dependent type Priority_Bit_map_control.
751 *  This type may be either 16 or 32 bits wide although only the 16
752 *  least significant bits will be used.
753 *
754 *  There are a number of variables in using a "find first bit" type
755 *  instruction.
756 *
757 *    (1) What happens when run on a value of zero?
758 *    (2) Bits may be numbered from MSB to LSB or vice-versa.
759 *    (3) The numbering may be zero or one based.
760 *    (4) The "find first bit" instruction may search from MSB or LSB.
761 *
762 *  RTEMS guarantees that (1) will never happen so it is not a concern.
763 *  (2),(3), (4) are handled by the macros _CPU_Priority_mask() and
764 *  _CPU_Priority_Bits_index().  These three form a set of routines
765 *  which must logically operate together.  Bits in the _value are
766 *  set and cleared based on masks built by _CPU_Priority_mask().
767 *  The basic major and minor values calculated by _Priority_Major()
768 *  and _Priority_Minor() are "massaged" by _CPU_Priority_Bits_index()
769 *  to properly range between the values returned by the "find first bit"
770 *  instruction.  This makes it possible for _Priority_Get_highest() to
771 *  calculate the major and directly index into the minor table.
772 *  This mapping is necessary to ensure that 0 (a high priority major/minor)
773 *  is the first bit found.
774 *
775 *  This entire "find first bit" and mapping process depends heavily
776 *  on the manner in which a priority is broken into a major and minor
777 *  components with the major being the 4 MSB of a priority and minor
778 *  the 4 LSB.  Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
779 *  priority.  And (15 << 4) + 14 corresponds to priority 254 -- the next
780 *  to the lowest priority.
781 *
782 *  If your CPU does not have a "find first bit" instruction, then
783 *  there are ways to make do without it.  Here are a handful of ways
784 *  to implement this in software:
785 *
786 *    - a series of 16 bit test instructions
787 *    - a "binary search using if's"
788 *    - _number = 0
789 *      if _value > 0x00ff
790 *        _value >>=8
791 *        _number = 8;
792 *
793 *      if _value > 0x0000f
794 *        _value >=8
795 *        _number += 4
796 *
797 *      _number += bit_set_table[ _value ]
798 *
799 *    where bit_set_table[ 16 ] has values which indicate the first
800 *      bit set
801 */
802
803#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
804    _output = _CPU_ffs( _value )
805
806/* end of Bitfield handler macros */
807
808/*
809 *  This routine builds the mask which corresponds to the bit fields
810 *  as searched by _CPU_Bitfield_Find_first_bit().  See the discussion
811 *  for that routine.
812 */
813
814#define _CPU_Priority_Mask( _bit_number ) \
815  ( 1 << (_bit_number) )
816
817/*
818 *  This routine translates the bit numbers returned by
819 *  _CPU_Bitfield_Find_first_bit() into something suitable for use as
820 *  a major or minor component of a priority.  See the discussion
821 *  for that routine.
822 */
823
824#define _CPU_Priority_Bits_index( _priority ) \
825  (_priority)
826
827/* end of Priority handler macros */
828
829/* functions */
830
831/*
832 *  _CPU_Initialize
833 *
834 *  This routine performs CPU dependent initialization.
835 */
836
837void _CPU_Initialize(
838  rtems_cpu_table  *cpu_table,
839  void      (*thread_dispatch)
840);
841
842/*
843 *  _CPU_ISR_install_raw_handler
844 *
845 *  This routine installs a "raw" interrupt handler directly into the
846 *  processor's vector table.
847 */
848 
849void _CPU_ISR_install_raw_handler(
850  unsigned32  vector,
851  proc_ptr    new_handler,
852  proc_ptr   *old_handler
853);
854
855/*
856 *  _CPU_ISR_install_vector
857 *
858 *  This routine installs an interrupt vector.
859 */
860
861void _CPU_ISR_install_vector(
862  unsigned32  vector,
863  proc_ptr    new_handler,
864  proc_ptr   *old_handler
865);
866
867/*
868 *  _CPU_Install_interrupt_stack
869 *
870 *  This routine installs the hardware interrupt stack pointer.
871 *
872 *  NOTE:  It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK
873 *         is TRUE.
874 */
875
876void _CPU_Install_interrupt_stack( void );
877
878/*
879 *  _CPU_Internal_threads_Idle_thread_body
880 *
881 *  This routine is the CPU dependent IDLE thread body.
882 *
883 *  NOTE:  It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY
884 *         is TRUE.
885 */
886
887void _CPU_Internal_threads_Idle_thread_body( void );
888
889/*
890 *  _CPU_Context_switch
891 *
892 *  This routine switches from the run context to the heir context.
893 */
894
895void _CPU_Context_switch(
896  Context_Control  *run,
897  Context_Control  *heir
898);
899
900/*
901 *  _CPU_Context_restore
902 *
903 *  This routine is generallu used only to restart self in an
904 *  efficient manner.  It may simply be a label in _CPU_Context_switch.
905 *
906 *  NOTE: May be unnecessary to reload some registers.
907 */
908
909void _CPU_Context_restore(
910  Context_Control *new_context
911);
912
913/*
914 *  _CPU_Save_float_context
915 *
916 *  This routine saves the floating point context passed to it.
917 */
918
919void _CPU_Save_float_context(
920  Context_Control_fp *fp_context_ptr
921);
922
923/*
924 *  _CPU_Restore_float_context
925 *
926 *  This routine restores the floating point context passed to it.
927 */
928
929void _CPU_Restore_float_context(
930  Context_Control_fp *fp_context_ptr
931);
932
933
934void _CPU_ISR_Set_signal_level(
935  unsigned32 level
936);
937
938void _CPU_Fatal_error(
939  unsigned32 _error
940);
941
942int _CPU_ffs(
943  unsigned32 _value
944);
945
946/*  The following routine swaps the endian format of an unsigned int.
947 *  It must be static because it is referenced indirectly.
948 *
949 *  This version will work on any processor, but if there is a better
950 *  way for your CPU PLEASE use it.  The most common way to do this is to:
951 *
952 *     swap least significant two bytes with 16-bit rotate
953 *     swap upper and lower 16-bits
954 *     swap most significant two bytes with 16-bit rotate
955 *
956 *  Some CPUs have special instructions which swap a 32-bit quantity in
957 *  a single instruction (e.g. i486).  It is probably best to avoid
958 *  an "endian swapping control bit" in the CPU.  One good reason is
959 *  that interrupts would probably have to be disabled to insure that
960 *  an interrupt does not try to access the same "chunk" with the wrong
961 *  endian.  Another good reason is that on some CPUs, the endian bit
962 *  endianness for ALL fetches -- both code and data -- so the code
963 *  will be fetched incorrectly.
964 */
965 
966static inline unsigned int CPU_swap_u32(
967  unsigned int value
968)
969{
970  unsigned32 byte1, byte2, byte3, byte4, swapped;
971 
972  byte4 = (value >> 24) & 0xff;
973  byte3 = (value >> 16) & 0xff;
974  byte2 = (value >> 8)  & 0xff;
975  byte1 =  value        & 0xff;
976 
977  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
978  return( swapped );
979}
980
981#ifdef __cplusplus
982}
983#endif
984
985#endif
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