source: rtems/c/src/exec/score/cpu/unix/cpu.h @ 77ea27fc

4.104.114.84.95
Last change on this file since 77ea27fc was 77ea27fc, checked in by Joel Sherrill <joel.sherrill@…>, on Feb 4, 1998 at 2:47:23 PM

Ralf Corsepius noticed that generally was spelled incorrectly.

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1/*  cpu.h
2 *
3 *  This include file contains information pertaining to the HP
4 *  PA-RISC processor (Level 1.1).
5 *
6 *  COPYRIGHT (c) 1994 by Division Incorporated
7 *
8 *  The license and distribution terms for this file may be
9 *  found in the file LICENSE in this distribution or at
10 *  http://www.OARcorp.com/rtems/license.html.
11 *
12 *  $Id$
13 */
14
15#ifndef __CPU_h
16#define __CPU_h
17
18#ifdef __cplusplus
19extern "C" {
20#endif
21
22#include <rtems/score/unix.h>              /* pick up machine definitions */
23#ifndef ASM
24#include <rtems/score/unixtypes.h>
25#endif
26
27#include <rtems/score/unixsize.h>
28
29#if defined(solaris2)
30#undef  _POSIX_C_SOURCE
31#define _POSIX_C_SOURCE 3
32#undef  __STRICT_ANSI__
33#define __STRICT_ANSI__
34#endif
35
36#if defined(linux)
37#define MALLOC_0_RETURNS_NULL
38#endif
39
40/* conditional compilation parameters */
41
42/*
43 *  Should the calls to _Thread_Enable_dispatch be inlined?
44 *
45 *  If TRUE, then they are inlined.
46 *  If FALSE, then a subroutine call is made.
47 *
48 *  Basically this is an example of the classic trade-off of size
49 *  versus speed.  Inlining the call (TRUE) typically increases the
50 *  size of RTEMS while speeding up the enabling of dispatching.
51 *  [NOTE: In general, the _Thread_Dispatch_disable_level will
52 *  only be 0 or 1 unless you are in an interrupt handler and that
53 *  interrupt handler invokes the executive.]  When not inlined
54 *  something calls _Thread_Enable_dispatch which in turns calls
55 *  _Thread_Dispatch.  If the enable dispatch is inlined, then
56 *  one subroutine call is avoided entirely.]
57 */
58
59#define CPU_INLINE_ENABLE_DISPATCH       FALSE
60
61/*
62 *  Should the body of the search loops in _Thread_queue_Enqueue_priority
63 *  be unrolled one time?  In unrolled each iteration of the loop examines
64 *  two "nodes" on the chain being searched.  Otherwise, only one node
65 *  is examined per iteration.
66 *
67 *  If TRUE, then the loops are unrolled.
68 *  If FALSE, then the loops are not unrolled.
69 *
70 *  The primary factor in making this decision is the cost of disabling
71 *  and enabling interrupts (_ISR_Flash) versus the cost of rest of the
72 *  body of the loop.  On some CPUs, the flash is more expensive than
73 *  one iteration of the loop body.  In this case, it might be desirable
74 *  to unroll the loop.  It is important to note that on some CPUs, this
75 *  code is the longest interrupt disable period in RTEMS.  So it is
76 *  necessary to strike a balance when setting this parameter.
77 */
78
79#define CPU_UNROLL_ENQUEUE_PRIORITY      TRUE
80
81/*
82 *  Does RTEMS manage a dedicated interrupt stack in software?
83 *
84 *  If TRUE, then a stack is allocated in _Interrupt_Manager_initialization.
85 *  If FALSE, nothing is done.
86 *
87 *  If the CPU supports a dedicated interrupt stack in hardware,
88 *  then it is generally the responsibility of the BSP to allocate it
89 *  and set it up.
90 *
91 *  If the CPU does not support a dedicated interrupt stack, then
92 *  the porter has two options: (1) execute interrupts on the
93 *  stack of the interrupted task, and (2) have RTEMS manage a dedicated
94 *  interrupt stack.
95 *
96 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
97 *
98 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
99 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
100 *  possible that both are FALSE for a particular CPU.  Although it
101 *  is unclear what that would imply about the interrupt processing
102 *  procedure on that CPU.
103 */
104
105#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE
106
107/*
108 *  Does this CPU have hardware support for a dedicated interrupt stack?
109 *
110 *  If TRUE, then it must be installed during initialization.
111 *  If FALSE, then no installation is performed.
112 *
113 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
114 *
115 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
116 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
117 *  possible that both are FALSE for a particular CPU.  Although it
118 *  is unclear what that would imply about the interrupt processing
119 *  procedure on that CPU.
120 */
121
122#define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE
123
124/*
125 *  Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
126 *
127 *  If TRUE, then the memory is allocated during initialization.
128 *  If FALSE, then the memory is allocated during initialization.
129 *
130 *  This should be TRUE if CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE
131 *  or CPU_INSTALL_HARDWARE_INTERRUPT_STACK is TRUE.
132 */
133
134#define CPU_ALLOCATE_INTERRUPT_STACK FALSE
135
136/*
137 *  Does the CPU have hardware floating point?
138 *
139 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
140 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
141 *
142 *  If there is a FP coprocessor such as the i387 or mc68881, then
143 *  the answer is TRUE.
144 *
145 *  The macro name "NO_CPU_HAS_FPU" should be made CPU specific.
146 *  It indicates whether or not this CPU model has FP support.  For
147 *  example, it would be possible to have an i386_nofp CPU model
148 *  which set this to false to indicate that you have an i386 without
149 *  an i387 and wish to leave floating point support out of RTEMS.
150 */
151
152#define CPU_HARDWARE_FP     TRUE
153
154/*
155 *  Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
156 *
157 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
158 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
159 *
160 *  So far, the only CPU in which this option has been used is the
161 *  HP PA-RISC.  The HP C compiler and gcc both implicitly use the
162 *  floating point registers to perform integer multiplies.  If
163 *  a function which you would not think utilize the FP unit DOES,
164 *  then one can not easily predict which tasks will use the FP hardware.
165 *  In this case, this option should be TRUE.
166 *
167 *  If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
168 */
169
170#define CPU_ALL_TASKS_ARE_FP     FALSE
171
172/*
173 *  Should the IDLE task have a floating point context?
174 *
175 *  If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
176 *  and it has a floating point context which is switched in and out.
177 *  If FALSE, then the IDLE task does not have a floating point context.
178 *
179 *  Setting this to TRUE negatively impacts the time required to preempt
180 *  the IDLE task from an interrupt because the floating point context
181 *  must be saved as part of the preemption.
182 */
183
184#define CPU_IDLE_TASK_IS_FP      FALSE
185
186/*
187 *  Should the saving of the floating point registers be deferred
188 *  until a context switch is made to another different floating point
189 *  task?
190 *
191 *  If TRUE, then the floating point context will not be stored until
192 *  necessary.  It will remain in the floating point registers and not
193 *  disturned until another floating point task is switched to.
194 *
195 *  If FALSE, then the floating point context is saved when a floating
196 *  point task is switched out and restored when the next floating point
197 *  task is restored.  The state of the floating point registers between
198 *  those two operations is not specified.
199 *
200 *  If the floating point context does NOT have to be saved as part of
201 *  interrupt dispatching, then it should be safe to set this to TRUE.
202 *
203 *  Setting this flag to TRUE results in using a different algorithm
204 *  for deciding when to save and restore the floating point context.
205 *  The deferred FP switch algorithm minimizes the number of times
206 *  the FP context is saved and restored.  The FP context is not saved
207 *  until a context switch is made to another, different FP task.
208 *  Thus in a system with only one FP task, the FP context will never
209 *  be saved or restored.
210 */
211
212#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
213
214/*
215 *  Does this port provide a CPU dependent IDLE task implementation?
216 *
217 *  If TRUE, then the routine _CPU_Thread_Idle_body
218 *  must be provided and is the default IDLE thread body instead of
219 *  _CPU_Thread_Idle_body.
220 *
221 *  If FALSE, then use the generic IDLE thread body if the BSP does
222 *  not provide one.
223 *
224 *  This is intended to allow for supporting processors which have
225 *  a low power or idle mode.  When the IDLE thread is executed, then
226 *  the CPU can be powered down.
227 *
228 *  The order of precedence for selecting the IDLE thread body is:
229 *
230 *    1.  BSP provided
231 *    2.  CPU dependent (if provided)
232 *    3.  generic (if no BSP and no CPU dependent)
233 */
234
235#define CPU_PROVIDES_IDLE_THREAD_BODY    TRUE
236
237/*
238 *  Does the stack grow up (toward higher addresses) or down
239 *  (toward lower addresses)?
240 *
241 *  If TRUE, then the grows upward.
242 *  If FALSE, then the grows toward smaller addresses.
243 */
244
245#if defined(hppa1_1)
246#define CPU_STACK_GROWS_UP               TRUE
247#elif defined(sparc) || defined(i386) || defined(__i386__)
248#define CPU_STACK_GROWS_UP               FALSE
249#else
250#error "unknown CPU!!"
251#endif
252
253
254/*
255 *  The following is the variable attribute used to force alignment
256 *  of critical RTEMS structures.  On some processors it may make
257 *  sense to have these aligned on tighter boundaries than
258 *  the minimum requirements of the compiler in order to have as
259 *  much of the critical data area as possible in a cache line.
260 *
261 *  The placement of this macro in the declaration of the variables
262 *  is based on the syntactically requirements of the GNU C
263 *  "__attribute__" extension.  For example with GNU C, use
264 *  the following to force a structures to a 32 byte boundary.
265 *
266 *      __attribute__ ((aligned (32)))
267 *
268 *  NOTE:  Currently only the Priority Bit Map table uses this feature.
269 *         To benefit from using this, the data must be heavily
270 *         used so it will stay in the cache and used frequently enough
271 *         in the executive to justify turning this on.
272 */
273
274#ifdef __GNUC__
275#define CPU_STRUCTURE_ALIGNMENT          __attribute__ ((aligned (32)))
276#else
277#define CPU_STRUCTURE_ALIGNMENT
278#endif
279
280/*
281 *  Define what is required to specify how the network to host conversion
282 *  routines are handled.
283 */
284
285#if defined(hppa1_1) || defined(sparc)
286#define CPU_CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES FALSE
287#define CPU_BIG_ENDIAN                           TRUE
288#define CPU_LITTLE_ENDIAN                        FALSE
289#elif defined(i386) || defined(__i386__)
290#define CPU_CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES FALSE
291#define CPU_BIG_ENDIAN                           FALSE
292#define CPU_LITTLE_ENDIAN                        TRUE
293#else
294#error "Unknown CPU!!!"
295#endif
296
297/*
298 *  The following defines the number of bits actually used in the
299 *  interrupt field of the task mode.  How those bits map to the
300 *  CPU interrupt levels is defined by the routine _CPU_ISR_Set_level().
301 */
302
303#define CPU_MODES_INTERRUPT_MASK   0x00000001
304
305#define CPU_NAME "UNIX"
306
307/*
308 *  Processor defined structures
309 *
310 *  Examples structures include the descriptor tables from the i386
311 *  and the processor control structure on the i960ca.
312 */
313
314/* may need to put some structures here.  */
315
316#if defined(hppa1_1)
317/*
318 * Word indices within a jmp_buf structure
319 */
320
321#ifdef RTEMS_NEWLIB_SETJMP
322#define RP_OFF       6
323#define SP_OFF       2
324#define R3_OFF      10
325#define R4_OFF      11
326#define R5_OFF      12
327#define R6_OFF      13
328#define R7_OFF      14
329#define R8_OFF      15
330#define R9_OFF      16
331#define R10_OFF     17
332#define R11_OFF     18
333#define R12_OFF     19
334#define R13_OFF     20
335#define R14_OFF     21
336#define R15_OFF     22
337#define R16_OFF     23
338#define R17_OFF     24
339#define R18_OFF     25
340#define DP_OFF      26
341#endif
342
343#ifdef RTEMS_UNIXLIB_SETJMP
344#define RP_OFF       0
345#define SP_OFF       1
346#define R3_OFF       4
347#define R4_OFF       5
348#define R5_OFF       6
349#define R6_OFF       7
350#define R7_OFF       8
351#define R8_OFF       9
352#define R9_OFF      10
353#define R10_OFF     11
354#define R11_OFF     12
355#define R12_OFF     13
356#define R13_OFF     14
357#define R14_OFF     15
358#define R15_OFF     16
359#define R16_OFF     17
360#define R17_OFF     18
361#define R18_OFF     19
362#define DP_OFF      20
363#endif
364#endif
365
366#if defined(i386) || defined(__i386__)
367 
368#ifdef RTEMS_NEWLIB
369#error "Newlib not installed"
370#endif
371 
372/*
373 *  For Linux 1.1
374 */
375 
376#ifdef RTEMS_UNIXLIB
377#define EBX_OFF    0
378#define ESI_OFF    1
379#define EDI_OFF    2
380#define EBP_OFF    3
381#define ESP_OFF    4
382#define RET_OFF    5
383#endif
384 
385#endif
386 
387#if defined(sparc)
388
389/*
390 *  Word indices within a jmp_buf structure
391 */
392 
393#ifdef RTEMS_NEWLIB
394#define ADDR_ADJ_OFFSET -8
395#define SP_OFF    0
396#define RP_OFF    1
397#define FP_OFF    2
398#endif
399
400#ifdef RTEMS_UNIXLIB
401#define ADDR_ADJ_OFFSET 0
402#define G0_OFF    0
403#define SP_OFF    1
404#define RP_OFF    2   
405#define FP_OFF    3
406#define I7_OFF    4
407#endif
408
409#endif
410
411/*
412 * Contexts
413 *
414 *  Generally there are 2 types of context to save.
415 *     1. Interrupt registers to save
416 *     2. Task level registers to save
417 *
418 *  This means we have the following 3 context items:
419 *     1. task level context stuff::  Context_Control
420 *     2. floating point task stuff:: Context_Control_fp
421 *     3. special interrupt level context :: Context_Control_interrupt
422 *
423 *  On some processors, it is cost-effective to save only the callee
424 *  preserved registers during a task context switch.  This means
425 *  that the ISR code needs to save those registers which do not
426 *  persist across function calls.  It is not mandatory to make this
427 *  distinctions between the caller/callee saves registers for the
428 *  purpose of minimizing context saved during task switch and on interrupts.
429 *  If the cost of saving extra registers is minimal, simplicity is the
430 *  choice.  Save the same context on interrupt entry as for tasks in
431 *  this case.
432 *
433 *  Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
434 *  care should be used in designing the context area.
435 *
436 *  On some CPUs with hardware floating point support, the Context_Control_fp
437 *  structure will not be used or it simply consist of an array of a
438 *  fixed number of bytes.   This is done when the floating point context
439 *  is dumped by a "FP save context" type instruction and the format
440 *  is not really defined by the CPU.  In this case, there is no need
441 *  to figure out the exact format -- only the size.  Of course, although
442 *  this is enough information for RTEMS, it is probably not enough for
443 *  a debugger such as gdb.  But that is another problem.
444 */
445
446/*
447 *  This is really just the area for the following fields.
448 *
449 *    jmp_buf    regs;
450 *    unsigned32 isr_level;
451 *
452 *  Doing it this way avoids conflicts between the native stuff and the
453 *  RTEMS stuff.
454 *
455 *  NOTE:
456 *      hpux9 setjmp is optimized for the case where the setjmp buffer
457 *      is 8 byte aligned.  In a RISC world, this seems likely to enable
458 *      8 byte copies, especially for the float registers.
459 *      So we always align them on 8 byte boundaries.
460 */
461
462#ifdef __GNUC__
463#define CONTEXT_STRUCTURE_ALIGNMENT          __attribute__ ((aligned (8)))
464#else
465#define CONTEXT_STRUCTURE_ALIGNMENT
466#endif
467
468typedef struct {
469  char      Area[ CPU_CONTEXT_SIZE_IN_BYTES ] CONTEXT_STRUCTURE_ALIGNMENT;
470} Context_Control;
471
472typedef struct {
473} Context_Control_fp;
474
475typedef struct {
476} CPU_Interrupt_frame;
477
478
479/*
480 *  The following table contains the information required to configure
481 *  the UNIX Simulator specific parameters.
482 */
483
484typedef struct {
485  void       (*pretasking_hook)( void );
486  void       (*predriver_hook)( void );
487  void       (*postdriver_hook)( void );
488  void       (*idle_task)( void );
489  boolean      do_zero_of_workspace;
490  unsigned32   interrupt_stack_size;
491  unsigned32   extra_mpci_receive_server_stack;
492  void *     (*stack_allocate_hook)( unsigned32 );
493  void       (*stack_free_hook)( void* );
494  /* end of required fields */
495}   rtems_cpu_table;
496
497/*
498 *  This variable is optional.  It is used on CPUs on which it is difficult
499 *  to generate an "uninitialized" FP context.  It is filled in by
500 *  _CPU_Initialize and copied into the task's FP context area during
501 *  _CPU_Context_Initialize.
502 */
503
504SCORE_EXTERN Context_Control_fp  _CPU_Null_fp_context;
505
506/*
507 *  On some CPUs, RTEMS supports a software managed interrupt stack.
508 *  This stack is allocated by the Interrupt Manager and the switch
509 *  is performed in _ISR_Handler.  These variables contain pointers
510 *  to the lowest and highest addresses in the chunk of memory allocated
511 *  for the interrupt stack.  Since it is unknown whether the stack
512 *  grows up or down (in general), this give the CPU dependent
513 *  code the option of picking the version it wants to use.
514 *
515 *  NOTE: These two variables are required if the macro
516 *        CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
517 */
518
519SCORE_EXTERN void               *_CPU_Interrupt_stack_low;
520SCORE_EXTERN void               *_CPU_Interrupt_stack_high;
521
522/*
523 *  With some compilation systems, it is difficult if not impossible to
524 *  call a high-level language routine from assembly language.  This
525 *  is especially true of commercial Ada compilers and name mangling
526 *  C++ ones.  This variable can be optionally defined by the CPU porter
527 *  and contains the address of the routine _Thread_Dispatch.  This
528 *  can make it easier to invoke that routine at the end of the interrupt
529 *  sequence (if a dispatch is necessary).
530 */
531
532SCORE_EXTERN void           (*_CPU_Thread_dispatch_pointer)();
533
534/*
535 *  Nothing prevents the porter from declaring more CPU specific variables.
536 */
537
538/* XXX: if needed, put more variables here */
539
540/*
541 *  The size of the floating point context area.  On some CPUs this
542 *  will not be a "sizeof" because the format of the floating point
543 *  area is not defined -- only the size is.  This is usually on
544 *  CPUs with a "floating point save context" instruction.
545 */
546
547#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
548
549/*
550 * The size of a frame on the stack
551 */
552
553#if defined(hppa1_1)
554#define CPU_FRAME_SIZE  (32 * 4)
555#elif defined(sparc)
556#define CPU_FRAME_SIZE  (112)   /* based on disassembled test code */
557#elif defined(i386) || defined(__i386__)
558#define CPU_FRAME_SIZE  (24)  /* return address, sp, and bp pushed plus fudge */
559#else
560#error "Unknown CPU!!!"
561#endif
562
563/*
564 *  Amount of extra stack (above minimum stack size) required by
565 *  MPCI receive server thread.  Remember that in a multiprocessor
566 *  system this thread must exist and be able to process all directives.
567 */
568
569#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
570
571/*
572 *  This defines the number of entries in the ISR_Vector_table managed
573 *  by RTEMS.
574 */
575
576#define CPU_INTERRUPT_NUMBER_OF_VECTORS      64
577#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
578
579/*
580 *  Should be large enough to run all RTEMS tests.  This insures
581 *  that a "reasonable" small application should not have any problems.
582 */
583
584#define CPU_STACK_MINIMUM_SIZE          (16 * 1024)
585
586/*
587 *  CPU's worst alignment requirement for data types on a byte boundary.  This
588 *  alignment does not take into account the requirements for the stack.
589 */
590
591#define CPU_ALIGNMENT              8
592
593/*
594 *  This number corresponds to the byte alignment requirement for the
595 *  heap handler.  This alignment requirement may be stricter than that
596 *  for the data types alignment specified by CPU_ALIGNMENT.  It is
597 *  common for the heap to follow the same alignment requirement as
598 *  CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict enough for the heap,
599 *  then this should be set to CPU_ALIGNMENT.
600 *
601 *  NOTE:  This does not have to be a power of 2.  It does have to
602 *         be greater or equal to than CPU_ALIGNMENT.
603 */
604
605#define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT
606
607/*
608 *  This number corresponds to the byte alignment requirement for memory
609 *  buffers allocated by the partition manager.  This alignment requirement
610 *  may be stricter than that for the data types alignment specified by
611 *  CPU_ALIGNMENT.  It is common for the partition to follow the same
612 *  alignment requirement as CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict
613 *  enough for the partition, then this should be set to CPU_ALIGNMENT.
614 *
615 *  NOTE:  This does not have to be a power of 2.  It does have to
616 *         be greater or equal to than CPU_ALIGNMENT.
617 */
618
619#define CPU_PARTITION_ALIGNMENT    CPU_ALIGNMENT
620
621/*
622 *  This number corresponds to the byte alignment requirement for the
623 *  stack.  This alignment requirement may be stricter than that for the
624 *  data types alignment specified by CPU_ALIGNMENT.  If the CPU_ALIGNMENT
625 *  is strict enough for the stack, then this should be set to 0.
626 *
627 *  NOTE:  This must be a power of 2 either 0 or greater than CPU_ALIGNMENT.
628 */
629
630#define CPU_STACK_ALIGNMENT        64
631
632/* ISR handler macros */
633
634/*
635 *  Disable all interrupts for an RTEMS critical section.  The previous
636 *  level is returned in _level.
637 */
638
639extern unsigned32 _CPU_ISR_Disable_support(void);
640
641#define _CPU_ISR_Disable( _level ) \
642    do { \
643      (_level) = _CPU_ISR_Disable_support(); \
644    } while ( 0 )
645
646/*
647 *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
648 *  This indicates the end of an RTEMS critical section.  The parameter
649 *  _level is not modified.
650 */
651
652void _CPU_ISR_Enable(unsigned32 level);
653
654/*
655 *  This temporarily restores the interrupt to _level before immediately
656 *  disabling them again.  This is used to divide long RTEMS critical
657 *  sections into two or more parts.  The parameter _level is not
658 * modified.
659 */
660
661#define _CPU_ISR_Flash( _level ) \
662  do { \
663      register unsigned32 _ignored = 0; \
664      _CPU_ISR_Enable( (_level) ); \
665      _CPU_ISR_Disable( _ignored ); \
666  } while ( 0 )
667
668/*
669 *  Map interrupt level in task mode onto the hardware that the CPU
670 *  actually provides.  Currently, interrupt levels which do not
671 *  map onto the CPU in a generic fashion are undefined.  Someday,
672 *  it would be nice if these were "mapped" by the application
673 *  via a callout.  For example, m68k has 8 levels 0 - 7, levels
674 *  8 - 255 would be available for bsp/application specific meaning.
675 *  This could be used to manage a programmable interrupt controller
676 *  via the rtems_task_mode directive.
677 */
678
679#define _CPU_ISR_Set_level( new_level ) \
680  { \
681    if ( new_level == 0 ) _CPU_ISR_Enable( 0 ); \
682    else                  _CPU_ISR_Enable( 1 ); \
683  }
684
685unsigned32 _CPU_ISR_Get_level( void );
686
687/* end of ISR handler macros */
688
689/* Context handler macros */
690
691/*
692 *  This routine is responsible for somehow restarting the currently
693 *  executing task.  If you are lucky, then all that is necessary
694 *  is restoring the context.  Otherwise, there will need to be
695 *  a special assembly routine which does something special in this
696 *  case.  Context_Restore should work most of the time.  It will
697 *  not work if restarting self conflicts with the stack frame
698 *  assumptions of restoring a context.
699 */
700
701#define _CPU_Context_Restart_self( _the_context ) \
702   _CPU_Context_restore( (_the_context) );
703
704/*
705 *  The purpose of this macro is to allow the initial pointer into
706 *  a floating point context area (used to save the floating point
707 *  context) to be at an arbitrary place in the floating point
708 *  context area.
709 *
710 *  This is necessary because some FP units are designed to have
711 *  their context saved as a stack which grows into lower addresses.
712 *  Other FP units can be saved by simply moving registers into offsets
713 *  from the base of the context area.  Finally some FP units provide
714 *  a "dump context" instruction which could fill in from high to low
715 *  or low to high based on the whim of the CPU designers.
716 */
717
718#define _CPU_Context_Fp_start( _base, _offset ) \
719   ( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
720
721/*
722 *  This routine initializes the FP context area passed to it to.
723 *  There are a few standard ways in which to initialize the
724 *  floating point context.  The code included for this macro assumes
725 *  that this is a CPU in which a "initial" FP context was saved into
726 *  _CPU_Null_fp_context and it simply copies it to the destination
727 *  context passed to it.
728 *
729 *  Other models include (1) not doing anything, and (2) putting
730 *  a "null FP status word" in the correct place in the FP context.
731 */
732
733#define _CPU_Context_Initialize_fp( _destination ) \
734  { \
735   *((Context_Control_fp *) *((void **) _destination)) = _CPU_Null_fp_context; \
736  }
737
738#define _CPU_Context_save_fp( _fp_context ) \
739    _CPU_Save_float_context( *(Context_Control_fp **)(_fp_context))
740
741#define _CPU_Context_restore_fp( _fp_context ) \
742    _CPU_Restore_float_context( *(Context_Control_fp **)(_fp_context))
743
744extern void _CPU_Context_Initialize(
745  Context_Control  *_the_context,
746  unsigned32       *_stack_base,
747  unsigned32        _size,
748  unsigned32        _new_level,
749  void             *_entry_point,
750  boolean           _is_fp
751);
752
753/* end of Context handler macros */
754
755/* Fatal Error manager macros */
756
757/*
758 *  This routine copies _error into a known place -- typically a stack
759 *  location or a register, optionally disables interrupts, and
760 *  halts/stops the CPU.
761 */
762
763#define _CPU_Fatal_halt( _error ) \
764    _CPU_Fatal_error( _error )
765
766/* end of Fatal Error manager macros */
767
768/* Bitfield handler macros */
769
770/*
771 *  This routine sets _output to the bit number of the first bit
772 *  set in _value.  _value is of CPU dependent type Priority_Bit_map_control.
773 *  This type may be either 16 or 32 bits wide although only the 16
774 *  least significant bits will be used.
775 *
776 *  There are a number of variables in using a "find first bit" type
777 *  instruction.
778 *
779 *    (1) What happens when run on a value of zero?
780 *    (2) Bits may be numbered from MSB to LSB or vice-versa.
781 *    (3) The numbering may be zero or one based.
782 *    (4) The "find first bit" instruction may search from MSB or LSB.
783 *
784 *  RTEMS guarantees that (1) will never happen so it is not a concern.
785 *  (2),(3), (4) are handled by the macros _CPU_Priority_mask() and
786 *  _CPU_Priority_bits_index().  These three form a set of routines
787 *  which must logically operate together.  Bits in the _value are
788 *  set and cleared based on masks built by _CPU_Priority_mask().
789 *  The basic major and minor values calculated by _Priority_Major()
790 *  and _Priority_Minor() are "massaged" by _CPU_Priority_bits_index()
791 *  to properly range between the values returned by the "find first bit"
792 *  instruction.  This makes it possible for _Priority_Get_highest() to
793 *  calculate the major and directly index into the minor table.
794 *  This mapping is necessary to ensure that 0 (a high priority major/minor)
795 *  is the first bit found.
796 *
797 *  This entire "find first bit" and mapping process depends heavily
798 *  on the manner in which a priority is broken into a major and minor
799 *  components with the major being the 4 MSB of a priority and minor
800 *  the 4 LSB.  Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
801 *  priority.  And (15 << 4) + 14 corresponds to priority 254 -- the next
802 *  to the lowest priority.
803 *
804 *  If your CPU does not have a "find first bit" instruction, then
805 *  there are ways to make do without it.  Here are a handful of ways
806 *  to implement this in software:
807 *
808 *    - a series of 16 bit test instructions
809 *    - a "binary search using if's"
810 *    - _number = 0
811 *      if _value > 0x00ff
812 *        _value >>=8
813 *        _number = 8;
814 *
815 *      if _value > 0x0000f
816 *        _value >=8
817 *        _number += 4
818 *
819 *      _number += bit_set_table[ _value ]
820 *
821 *    where bit_set_table[ 16 ] has values which indicate the first
822 *      bit set
823 */
824
825/*
826 *  The UNIX port uses the generic C algorithm for bitfield scan to avoid
827 *  dependencies on either a native bitscan instruction or an ffs() in the
828 *  C library.
829 */
830 
831#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
832#define CPU_USE_GENERIC_BITFIELD_DATA TRUE
833 
834/* end of Bitfield handler macros */
835 
836/* Priority handler handler macros */
837 
838/*
839 *  The UNIX port uses the generic C algorithm for bitfield scan to avoid
840 *  dependencies on either a native bitscan instruction or an ffs() in the
841 *  C library.
842 */
843 
844/* end of Priority handler macros */
845
846/* functions */
847
848/*
849 *  _CPU_Initialize
850 *
851 *  This routine performs CPU dependent initialization.
852 */
853
854void _CPU_Initialize(
855  rtems_cpu_table  *cpu_table,
856  void      (*thread_dispatch)
857);
858
859/*
860 *  _CPU_ISR_install_raw_handler
861 *
862 *  This routine installs a "raw" interrupt handler directly into the
863 *  processor's vector table.
864 */
865 
866void _CPU_ISR_install_raw_handler(
867  unsigned32  vector,
868  proc_ptr    new_handler,
869  proc_ptr   *old_handler
870);
871
872/*
873 *  _CPU_ISR_install_vector
874 *
875 *  This routine installs an interrupt vector.
876 */
877
878void _CPU_ISR_install_vector(
879  unsigned32  vector,
880  proc_ptr    new_handler,
881  proc_ptr   *old_handler
882);
883
884/*
885 *  _CPU_Install_interrupt_stack
886 *
887 *  This routine installs the hardware interrupt stack pointer.
888 *
889 *  NOTE:  It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK
890 *         is TRUE.
891 */
892
893void _CPU_Install_interrupt_stack( void );
894
895/*
896 *  _CPU_Thread_Idle_body
897 *
898 *  This routine is the CPU dependent IDLE thread body.
899 *
900 *  NOTE:  It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY
901 *         is TRUE.
902 */
903
904void _CPU_Thread_Idle_body( void );
905
906/*
907 *  _CPU_Context_switch
908 *
909 *  This routine switches from the run context to the heir context.
910 */
911
912void _CPU_Context_switch(
913  Context_Control  *run,
914  Context_Control  *heir
915);
916
917/*
918 *  _CPU_Context_restore
919 *
920 *  This routine is generally used only to restart self in an
921 *  efficient manner.  It may simply be a label in _CPU_Context_switch.
922 *
923 *  NOTE: May be unnecessary to reload some registers.
924 */
925
926void _CPU_Context_restore(
927  Context_Control *new_context
928);
929
930/*
931 *  _CPU_Save_float_context
932 *
933 *  This routine saves the floating point context passed to it.
934 */
935
936void _CPU_Save_float_context(
937  Context_Control_fp *fp_context_ptr
938);
939
940/*
941 *  _CPU_Restore_float_context
942 *
943 *  This routine restores the floating point context passed to it.
944 */
945
946void _CPU_Restore_float_context(
947  Context_Control_fp *fp_context_ptr
948);
949
950
951void _CPU_ISR_Set_signal_level(
952  unsigned32 level
953);
954
955void _CPU_Fatal_error(
956  unsigned32 _error
957);
958
959/*  The following routine swaps the endian format of an unsigned int.
960 *  It must be static because it is referenced indirectly.
961 *
962 *  This version will work on any processor, but if there is a better
963 *  way for your CPU PLEASE use it.  The most common way to do this is to:
964 *
965 *     swap least significant two bytes with 16-bit rotate
966 *     swap upper and lower 16-bits
967 *     swap most significant two bytes with 16-bit rotate
968 *
969 *  Some CPUs have special instructions which swap a 32-bit quantity in
970 *  a single instruction (e.g. i486).  It is probably best to avoid
971 *  an "endian swapping control bit" in the CPU.  One good reason is
972 *  that interrupts would probably have to be disabled to insure that
973 *  an interrupt does not try to access the same "chunk" with the wrong
974 *  endian.  Another good reason is that on some CPUs, the endian bit
975 *  endianness for ALL fetches -- both code and data -- so the code
976 *  will be fetched incorrectly.
977 */
978 
979static inline unsigned int CPU_swap_u32(
980  unsigned int value
981)
982{
983  unsigned32 byte1, byte2, byte3, byte4, swapped;
984 
985  byte4 = (value >> 24) & 0xff;
986  byte3 = (value >> 16) & 0xff;
987  byte2 = (value >> 8)  & 0xff;
988  byte1 =  value        & 0xff;
989 
990  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
991  return( swapped );
992}
993
994/*
995 *  Special Purpose Routines to hide the use of UNIX system calls.
996 */
997
998
999/*
1000 *  Pointer to a sync io  Handler
1001 */
1002
1003typedef void ( *rtems_sync_io_handler )(
1004  int fd,
1005  boolean read,
1006  boolean wrtie,
1007  boolean except
1008);
1009
1010/* returns -1 if fd to large, 0 is successful */
1011int _CPU_Set_sync_io_handler(
1012  int fd,
1013  boolean read,
1014  boolean write,
1015  boolean except,
1016  rtems_sync_io_handler handler
1017);
1018
1019/* returns -1 if fd to large, o if successful */
1020int _CPU_Clear_sync_io_handler(
1021  int fd
1022);
1023
1024int _CPU_Get_clock_vector( void );
1025
1026void _CPU_Start_clock( 
1027  int microseconds
1028);
1029
1030void _CPU_Stop_clock( void );
1031
1032void _CPU_SHM_Init( 
1033  unsigned32   maximum_nodes,
1034  boolean      is_master_node,
1035  void       **shm_address,
1036  unsigned32  *shm_length
1037);
1038
1039int _CPU_Get_pid( void );
1040 
1041int _CPU_SHM_Get_vector( void );
1042 
1043void _CPU_SHM_Send_interrupt(
1044  int pid,
1045  int vector
1046);
1047 
1048void _CPU_SHM_Lock( 
1049  int semaphore
1050);
1051
1052void _CPU_SHM_Unlock(
1053  int semaphore
1054);
1055
1056#ifdef __cplusplus
1057}
1058#endif
1059
1060#endif
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