source: rtems/c/src/exec/score/cpu/unix/cpu.h @ 637df35

4.104.114.84.95
Last change on this file since 637df35 was 637df35, checked in by Joel Sherrill <joel.sherrill@…>, on Jul 12, 1995 at 7:47:25 PM

Ada95, gnat, go32

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1/*  cpu.h
2 *
3 *  This include file contains information pertaining to the HP
4 *  PA-RISC processor (Level 1.1).
5 *
6 *  COPYRIGHT (c) 1994 by Division Incorporated
7 *
8 *  To anyone who acknowledges that this file is provided "AS IS"
9 *  without any express or implied warranty:
10 *      permission to use, copy, modify, and distribute this file
11 *      for any purpose is hereby granted without fee, provided that
12 *      the above copyright notice and this notice appears in all
13 *      copies, and that the name of Division Incorporated not be
14 *      used in advertising or publicity pertaining to distribution
15 *      of the software without specific, written prior permission.
16 *      Division Incorporated makes no representations about the
17 *      suitability of this software for any purpose.
18 *
19 *  $Id$
20 */
21
22#ifndef __CPU_h
23#define __CPU_h
24
25#ifdef __cplusplus
26extern "C" {
27#endif
28
29#include <rtems/unix.h>
30#ifndef ASM
31#include <rtems/unixtypes.h>
32#endif
33
34#if defined(solaris2)
35#undef  _POSIX_C_SOURCE
36#define _POSIX_C_SOURCE 3
37#undef  __STRICT_ANSI__
38#define __STRICT_ANSI__
39#endif
40
41#if 0
42
43/*
44 *  In order to get the types and prototypes used in this file under
45 *  Solaris 2.3, it is necessary to pull the following magic.
46 */
47
48#if defined(solaris2)
49#warning "Ignore the undefining __STDC__ warning"
50#undef __STDC__
51#define __STDC__ 0
52#undef  _POSIX_C_SOURCE
53#endif
54
55#endif
56
57#include <setjmp.h>
58#include <signal.h>
59
60/* conditional compilation parameters */
61
62/*
63 *  Should the calls to _Thread_Enable_dispatch be inlined?
64 *
65 *  If TRUE, then they are inlined.
66 *  If FALSE, then a subroutine call is made.
67 *
68 *  Basically this is an example of the classic trade-off of size
69 *  versus speed.  Inlining the call (TRUE) typically increases the
70 *  size of RTEMS while speeding up the enabling of dispatching.
71 *  [NOTE: In general, the _Thread_Dispatch_disable_level will
72 *  only be 0 or 1 unless you are in an interrupt handler and that
73 *  interrupt handler invokes the executive.]  When not inlined
74 *  something calls _Thread_Enable_dispatch which in turns calls
75 *  _Thread_Dispatch.  If the enable dispatch is inlined, then
76 *  one subroutine call is avoided entirely.]
77 */
78
79#define CPU_INLINE_ENABLE_DISPATCH       FALSE
80
81/*
82 *  Should the body of the search loops in _Thread_queue_Enqueue_priority
83 *  be unrolled one time?  In unrolled each iteration of the loop examines
84 *  two "nodes" on the chain being searched.  Otherwise, only one node
85 *  is examined per iteration.
86 *
87 *  If TRUE, then the loops are unrolled.
88 *  If FALSE, then the loops are not unrolled.
89 *
90 *  The primary factor in making this decision is the cost of disabling
91 *  and enabling interrupts (_ISR_Flash) versus the cost of rest of the
92 *  body of the loop.  On some CPUs, the flash is more expensive than
93 *  one iteration of the loop body.  In this case, it might be desirable
94 *  to unroll the loop.  It is important to note that on some CPUs, this
95 *  code is the longest interrupt disable period in RTEMS.  So it is
96 *  necessary to strike a balance when setting this parameter.
97 */
98
99#define CPU_UNROLL_ENQUEUE_PRIORITY      TRUE
100
101/*
102 *  Does RTEMS manage a dedicated interrupt stack in software?
103 *
104 *  If TRUE, then a stack is allocated in _Interrupt_Manager_initialization.
105 *  If FALSE, nothing is done.
106 *
107 *  If the CPU supports a dedicated interrupt stack in hardware,
108 *  then it is generally the responsibility of the BSP to allocate it
109 *  and set it up.
110 *
111 *  If the CPU does not support a dedicated interrupt stack, then
112 *  the porter has two options: (1) execute interrupts on the
113 *  stack of the interrupted task, and (2) have RTEMS manage a dedicated
114 *  interrupt stack.
115 *
116 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
117 *
118 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
119 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
120 *  possible that both are FALSE for a particular CPU.  Although it
121 *  is unclear what that would imply about the interrupt processing
122 *  procedure on that CPU.
123 */
124
125#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE
126
127/*
128 *  Does this CPU have hardware support for a dedicated interrupt stack?
129 *
130 *  If TRUE, then it must be installed during initialization.
131 *  If FALSE, then no installation is performed.
132 *
133 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
134 *
135 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
136 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
137 *  possible that both are FALSE for a particular CPU.  Although it
138 *  is unclear what that would imply about the interrupt processing
139 *  procedure on that CPU.
140 */
141
142#define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE
143
144/*
145 *  Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
146 *
147 *  If TRUE, then the memory is allocated during initialization.
148 *  If FALSE, then the memory is allocated during initialization.
149 *
150 *  This should be TRUE if CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE
151 *  or CPU_INSTALL_HARDWARE_INTERRUPT_STACK is TRUE.
152 */
153
154#define CPU_ALLOCATE_INTERRUPT_STACK FALSE
155
156/*
157 *  Does the CPU have hardware floating point?
158 *
159 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
160 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
161 *
162 *  If there is a FP coprocessor such as the i387 or mc68881, then
163 *  the answer is TRUE.
164 *
165 *  The macro name "NO_CPU_HAS_FPU" should be made CPU specific.
166 *  It indicates whether or not this CPU model has FP support.  For
167 *  example, it would be possible to have an i386_nofp CPU model
168 *  which set this to false to indicate that you have an i386 without
169 *  an i387 and wish to leave floating point support out of RTEMS.
170 */
171
172#define CPU_HARDWARE_FP     TRUE
173
174/*
175 *  Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
176 *
177 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
178 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
179 *
180 *  So far, the only CPU in which this option has been used is the
181 *  HP PA-RISC.  The HP C compiler and gcc both implicitly use the
182 *  floating point registers to perform integer multiplies.  If
183 *  a function which you would not think utilize the FP unit DOES,
184 *  then one can not easily predict which tasks will use the FP hardware.
185 *  In this case, this option should be TRUE.
186 *
187 *  If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
188 */
189
190#define CPU_ALL_TASKS_ARE_FP     FALSE
191
192/*
193 *  Should the IDLE task have a floating point context?
194 *
195 *  If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
196 *  and it has a floating point context which is switched in and out.
197 *  If FALSE, then the IDLE task does not have a floating point context.
198 *
199 *  Setting this to TRUE negatively impacts the time required to preempt
200 *  the IDLE task from an interrupt because the floating point context
201 *  must be saved as part of the preemption.
202 */
203
204#define CPU_IDLE_TASK_IS_FP      FALSE
205
206/*
207 *  Should the saving of the floating point registers be deferred
208 *  until a context switch is made to another different floating point
209 *  task?
210 *
211 *  If TRUE, then the floating point context will not be stored until
212 *  necessary.  It will remain in the floating point registers and not
213 *  disturned until another floating point task is switched to.
214 *
215 *  If FALSE, then the floating point context is saved when a floating
216 *  point task is switched out and restored when the next floating point
217 *  task is restored.  The state of the floating point registers between
218 *  those two operations is not specified.
219 *
220 *  If the floating point context does NOT have to be saved as part of
221 *  interrupt dispatching, then it should be safe to set this to TRUE.
222 *
223 *  Setting this flag to TRUE results in using a different algorithm
224 *  for deciding when to save and restore the floating point context.
225 *  The deferred FP switch algorithm minimizes the number of times
226 *  the FP context is saved and restored.  The FP context is not saved
227 *  until a context switch is made to another, different FP task.
228 *  Thus in a system with only one FP task, the FP context will never
229 *  be saved or restored.
230 */
231
232#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
233
234/*
235 *  Does this port provide a CPU dependent IDLE task implementation?
236 *
237 *  If TRUE, then the routine _CPU_Internal_threads_Idle_thread_body
238 *  must be provided and is the default IDLE thread body instead of
239 *  _Internal_threads_Idle_thread_body.
240 *
241 *  If FALSE, then use the generic IDLE thread body if the BSP does
242 *  not provide one.
243 *
244 *  This is intended to allow for supporting processors which have
245 *  a low power or idle mode.  When the IDLE thread is executed, then
246 *  the CPU can be powered down.
247 *
248 *  The order of precedence for selecting the IDLE thread body is:
249 *
250 *    1.  BSP provided
251 *    2.  CPU dependent (if provided)
252 *    3.  generic (if no BSP and no CPU dependent)
253 */
254
255#define CPU_PROVIDES_IDLE_THREAD_BODY    TRUE
256
257/*
258 *  Does the stack grow up (toward higher addresses) or down
259 *  (toward lower addresses)?
260 *
261 *  If TRUE, then the grows upward.
262 *  If FALSE, then the grows toward smaller addresses.
263 */
264
265#if defined(hppa1_1)
266#define CPU_STACK_GROWS_UP               TRUE
267#elif defined(sparc)
268#define CPU_STACK_GROWS_UP               FALSE
269#else
270#error "unknown CPU!!"
271#endif
272
273
274/*
275 *  The following is the variable attribute used to force alignment
276 *  of critical RTEMS structures.  On some processors it may make
277 *  sense to have these aligned on tighter boundaries than
278 *  the minimum requirements of the compiler in order to have as
279 *  much of the critical data area as possible in a cache line.
280 *
281 *  The placement of this macro in the declaration of the variables
282 *  is based on the syntactically requirements of the GNU C
283 *  "__attribute__" extension.  For example with GNU C, use
284 *  the following to force a structures to a 32 byte boundary.
285 *
286 *      __attribute__ ((aligned (32)))
287 *
288 *  NOTE:  Currently only the Priority Bit Map table uses this feature.
289 *         To benefit from using this, the data must be heavily
290 *         used so it will stay in the cache and used frequently enough
291 *         in the executive to justify turning this on.
292 */
293
294#define CPU_STRUCTURE_ALIGNMENT          __attribute__ ((aligned (32)))
295
296/*
297 *  The following defines the number of bits actually used in the
298 *  interrupt field of the task mode.  How those bits map to the
299 *  CPU interrupt levels is defined by the routine _CPU_ISR_Set_level().
300 */
301
302#define CPU_MODES_INTERRUPT_MASK   0x00000001
303
304#define CPU_NAME "UNIX"
305
306/*
307 *  Processor defined structures
308 *
309 *  Examples structures include the descriptor tables from the i386
310 *  and the processor control structure on the i960ca.
311 */
312
313/* may need to put some structures here.  */
314
315#if defined(hppa1_1)
316/*
317 * Word indices within a jmp_buf structure
318 */
319
320#ifdef RTEMS_NEWLIB
321#define RP_OFF       6
322#define SP_OFF       2
323#define R3_OFF      10
324#define R4_OFF      11
325#define R5_OFF      12
326#define R6_OFF      13
327#define R7_OFF      14
328#define R8_OFF      15
329#define R9_OFF      16
330#define R10_OFF     17
331#define R11_OFF     18
332#define R12_OFF     19
333#define R13_OFF     20
334#define R14_OFF     21
335#define R15_OFF     22
336#define R16_OFF     23
337#define R17_OFF     24
338#define R18_OFF     25
339#define DP_OFF      26
340#endif
341
342#ifdef RTEMS_UNIXLIB
343#define RP_OFF       0
344#define SP_OFF       1
345#define R3_OFF       4
346#define R4_OFF       5
347#define R5_OFF       6
348#define R6_OFF       7
349#define R7_OFF       8
350#define R8_OFF       9
351#define R9_OFF      10
352#define R10_OFF     11
353#define R11_OFF     12
354#define R12_OFF     13
355#define R13_OFF     14
356#define R14_OFF     15
357#define R15_OFF     16
358#define R16_OFF     17
359#define R17_OFF     18
360#define R18_OFF     19
361#define DP_OFF      20
362#endif
363#endif
364
365#if defined(sparc)
366
367/*
368 *  Word indices within a jmp_buf structure
369 */
370 
371#ifdef RTEMS_NEWLIB
372#define ADDR_ADJ_OFFSET -8
373#define SP_OFF    0
374#define RP_OFF    1
375#define FP_OFF    2
376#endif
377
378#ifdef RTEMS_UNIXLIB
379#define ADDR_ADJ_OFFSET 0
380#define G0_OFF    0
381#define SP_OFF    1
382#define RP_OFF    2   
383#define FP_OFF    3
384#define I7_OFF    4
385#endif
386
387#endif
388
389/*
390 * Contexts
391 *
392 *  Generally there are 2 types of context to save.
393 *     1. Interrupt registers to save
394 *     2. Task level registers to save
395 *
396 *  This means we have the following 3 context items:
397 *     1. task level context stuff::  Context_Control
398 *     2. floating point task stuff:: Context_Control_fp
399 *     3. special interrupt level context :: Context_Control_interrupt
400 *
401 *  On some processors, it is cost-effective to save only the callee
402 *  preserved registers during a task context switch.  This means
403 *  that the ISR code needs to save those registers which do not
404 *  persist across function calls.  It is not mandatory to make this
405 *  distinctions between the caller/callee saves registers for the
406 *  purpose of minimizing context saved during task switch and on interrupts.
407 *  If the cost of saving extra registers is minimal, simplicity is the
408 *  choice.  Save the same context on interrupt entry as for tasks in
409 *  this case.
410 *
411 *  Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
412 *  care should be used in designing the context area.
413 *
414 *  On some CPUs with hardware floating point support, the Context_Control_fp
415 *  structure will not be used or it simply consist of an array of a
416 *  fixed number of bytes.   This is done when the floating point context
417 *  is dumped by a "FP save context" type instruction and the format
418 *  is not really defined by the CPU.  In this case, there is no need
419 *  to figure out the exact format -- only the size.  Of course, although
420 *  this is enough information for RTEMS, it is probably not enough for
421 *  a debugger such as gdb.  But that is another problem.
422 */
423
424typedef struct {
425  jmp_buf   regs;
426  sigset_t  isr_level;
427  int       junk;
428} Context_Control;
429
430typedef struct {
431} Context_Control_fp;
432
433typedef struct {
434} CPU_Interrupt_frame;
435
436
437/*
438 *  The following table contains the information required to configure
439 *  the XXX processor specific parameters.
440 *
441 *  NOTE: The interrupt_stack_size field is required if
442 *        CPU_ALLOCATE_INTERRUPT_STACK is defined as TRUE.
443 *
444 *        The pretasking_hook, predriver_hook, and postdriver_hook,
445 *        and the do_zero_of_workspace fields are required on ALL CPUs.
446 */
447
448typedef struct {
449  void       (*pretasking_hook)( void );
450  void       (*predriver_hook)( void );
451  void       (*postdriver_hook)( void );
452  void       (*idle_task)( void );
453  boolean      do_zero_of_workspace;
454  unsigned32   interrupt_stack_size;
455  unsigned32   extra_system_initialization_stack;
456}   rtems_cpu_table;
457
458/*
459 *  This variable is optional.  It is used on CPUs on which it is difficult
460 *  to generate an "uninitialized" FP context.  It is filled in by
461 *  _CPU_Initialize and copied into the task's FP context area during
462 *  _CPU_Context_Initialize.
463 */
464
465EXTERN Context_Control_fp  _CPU_Null_fp_context;
466
467/*
468 *  On some CPUs, RTEMS supports a software managed interrupt stack.
469 *  This stack is allocated by the Interrupt Manager and the switch
470 *  is performed in _ISR_Handler.  These variables contain pointers
471 *  to the lowest and highest addresses in the chunk of memory allocated
472 *  for the interrupt stack.  Since it is unknown whether the stack
473 *  grows up or down (in general), this give the CPU dependent
474 *  code the option of picking the version it wants to use.
475 *
476 *  NOTE: These two variables are required if the macro
477 *        CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
478 */
479
480EXTERN void               *_CPU_Interrupt_stack_low;
481EXTERN void               *_CPU_Interrupt_stack_high;
482
483/*
484 *  With some compilation systems, it is difficult if not impossible to
485 *  call a high-level language routine from assembly language.  This
486 *  is especially true of commercial Ada compilers and name mangling
487 *  C++ ones.  This variable can be optionally defined by the CPU porter
488 *  and contains the address of the routine _Thread_Dispatch.  This
489 *  can make it easier to invoke that routine at the end of the interrupt
490 *  sequence (if a dispatch is necessary).
491 */
492
493EXTERN void           (*_CPU_Thread_dispatch_pointer)();
494
495/*
496 *  Nothing prevents the porter from declaring more CPU specific variables.
497 */
498
499/* XXX: if needed, put more variables here */
500
501/*
502 *  The size of the floating point context area.  On some CPUs this
503 *  will not be a "sizeof" because the format of the floating point
504 *  area is not defined -- only the size is.  This is usually on
505 *  CPUs with a "floating point save context" instruction.
506 */
507
508#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
509
510/*
511 * The size of a frame on the stack
512 */
513
514#if defined(hppa1_1)
515#define CPU_FRAME_SIZE  (32 * 4)
516#elif defined(sparc)
517#define CPU_FRAME_SIZE  (112)   /* based on disassembled test code */
518#else
519#error "Unknown CPU!!!"
520#endif
521
522/*
523 *  Amount of extra stack (above minimum stack size) required by
524 *  system initialization thread.  Remember that in a multiprocessor
525 *  system the system intialization thread becomes the MP server thread.
526 */
527
528#define CPU_SYSTEM_INITIALIZATION_THREAD_EXTRA_STACK 0
529
530/*
531 *  This defines the number of entries in the ISR_Vector_table managed
532 *  by RTEMS.
533 */
534
535#define CPU_INTERRUPT_NUMBER_OF_VECTORS  64
536
537/*
538 *  Should be large enough to run all RTEMS tests.  This insures
539 *  that a "reasonable" small application should not have any problems.
540 */
541
542#define CPU_STACK_MINIMUM_SIZE          (16 * 1024)
543
544/*
545 *  CPU's worst alignment requirement for data types on a byte boundary.  This
546 *  alignment does not take into account the requirements for the stack.
547 */
548
549#define CPU_ALIGNMENT              8
550
551/*
552 *  This number corresponds to the byte alignment requirement for the
553 *  heap handler.  This alignment requirement may be stricter than that
554 *  for the data types alignment specified by CPU_ALIGNMENT.  It is
555 *  common for the heap to follow the same alignment requirement as
556 *  CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict enough for the heap,
557 *  then this should be set to CPU_ALIGNMENT.
558 *
559 *  NOTE:  This does not have to be a power of 2.  It does have to
560 *         be greater or equal to than CPU_ALIGNMENT.
561 */
562
563#define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT
564
565/*
566 *  This number corresponds to the byte alignment requirement for memory
567 *  buffers allocated by the partition manager.  This alignment requirement
568 *  may be stricter than that for the data types alignment specified by
569 *  CPU_ALIGNMENT.  It is common for the partition to follow the same
570 *  alignment requirement as CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict
571 *  enough for the partition, then this should be set to CPU_ALIGNMENT.
572 *
573 *  NOTE:  This does not have to be a power of 2.  It does have to
574 *         be greater or equal to than CPU_ALIGNMENT.
575 */
576
577#define CPU_PARTITION_ALIGNMENT    CPU_ALIGNMENT
578
579/*
580 *  This number corresponds to the byte alignment requirement for the
581 *  stack.  This alignment requirement may be stricter than that for the
582 *  data types alignment specified by CPU_ALIGNMENT.  If the CPU_ALIGNMENT
583 *  is strict enough for the stack, then this should be set to 0.
584 *
585 *  NOTE:  This must be a power of 2 either 0 or greater than CPU_ALIGNMENT.
586 */
587
588#define CPU_STACK_ALIGNMENT        64
589
590/* ISR handler macros */
591
592/*
593 *  Disable all interrupts for an RTEMS critical section.  The previous
594 *  level is returned in _level.
595 */
596
597extern unsigned32 _CPU_ISR_Disable_support(void);
598
599#define _CPU_ISR_Disable( _level ) \
600    do { \
601      (_level) = _CPU_ISR_Disable_support(); \
602    } while ( 0 )
603
604/*
605 *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
606 *  This indicates the end of an RTEMS critical section.  The parameter
607 *  _level is not modified.
608 */
609
610void _CPU_ISR_Enable(unsigned32 level);
611
612/*
613 *  This temporarily restores the interrupt to _level before immediately
614 *  disabling them again.  This is used to divide long RTEMS critical
615 *  sections into two or more parts.  The parameter _level is not
616 * modified.
617 */
618
619#define _CPU_ISR_Flash( _level ) \
620  do { \
621      register _ignored = 0; \
622      _CPU_ISR_Enable( (_level) ); \
623      _CPU_ISR_Disable( _ignored ); \
624  } while ( 0 )
625
626/*
627 *  Map interrupt level in task mode onto the hardware that the CPU
628 *  actually provides.  Currently, interrupt levels which do not
629 *  map onto the CPU in a generic fashion are undefined.  Someday,
630 *  it would be nice if these were "mapped" by the application
631 *  via a callout.  For example, m68k has 8 levels 0 - 7, levels
632 *  8 - 255 would be available for bsp/application specific meaning.
633 *  This could be used to manage a programmable interrupt controller
634 *  via the rtems_task_mode directive.
635 */
636
637#define _CPU_ISR_Set_level( new_level ) \
638  { \
639    if ( new_level == 0 ) _CPU_ISR_Enable( 0 ); \
640    else                  _CPU_ISR_Enable( 1 ); \
641  }
642
643/* end of ISR handler macros */
644
645/* Context handler macros */
646
647/*
648 *  This routine is responsible for somehow restarting the currently
649 *  executing task.  If you are lucky, then all that is necessary
650 *  is restoring the context.  Otherwise, there will need to be
651 *  a special assembly routine which does something special in this
652 *  case.  Context_Restore should work most of the time.  It will
653 *  not work if restarting self conflicts with the stack frame
654 *  assumptions of restoring a context.
655 */
656
657#define _CPU_Context_Restart_self( _the_context ) \
658   _CPU_Context_restore( (_the_context) );
659
660/*
661 *  The purpose of this macro is to allow the initial pointer into
662 *  a floating point context area (used to save the floating point
663 *  context) to be at an arbitrary place in the floating point
664 *  context area.
665 *
666 *  This is necessary because some FP units are designed to have
667 *  their context saved as a stack which grows into lower addresses.
668 *  Other FP units can be saved by simply moving registers into offsets
669 *  from the base of the context area.  Finally some FP units provide
670 *  a "dump context" instruction which could fill in from high to low
671 *  or low to high based on the whim of the CPU designers.
672 */
673
674#define _CPU_Context_Fp_start( _base, _offset ) \
675   ( (void *) (_base) + (_offset) )
676
677/*
678 *  This routine initializes the FP context area passed to it to.
679 *  There are a few standard ways in which to initialize the
680 *  floating point context.  The code included for this macro assumes
681 *  that this is a CPU in which a "initial" FP context was saved into
682 *  _CPU_Null_fp_context and it simply copies it to the destination
683 *  context passed to it.
684 *
685 *  Other models include (1) not doing anything, and (2) putting
686 *  a "null FP status word" in the correct place in the FP context.
687 */
688
689#define _CPU_Context_Initialize_fp( _destination ) \
690  { \
691   *((Context_Control_fp *) *((void **) _destination)) = _CPU_Null_fp_context; \
692  }
693
694#define _CPU_Context_save_fp( _fp_context ) \
695    _CPU_Save_float_context( *(Context_Control_fp **)(_fp_context))
696
697#define _CPU_Context_restore_fp( _fp_context ) \
698    _CPU_Restore_float_context( *(Context_Control_fp **)(_fp_context))
699
700extern void _CPU_Context_Initialize(
701  Context_Control  *_the_context,
702  unsigned32       *_stack_base,
703  unsigned32        _size,
704  unsigned32        _new_level,
705  void             *_entry_point
706);
707
708/* end of Context handler macros */
709
710/* Fatal Error manager macros */
711
712/*
713 *  This routine copies _error into a known place -- typically a stack
714 *  location or a register, optionally disables interrupts, and
715 *  halts/stops the CPU.
716 */
717
718#define _CPU_Fatal_halt( _error ) \
719    _CPU_Fatal_error( _error )
720
721/* end of Fatal Error manager macros */
722
723/* Bitfield handler macros */
724
725/*
726 *  This routine sets _output to the bit number of the first bit
727 *  set in _value.  _value is of CPU dependent type Priority_Bit_map_control.
728 *  This type may be either 16 or 32 bits wide although only the 16
729 *  least significant bits will be used.
730 *
731 *  There are a number of variables in using a "find first bit" type
732 *  instruction.
733 *
734 *    (1) What happens when run on a value of zero?
735 *    (2) Bits may be numbered from MSB to LSB or vice-versa.
736 *    (3) The numbering may be zero or one based.
737 *    (4) The "find first bit" instruction may search from MSB or LSB.
738 *
739 *  RTEMS guarantees that (1) will never happen so it is not a concern.
740 *  (2),(3), (4) are handled by the macros _CPU_Priority_mask() and
741 *  _CPU_Priority_Bits_index().  These three form a set of routines
742 *  which must logically operate together.  Bits in the _value are
743 *  set and cleared based on masks built by _CPU_Priority_mask().
744 *  The basic major and minor values calculated by _Priority_Major()
745 *  and _Priority_Minor() are "massaged" by _CPU_Priority_Bits_index()
746 *  to properly range between the values returned by the "find first bit"
747 *  instruction.  This makes it possible for _Priority_Get_highest() to
748 *  calculate the major and directly index into the minor table.
749 *  This mapping is necessary to ensure that 0 (a high priority major/minor)
750 *  is the first bit found.
751 *
752 *  This entire "find first bit" and mapping process depends heavily
753 *  on the manner in which a priority is broken into a major and minor
754 *  components with the major being the 4 MSB of a priority and minor
755 *  the 4 LSB.  Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
756 *  priority.  And (15 << 4) + 14 corresponds to priority 254 -- the next
757 *  to the lowest priority.
758 *
759 *  If your CPU does not have a "find first bit" instruction, then
760 *  there are ways to make do without it.  Here are a handful of ways
761 *  to implement this in software:
762 *
763 *    - a series of 16 bit test instructions
764 *    - a "binary search using if's"
765 *    - _number = 0
766 *      if _value > 0x00ff
767 *        _value >>=8
768 *        _number = 8;
769 *
770 *      if _value > 0x0000f
771 *        _value >=8
772 *        _number += 4
773 *
774 *      _number += bit_set_table[ _value ]
775 *
776 *    where bit_set_table[ 16 ] has values which indicate the first
777 *      bit set
778 */
779
780#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
781    _output = _CPU_ffs( _value )
782
783/* end of Bitfield handler macros */
784
785/*
786 *  This routine builds the mask which corresponds to the bit fields
787 *  as searched by _CPU_Bitfield_Find_first_bit().  See the discussion
788 *  for that routine.
789 */
790
791#define _CPU_Priority_Mask( _bit_number ) \
792  ( 1 << (_bit_number) )
793
794/*
795 *  This routine translates the bit numbers returned by
796 *  _CPU_Bitfield_Find_first_bit() into something suitable for use as
797 *  a major or minor component of a priority.  See the discussion
798 *  for that routine.
799 */
800
801#define _CPU_Priority_Bits_index( _priority ) \
802  (_priority)
803
804/* end of Priority handler macros */
805
806/* functions */
807
808/*
809 *  _CPU_Initialize
810 *
811 *  This routine performs CPU dependent initialization.
812 */
813
814void _CPU_Initialize(
815  rtems_cpu_table  *cpu_table,
816  void      (*thread_dispatch)
817);
818
819/*
820 *  _CPU_ISR_install_raw_handler
821 *
822 *  This routine installs a "raw" interrupt handler directly into the
823 *  processor's vector table.
824 */
825 
826void _CPU_ISR_install_raw_handler(
827  unsigned32  vector,
828  proc_ptr    new_handler,
829  proc_ptr   *old_handler
830);
831
832/*
833 *  _CPU_ISR_install_vector
834 *
835 *  This routine installs an interrupt vector.
836 */
837
838void _CPU_ISR_install_vector(
839  unsigned32  vector,
840  proc_ptr    new_handler,
841  proc_ptr   *old_handler
842);
843
844/*
845 *  _CPU_Install_interrupt_stack
846 *
847 *  This routine installs the hardware interrupt stack pointer.
848 *
849 *  NOTE:  It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK
850 *         is TRUE.
851 */
852
853void _CPU_Install_interrupt_stack( void );
854
855/*
856 *  _CPU_Internal_threads_Idle_thread_body
857 *
858 *  This routine is the CPU dependent IDLE thread body.
859 *
860 *  NOTE:  It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY
861 *         is TRUE.
862 */
863
864void _CPU_Internal_threads_Idle_thread_body( void );
865
866/*
867 *  _CPU_Context_switch
868 *
869 *  This routine switches from the run context to the heir context.
870 */
871
872void _CPU_Context_switch(
873  Context_Control  *run,
874  Context_Control  *heir
875);
876
877/*
878 *  _CPU_Context_restore
879 *
880 *  This routine is generallu used only to restart self in an
881 *  efficient manner.  It may simply be a label in _CPU_Context_switch.
882 *
883 *  NOTE: May be unnecessary to reload some registers.
884 */
885
886void _CPU_Context_restore(
887  Context_Control *new_context
888);
889
890/*
891 *  _CPU_Save_float_context
892 *
893 *  This routine saves the floating point context passed to it.
894 */
895
896void _CPU_Save_float_context(
897  Context_Control_fp *fp_context_ptr
898);
899
900/*
901 *  _CPU_Restore_float_context
902 *
903 *  This routine restores the floating point context passed to it.
904 */
905
906void _CPU_Restore_float_context(
907  Context_Control_fp *fp_context_ptr
908);
909
910
911void _CPU_ISR_Set_signal_level(
912  unsigned32 level
913);
914
915void _CPU_Fatal_error(
916  unsigned32 _error
917);
918
919int _CPU_ffs(
920  unsigned32 _value
921);
922
923/*  The following routine swaps the endian format of an unsigned int.
924 *  It must be static because it is referenced indirectly.
925 *
926 *  This version will work on any processor, but if there is a better
927 *  way for your CPU PLEASE use it.  The most common way to do this is to:
928 *
929 *     swap least significant two bytes with 16-bit rotate
930 *     swap upper and lower 16-bits
931 *     swap most significant two bytes with 16-bit rotate
932 *
933 *  Some CPUs have special instructions which swap a 32-bit quantity in
934 *  a single instruction (e.g. i486).  It is probably best to avoid
935 *  an "endian swapping control bit" in the CPU.  One good reason is
936 *  that interrupts would probably have to be disabled to insure that
937 *  an interrupt does not try to access the same "chunk" with the wrong
938 *  endian.  Another good reason is that on some CPUs, the endian bit
939 *  endianness for ALL fetches -- both code and data -- so the code
940 *  will be fetched incorrectly.
941 */
942 
943static inline unsigned int CPU_swap_u32(
944  unsigned int value
945)
946{
947  unsigned32 byte1, byte2, byte3, byte4, swapped;
948 
949  byte4 = (value >> 24) & 0xff;
950  byte3 = (value >> 16) & 0xff;
951  byte2 = (value >> 8)  & 0xff;
952  byte1 =  value        & 0xff;
953 
954  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
955  return( swapped );
956}
957
958#ifdef __cplusplus
959}
960#endif
961
962#endif
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