source: rtems/c/src/exec/score/cpu/unix/cpu.h @ 3b170f5

4.104.114.84.95
Last change on this file since 3b170f5 was 3b170f5, checked in by Joel Sherrill <joel.sherrill@…>, on Jul 20, 1995 at 1:20:18 PM

removed junk field in context_control

  • Property mode set to 100644
File size: 30.0 KB
Line 
1/*  cpu.h
2 *
3 *  This include file contains information pertaining to the HP
4 *  PA-RISC processor (Level 1.1).
5 *
6 *  COPYRIGHT (c) 1994 by Division Incorporated
7 *
8 *  To anyone who acknowledges that this file is provided "AS IS"
9 *  without any express or implied warranty:
10 *      permission to use, copy, modify, and distribute this file
11 *      for any purpose is hereby granted without fee, provided that
12 *      the above copyright notice and this notice appears in all
13 *      copies, and that the name of Division Incorporated not be
14 *      used in advertising or publicity pertaining to distribution
15 *      of the software without specific, written prior permission.
16 *      Division Incorporated makes no representations about the
17 *      suitability of this software for any purpose.
18 *
19 *  $Id$
20 */
21
22#ifndef __CPU_h
23#define __CPU_h
24
25#ifdef __cplusplus
26extern "C" {
27#endif
28
29#include <rtems/unix.h>
30#ifndef ASM
31#include <rtems/unixtypes.h>
32#endif
33
34#if defined(solaris2)
35#undef  _POSIX_C_SOURCE
36#define _POSIX_C_SOURCE 3
37#undef  __STRICT_ANSI__
38#define __STRICT_ANSI__
39#endif
40
41#if defined(linux)
42#define MALLOC_0_RETURNS_NULL
43#endif
44
45#if 0
46
47/*
48 *  In order to get the types and prototypes used in this file under
49 *  Solaris 2.3, it is necessary to pull the following magic.
50 */
51
52#if defined(solaris2)
53#warning "Ignore the undefining __STDC__ warning"
54#undef __STDC__
55#define __STDC__ 0
56#undef  _POSIX_C_SOURCE
57#endif
58
59#endif
60
61#include <setjmp.h>
62#include <signal.h>
63
64/* conditional compilation parameters */
65
66/*
67 *  Should the calls to _Thread_Enable_dispatch be inlined?
68 *
69 *  If TRUE, then they are inlined.
70 *  If FALSE, then a subroutine call is made.
71 *
72 *  Basically this is an example of the classic trade-off of size
73 *  versus speed.  Inlining the call (TRUE) typically increases the
74 *  size of RTEMS while speeding up the enabling of dispatching.
75 *  [NOTE: In general, the _Thread_Dispatch_disable_level will
76 *  only be 0 or 1 unless you are in an interrupt handler and that
77 *  interrupt handler invokes the executive.]  When not inlined
78 *  something calls _Thread_Enable_dispatch which in turns calls
79 *  _Thread_Dispatch.  If the enable dispatch is inlined, then
80 *  one subroutine call is avoided entirely.]
81 */
82
83#define CPU_INLINE_ENABLE_DISPATCH       FALSE
84
85/*
86 *  Should the body of the search loops in _Thread_queue_Enqueue_priority
87 *  be unrolled one time?  In unrolled each iteration of the loop examines
88 *  two "nodes" on the chain being searched.  Otherwise, only one node
89 *  is examined per iteration.
90 *
91 *  If TRUE, then the loops are unrolled.
92 *  If FALSE, then the loops are not unrolled.
93 *
94 *  The primary factor in making this decision is the cost of disabling
95 *  and enabling interrupts (_ISR_Flash) versus the cost of rest of the
96 *  body of the loop.  On some CPUs, the flash is more expensive than
97 *  one iteration of the loop body.  In this case, it might be desirable
98 *  to unroll the loop.  It is important to note that on some CPUs, this
99 *  code is the longest interrupt disable period in RTEMS.  So it is
100 *  necessary to strike a balance when setting this parameter.
101 */
102
103#define CPU_UNROLL_ENQUEUE_PRIORITY      TRUE
104
105/*
106 *  Does RTEMS manage a dedicated interrupt stack in software?
107 *
108 *  If TRUE, then a stack is allocated in _Interrupt_Manager_initialization.
109 *  If FALSE, nothing is done.
110 *
111 *  If the CPU supports a dedicated interrupt stack in hardware,
112 *  then it is generally the responsibility of the BSP to allocate it
113 *  and set it up.
114 *
115 *  If the CPU does not support a dedicated interrupt stack, then
116 *  the porter has two options: (1) execute interrupts on the
117 *  stack of the interrupted task, and (2) have RTEMS manage a dedicated
118 *  interrupt stack.
119 *
120 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
121 *
122 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
123 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
124 *  possible that both are FALSE for a particular CPU.  Although it
125 *  is unclear what that would imply about the interrupt processing
126 *  procedure on that CPU.
127 */
128
129#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE
130
131/*
132 *  Does this CPU have hardware support for a dedicated interrupt stack?
133 *
134 *  If TRUE, then it must be installed during initialization.
135 *  If FALSE, then no installation is performed.
136 *
137 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
138 *
139 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
140 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
141 *  possible that both are FALSE for a particular CPU.  Although it
142 *  is unclear what that would imply about the interrupt processing
143 *  procedure on that CPU.
144 */
145
146#define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE
147
148/*
149 *  Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
150 *
151 *  If TRUE, then the memory is allocated during initialization.
152 *  If FALSE, then the memory is allocated during initialization.
153 *
154 *  This should be TRUE if CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE
155 *  or CPU_INSTALL_HARDWARE_INTERRUPT_STACK is TRUE.
156 */
157
158#define CPU_ALLOCATE_INTERRUPT_STACK FALSE
159
160/*
161 *  Does the CPU have hardware floating point?
162 *
163 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
164 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
165 *
166 *  If there is a FP coprocessor such as the i387 or mc68881, then
167 *  the answer is TRUE.
168 *
169 *  The macro name "NO_CPU_HAS_FPU" should be made CPU specific.
170 *  It indicates whether or not this CPU model has FP support.  For
171 *  example, it would be possible to have an i386_nofp CPU model
172 *  which set this to false to indicate that you have an i386 without
173 *  an i387 and wish to leave floating point support out of RTEMS.
174 */
175
176#define CPU_HARDWARE_FP     TRUE
177
178/*
179 *  Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
180 *
181 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
182 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
183 *
184 *  So far, the only CPU in which this option has been used is the
185 *  HP PA-RISC.  The HP C compiler and gcc both implicitly use the
186 *  floating point registers to perform integer multiplies.  If
187 *  a function which you would not think utilize the FP unit DOES,
188 *  then one can not easily predict which tasks will use the FP hardware.
189 *  In this case, this option should be TRUE.
190 *
191 *  If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
192 */
193
194#define CPU_ALL_TASKS_ARE_FP     FALSE
195
196/*
197 *  Should the IDLE task have a floating point context?
198 *
199 *  If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
200 *  and it has a floating point context which is switched in and out.
201 *  If FALSE, then the IDLE task does not have a floating point context.
202 *
203 *  Setting this to TRUE negatively impacts the time required to preempt
204 *  the IDLE task from an interrupt because the floating point context
205 *  must be saved as part of the preemption.
206 */
207
208#define CPU_IDLE_TASK_IS_FP      FALSE
209
210/*
211 *  Should the saving of the floating point registers be deferred
212 *  until a context switch is made to another different floating point
213 *  task?
214 *
215 *  If TRUE, then the floating point context will not be stored until
216 *  necessary.  It will remain in the floating point registers and not
217 *  disturned until another floating point task is switched to.
218 *
219 *  If FALSE, then the floating point context is saved when a floating
220 *  point task is switched out and restored when the next floating point
221 *  task is restored.  The state of the floating point registers between
222 *  those two operations is not specified.
223 *
224 *  If the floating point context does NOT have to be saved as part of
225 *  interrupt dispatching, then it should be safe to set this to TRUE.
226 *
227 *  Setting this flag to TRUE results in using a different algorithm
228 *  for deciding when to save and restore the floating point context.
229 *  The deferred FP switch algorithm minimizes the number of times
230 *  the FP context is saved and restored.  The FP context is not saved
231 *  until a context switch is made to another, different FP task.
232 *  Thus in a system with only one FP task, the FP context will never
233 *  be saved or restored.
234 */
235
236#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
237
238/*
239 *  Does this port provide a CPU dependent IDLE task implementation?
240 *
241 *  If TRUE, then the routine _CPU_Internal_threads_Idle_thread_body
242 *  must be provided and is the default IDLE thread body instead of
243 *  _Internal_threads_Idle_thread_body.
244 *
245 *  If FALSE, then use the generic IDLE thread body if the BSP does
246 *  not provide one.
247 *
248 *  This is intended to allow for supporting processors which have
249 *  a low power or idle mode.  When the IDLE thread is executed, then
250 *  the CPU can be powered down.
251 *
252 *  The order of precedence for selecting the IDLE thread body is:
253 *
254 *    1.  BSP provided
255 *    2.  CPU dependent (if provided)
256 *    3.  generic (if no BSP and no CPU dependent)
257 */
258
259#define CPU_PROVIDES_IDLE_THREAD_BODY    TRUE
260
261/*
262 *  Does the stack grow up (toward higher addresses) or down
263 *  (toward lower addresses)?
264 *
265 *  If TRUE, then the grows upward.
266 *  If FALSE, then the grows toward smaller addresses.
267 */
268
269#if defined(hppa1_1)
270#define CPU_STACK_GROWS_UP               TRUE
271#elif defined(sparc) || defined(i386)
272#define CPU_STACK_GROWS_UP               FALSE
273#else
274#error "unknown CPU!!"
275#endif
276
277
278/*
279 *  The following is the variable attribute used to force alignment
280 *  of critical RTEMS structures.  On some processors it may make
281 *  sense to have these aligned on tighter boundaries than
282 *  the minimum requirements of the compiler in order to have as
283 *  much of the critical data area as possible in a cache line.
284 *
285 *  The placement of this macro in the declaration of the variables
286 *  is based on the syntactically requirements of the GNU C
287 *  "__attribute__" extension.  For example with GNU C, use
288 *  the following to force a structures to a 32 byte boundary.
289 *
290 *      __attribute__ ((aligned (32)))
291 *
292 *  NOTE:  Currently only the Priority Bit Map table uses this feature.
293 *         To benefit from using this, the data must be heavily
294 *         used so it will stay in the cache and used frequently enough
295 *         in the executive to justify turning this on.
296 */
297
298#define CPU_STRUCTURE_ALIGNMENT          __attribute__ ((aligned (32)))
299
300/*
301 *  The following defines the number of bits actually used in the
302 *  interrupt field of the task mode.  How those bits map to the
303 *  CPU interrupt levels is defined by the routine _CPU_ISR_Set_level().
304 */
305
306#define CPU_MODES_INTERRUPT_MASK   0x00000001
307
308#define CPU_NAME "UNIX"
309
310/*
311 *  Processor defined structures
312 *
313 *  Examples structures include the descriptor tables from the i386
314 *  and the processor control structure on the i960ca.
315 */
316
317/* may need to put some structures here.  */
318
319#if defined(hppa1_1)
320/*
321 * Word indices within a jmp_buf structure
322 */
323
324#ifdef RTEMS_NEWLIB
325#define RP_OFF       6
326#define SP_OFF       2
327#define R3_OFF      10
328#define R4_OFF      11
329#define R5_OFF      12
330#define R6_OFF      13
331#define R7_OFF      14
332#define R8_OFF      15
333#define R9_OFF      16
334#define R10_OFF     17
335#define R11_OFF     18
336#define R12_OFF     19
337#define R13_OFF     20
338#define R14_OFF     21
339#define R15_OFF     22
340#define R16_OFF     23
341#define R17_OFF     24
342#define R18_OFF     25
343#define DP_OFF      26
344#endif
345
346#ifdef RTEMS_UNIXLIB
347#define RP_OFF       0
348#define SP_OFF       1
349#define R3_OFF       4
350#define R4_OFF       5
351#define R5_OFF       6
352#define R6_OFF       7
353#define R7_OFF       8
354#define R8_OFF       9
355#define R9_OFF      10
356#define R10_OFF     11
357#define R11_OFF     12
358#define R12_OFF     13
359#define R13_OFF     14
360#define R14_OFF     15
361#define R15_OFF     16
362#define R16_OFF     17
363#define R17_OFF     18
364#define R18_OFF     19
365#define DP_OFF      20
366#endif
367#endif
368
369#if defined(i386)
370 
371#ifdef RTEMS_NEWLIB
372#error "Newlib not installed"
373#endif
374 
375/*
376 *  For Linux 1.1
377 */
378 
379#ifdef RTEMS_UNIXLIB
380#define EBX_OFF    0
381#define ESI_OFF    1
382#define EDI_OFF    2
383#define EBP_OFF    3
384#define ESP_OFF    4
385#define RET_OFF    5
386#endif
387 
388#endif
389 
390#if defined(sparc)
391
392/*
393 *  Word indices within a jmp_buf structure
394 */
395 
396#ifdef RTEMS_NEWLIB
397#define ADDR_ADJ_OFFSET -8
398#define SP_OFF    0
399#define RP_OFF    1
400#define FP_OFF    2
401#endif
402
403#ifdef RTEMS_UNIXLIB
404#define ADDR_ADJ_OFFSET 0
405#define G0_OFF    0
406#define SP_OFF    1
407#define RP_OFF    2   
408#define FP_OFF    3
409#define I7_OFF    4
410#endif
411
412#endif
413
414/*
415 * Contexts
416 *
417 *  Generally there are 2 types of context to save.
418 *     1. Interrupt registers to save
419 *     2. Task level registers to save
420 *
421 *  This means we have the following 3 context items:
422 *     1. task level context stuff::  Context_Control
423 *     2. floating point task stuff:: Context_Control_fp
424 *     3. special interrupt level context :: Context_Control_interrupt
425 *
426 *  On some processors, it is cost-effective to save only the callee
427 *  preserved registers during a task context switch.  This means
428 *  that the ISR code needs to save those registers which do not
429 *  persist across function calls.  It is not mandatory to make this
430 *  distinctions between the caller/callee saves registers for the
431 *  purpose of minimizing context saved during task switch and on interrupts.
432 *  If the cost of saving extra registers is minimal, simplicity is the
433 *  choice.  Save the same context on interrupt entry as for tasks in
434 *  this case.
435 *
436 *  Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
437 *  care should be used in designing the context area.
438 *
439 *  On some CPUs with hardware floating point support, the Context_Control_fp
440 *  structure will not be used or it simply consist of an array of a
441 *  fixed number of bytes.   This is done when the floating point context
442 *  is dumped by a "FP save context" type instruction and the format
443 *  is not really defined by the CPU.  In this case, there is no need
444 *  to figure out the exact format -- only the size.  Of course, although
445 *  this is enough information for RTEMS, it is probably not enough for
446 *  a debugger such as gdb.  But that is another problem.
447 */
448
449typedef struct {
450  jmp_buf   regs;
451  sigset_t  isr_level;
452} Context_Control;
453
454typedef struct {
455} Context_Control_fp;
456
457typedef struct {
458} CPU_Interrupt_frame;
459
460
461/*
462 *  The following table contains the information required to configure
463 *  the XXX processor specific parameters.
464 *
465 *  NOTE: The interrupt_stack_size field is required if
466 *        CPU_ALLOCATE_INTERRUPT_STACK is defined as TRUE.
467 *
468 *        The pretasking_hook, predriver_hook, and postdriver_hook,
469 *        and the do_zero_of_workspace fields are required on ALL CPUs.
470 */
471
472typedef struct {
473  void       (*pretasking_hook)( void );
474  void       (*predriver_hook)( void );
475  void       (*postdriver_hook)( void );
476  void       (*idle_task)( void );
477  boolean      do_zero_of_workspace;
478  unsigned32   interrupt_stack_size;
479  unsigned32   extra_system_initialization_stack;
480}   rtems_cpu_table;
481
482/*
483 *  This variable is optional.  It is used on CPUs on which it is difficult
484 *  to generate an "uninitialized" FP context.  It is filled in by
485 *  _CPU_Initialize and copied into the task's FP context area during
486 *  _CPU_Context_Initialize.
487 */
488
489EXTERN Context_Control_fp  _CPU_Null_fp_context;
490
491/*
492 *  On some CPUs, RTEMS supports a software managed interrupt stack.
493 *  This stack is allocated by the Interrupt Manager and the switch
494 *  is performed in _ISR_Handler.  These variables contain pointers
495 *  to the lowest and highest addresses in the chunk of memory allocated
496 *  for the interrupt stack.  Since it is unknown whether the stack
497 *  grows up or down (in general), this give the CPU dependent
498 *  code the option of picking the version it wants to use.
499 *
500 *  NOTE: These two variables are required if the macro
501 *        CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
502 */
503
504EXTERN void               *_CPU_Interrupt_stack_low;
505EXTERN void               *_CPU_Interrupt_stack_high;
506
507/*
508 *  With some compilation systems, it is difficult if not impossible to
509 *  call a high-level language routine from assembly language.  This
510 *  is especially true of commercial Ada compilers and name mangling
511 *  C++ ones.  This variable can be optionally defined by the CPU porter
512 *  and contains the address of the routine _Thread_Dispatch.  This
513 *  can make it easier to invoke that routine at the end of the interrupt
514 *  sequence (if a dispatch is necessary).
515 */
516
517EXTERN void           (*_CPU_Thread_dispatch_pointer)();
518
519/*
520 *  Nothing prevents the porter from declaring more CPU specific variables.
521 */
522
523/* XXX: if needed, put more variables here */
524
525/*
526 *  The size of the floating point context area.  On some CPUs this
527 *  will not be a "sizeof" because the format of the floating point
528 *  area is not defined -- only the size is.  This is usually on
529 *  CPUs with a "floating point save context" instruction.
530 */
531
532#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
533
534/*
535 * The size of a frame on the stack
536 */
537
538#if defined(hppa1_1)
539#define CPU_FRAME_SIZE  (32 * 4)
540#elif defined(sparc)
541#define CPU_FRAME_SIZE  (112)   /* based on disassembled test code */
542#elif defined(i386)
543#define CPU_FRAME_SIZE  (24)  /* return address, sp, and bp pushed plus fudge */
544#else
545#error "Unknown CPU!!!"
546#endif
547
548/*
549 *  Amount of extra stack (above minimum stack size) required by
550 *  system initialization thread.  Remember that in a multiprocessor
551 *  system the system intialization thread becomes the MP server thread.
552 */
553
554#define CPU_SYSTEM_INITIALIZATION_THREAD_EXTRA_STACK 0
555
556/*
557 *  This defines the number of entries in the ISR_Vector_table managed
558 *  by RTEMS.
559 */
560
561#define CPU_INTERRUPT_NUMBER_OF_VECTORS  64
562
563/*
564 *  Should be large enough to run all RTEMS tests.  This insures
565 *  that a "reasonable" small application should not have any problems.
566 */
567
568#define CPU_STACK_MINIMUM_SIZE          (16 * 1024)
569
570/*
571 *  CPU's worst alignment requirement for data types on a byte boundary.  This
572 *  alignment does not take into account the requirements for the stack.
573 */
574
575#define CPU_ALIGNMENT              8
576
577/*
578 *  This number corresponds to the byte alignment requirement for the
579 *  heap handler.  This alignment requirement may be stricter than that
580 *  for the data types alignment specified by CPU_ALIGNMENT.  It is
581 *  common for the heap to follow the same alignment requirement as
582 *  CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict enough for the heap,
583 *  then this should be set to CPU_ALIGNMENT.
584 *
585 *  NOTE:  This does not have to be a power of 2.  It does have to
586 *         be greater or equal to than CPU_ALIGNMENT.
587 */
588
589#define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT
590
591/*
592 *  This number corresponds to the byte alignment requirement for memory
593 *  buffers allocated by the partition manager.  This alignment requirement
594 *  may be stricter than that for the data types alignment specified by
595 *  CPU_ALIGNMENT.  It is common for the partition to follow the same
596 *  alignment requirement as CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict
597 *  enough for the partition, then this should be set to CPU_ALIGNMENT.
598 *
599 *  NOTE:  This does not have to be a power of 2.  It does have to
600 *         be greater or equal to than CPU_ALIGNMENT.
601 */
602
603#define CPU_PARTITION_ALIGNMENT    CPU_ALIGNMENT
604
605/*
606 *  This number corresponds to the byte alignment requirement for the
607 *  stack.  This alignment requirement may be stricter than that for the
608 *  data types alignment specified by CPU_ALIGNMENT.  If the CPU_ALIGNMENT
609 *  is strict enough for the stack, then this should be set to 0.
610 *
611 *  NOTE:  This must be a power of 2 either 0 or greater than CPU_ALIGNMENT.
612 */
613
614#define CPU_STACK_ALIGNMENT        64
615
616/* ISR handler macros */
617
618/*
619 *  Disable all interrupts for an RTEMS critical section.  The previous
620 *  level is returned in _level.
621 */
622
623extern unsigned32 _CPU_ISR_Disable_support(void);
624
625#define _CPU_ISR_Disable( _level ) \
626    do { \
627      (_level) = _CPU_ISR_Disable_support(); \
628    } while ( 0 )
629
630/*
631 *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
632 *  This indicates the end of an RTEMS critical section.  The parameter
633 *  _level is not modified.
634 */
635
636void _CPU_ISR_Enable(unsigned32 level);
637
638/*
639 *  This temporarily restores the interrupt to _level before immediately
640 *  disabling them again.  This is used to divide long RTEMS critical
641 *  sections into two or more parts.  The parameter _level is not
642 * modified.
643 */
644
645#define _CPU_ISR_Flash( _level ) \
646  do { \
647      register _ignored = 0; \
648      _CPU_ISR_Enable( (_level) ); \
649      _CPU_ISR_Disable( _ignored ); \
650  } while ( 0 )
651
652/*
653 *  Map interrupt level in task mode onto the hardware that the CPU
654 *  actually provides.  Currently, interrupt levels which do not
655 *  map onto the CPU in a generic fashion are undefined.  Someday,
656 *  it would be nice if these were "mapped" by the application
657 *  via a callout.  For example, m68k has 8 levels 0 - 7, levels
658 *  8 - 255 would be available for bsp/application specific meaning.
659 *  This could be used to manage a programmable interrupt controller
660 *  via the rtems_task_mode directive.
661 */
662
663#define _CPU_ISR_Set_level( new_level ) \
664  { \
665    if ( new_level == 0 ) _CPU_ISR_Enable( 0 ); \
666    else                  _CPU_ISR_Enable( 1 ); \
667  }
668
669/* end of ISR handler macros */
670
671/* Context handler macros */
672
673/*
674 *  This routine is responsible for somehow restarting the currently
675 *  executing task.  If you are lucky, then all that is necessary
676 *  is restoring the context.  Otherwise, there will need to be
677 *  a special assembly routine which does something special in this
678 *  case.  Context_Restore should work most of the time.  It will
679 *  not work if restarting self conflicts with the stack frame
680 *  assumptions of restoring a context.
681 */
682
683#define _CPU_Context_Restart_self( _the_context ) \
684   _CPU_Context_restore( (_the_context) );
685
686/*
687 *  The purpose of this macro is to allow the initial pointer into
688 *  a floating point context area (used to save the floating point
689 *  context) to be at an arbitrary place in the floating point
690 *  context area.
691 *
692 *  This is necessary because some FP units are designed to have
693 *  their context saved as a stack which grows into lower addresses.
694 *  Other FP units can be saved by simply moving registers into offsets
695 *  from the base of the context area.  Finally some FP units provide
696 *  a "dump context" instruction which could fill in from high to low
697 *  or low to high based on the whim of the CPU designers.
698 */
699
700#define _CPU_Context_Fp_start( _base, _offset ) \
701   ( (void *) (_base) + (_offset) )
702
703/*
704 *  This routine initializes the FP context area passed to it to.
705 *  There are a few standard ways in which to initialize the
706 *  floating point context.  The code included for this macro assumes
707 *  that this is a CPU in which a "initial" FP context was saved into
708 *  _CPU_Null_fp_context and it simply copies it to the destination
709 *  context passed to it.
710 *
711 *  Other models include (1) not doing anything, and (2) putting
712 *  a "null FP status word" in the correct place in the FP context.
713 */
714
715#define _CPU_Context_Initialize_fp( _destination ) \
716  { \
717   *((Context_Control_fp *) *((void **) _destination)) = _CPU_Null_fp_context; \
718  }
719
720#define _CPU_Context_save_fp( _fp_context ) \
721    _CPU_Save_float_context( *(Context_Control_fp **)(_fp_context))
722
723#define _CPU_Context_restore_fp( _fp_context ) \
724    _CPU_Restore_float_context( *(Context_Control_fp **)(_fp_context))
725
726extern void _CPU_Context_Initialize(
727  Context_Control  *_the_context,
728  unsigned32       *_stack_base,
729  unsigned32        _size,
730  unsigned32        _new_level,
731  void             *_entry_point
732);
733
734/* end of Context handler macros */
735
736/* Fatal Error manager macros */
737
738/*
739 *  This routine copies _error into a known place -- typically a stack
740 *  location or a register, optionally disables interrupts, and
741 *  halts/stops the CPU.
742 */
743
744#define _CPU_Fatal_halt( _error ) \
745    _CPU_Fatal_error( _error )
746
747/* end of Fatal Error manager macros */
748
749/* Bitfield handler macros */
750
751/*
752 *  This routine sets _output to the bit number of the first bit
753 *  set in _value.  _value is of CPU dependent type Priority_Bit_map_control.
754 *  This type may be either 16 or 32 bits wide although only the 16
755 *  least significant bits will be used.
756 *
757 *  There are a number of variables in using a "find first bit" type
758 *  instruction.
759 *
760 *    (1) What happens when run on a value of zero?
761 *    (2) Bits may be numbered from MSB to LSB or vice-versa.
762 *    (3) The numbering may be zero or one based.
763 *    (4) The "find first bit" instruction may search from MSB or LSB.
764 *
765 *  RTEMS guarantees that (1) will never happen so it is not a concern.
766 *  (2),(3), (4) are handled by the macros _CPU_Priority_mask() and
767 *  _CPU_Priority_Bits_index().  These three form a set of routines
768 *  which must logically operate together.  Bits in the _value are
769 *  set and cleared based on masks built by _CPU_Priority_mask().
770 *  The basic major and minor values calculated by _Priority_Major()
771 *  and _Priority_Minor() are "massaged" by _CPU_Priority_Bits_index()
772 *  to properly range between the values returned by the "find first bit"
773 *  instruction.  This makes it possible for _Priority_Get_highest() to
774 *  calculate the major and directly index into the minor table.
775 *  This mapping is necessary to ensure that 0 (a high priority major/minor)
776 *  is the first bit found.
777 *
778 *  This entire "find first bit" and mapping process depends heavily
779 *  on the manner in which a priority is broken into a major and minor
780 *  components with the major being the 4 MSB of a priority and minor
781 *  the 4 LSB.  Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
782 *  priority.  And (15 << 4) + 14 corresponds to priority 254 -- the next
783 *  to the lowest priority.
784 *
785 *  If your CPU does not have a "find first bit" instruction, then
786 *  there are ways to make do without it.  Here are a handful of ways
787 *  to implement this in software:
788 *
789 *    - a series of 16 bit test instructions
790 *    - a "binary search using if's"
791 *    - _number = 0
792 *      if _value > 0x00ff
793 *        _value >>=8
794 *        _number = 8;
795 *
796 *      if _value > 0x0000f
797 *        _value >=8
798 *        _number += 4
799 *
800 *      _number += bit_set_table[ _value ]
801 *
802 *    where bit_set_table[ 16 ] has values which indicate the first
803 *      bit set
804 */
805
806#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
807    _output = _CPU_ffs( _value )
808
809/* end of Bitfield handler macros */
810
811/*
812 *  This routine builds the mask which corresponds to the bit fields
813 *  as searched by _CPU_Bitfield_Find_first_bit().  See the discussion
814 *  for that routine.
815 */
816
817#define _CPU_Priority_Mask( _bit_number ) \
818  ( 1 << (_bit_number) )
819
820/*
821 *  This routine translates the bit numbers returned by
822 *  _CPU_Bitfield_Find_first_bit() into something suitable for use as
823 *  a major or minor component of a priority.  See the discussion
824 *  for that routine.
825 */
826
827#define _CPU_Priority_Bits_index( _priority ) \
828  (_priority)
829
830/* end of Priority handler macros */
831
832/* functions */
833
834/*
835 *  _CPU_Initialize
836 *
837 *  This routine performs CPU dependent initialization.
838 */
839
840void _CPU_Initialize(
841  rtems_cpu_table  *cpu_table,
842  void      (*thread_dispatch)
843);
844
845/*
846 *  _CPU_ISR_install_raw_handler
847 *
848 *  This routine installs a "raw" interrupt handler directly into the
849 *  processor's vector table.
850 */
851 
852void _CPU_ISR_install_raw_handler(
853  unsigned32  vector,
854  proc_ptr    new_handler,
855  proc_ptr   *old_handler
856);
857
858/*
859 *  _CPU_ISR_install_vector
860 *
861 *  This routine installs an interrupt vector.
862 */
863
864void _CPU_ISR_install_vector(
865  unsigned32  vector,
866  proc_ptr    new_handler,
867  proc_ptr   *old_handler
868);
869
870/*
871 *  _CPU_Install_interrupt_stack
872 *
873 *  This routine installs the hardware interrupt stack pointer.
874 *
875 *  NOTE:  It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK
876 *         is TRUE.
877 */
878
879void _CPU_Install_interrupt_stack( void );
880
881/*
882 *  _CPU_Internal_threads_Idle_thread_body
883 *
884 *  This routine is the CPU dependent IDLE thread body.
885 *
886 *  NOTE:  It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY
887 *         is TRUE.
888 */
889
890void _CPU_Internal_threads_Idle_thread_body( void );
891
892/*
893 *  _CPU_Context_switch
894 *
895 *  This routine switches from the run context to the heir context.
896 */
897
898void _CPU_Context_switch(
899  Context_Control  *run,
900  Context_Control  *heir
901);
902
903/*
904 *  _CPU_Context_restore
905 *
906 *  This routine is generallu used only to restart self in an
907 *  efficient manner.  It may simply be a label in _CPU_Context_switch.
908 *
909 *  NOTE: May be unnecessary to reload some registers.
910 */
911
912void _CPU_Context_restore(
913  Context_Control *new_context
914);
915
916/*
917 *  _CPU_Save_float_context
918 *
919 *  This routine saves the floating point context passed to it.
920 */
921
922void _CPU_Save_float_context(
923  Context_Control_fp *fp_context_ptr
924);
925
926/*
927 *  _CPU_Restore_float_context
928 *
929 *  This routine restores the floating point context passed to it.
930 */
931
932void _CPU_Restore_float_context(
933  Context_Control_fp *fp_context_ptr
934);
935
936
937void _CPU_ISR_Set_signal_level(
938  unsigned32 level
939);
940
941void _CPU_Fatal_error(
942  unsigned32 _error
943);
944
945int _CPU_ffs(
946  unsigned32 _value
947);
948
949/*  The following routine swaps the endian format of an unsigned int.
950 *  It must be static because it is referenced indirectly.
951 *
952 *  This version will work on any processor, but if there is a better
953 *  way for your CPU PLEASE use it.  The most common way to do this is to:
954 *
955 *     swap least significant two bytes with 16-bit rotate
956 *     swap upper and lower 16-bits
957 *     swap most significant two bytes with 16-bit rotate
958 *
959 *  Some CPUs have special instructions which swap a 32-bit quantity in
960 *  a single instruction (e.g. i486).  It is probably best to avoid
961 *  an "endian swapping control bit" in the CPU.  One good reason is
962 *  that interrupts would probably have to be disabled to insure that
963 *  an interrupt does not try to access the same "chunk" with the wrong
964 *  endian.  Another good reason is that on some CPUs, the endian bit
965 *  endianness for ALL fetches -- both code and data -- so the code
966 *  will be fetched incorrectly.
967 */
968 
969static inline unsigned int CPU_swap_u32(
970  unsigned int value
971)
972{
973  unsigned32 byte1, byte2, byte3, byte4, swapped;
974 
975  byte4 = (value >> 24) & 0xff;
976  byte3 = (value >> 16) & 0xff;
977  byte2 = (value >> 8)  & 0xff;
978  byte1 =  value        & 0xff;
979 
980  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
981  return( swapped );
982}
983
984#ifdef __cplusplus
985}
986#endif
987
988#endif
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