source: rtems/c/src/exec/score/cpu/unix/cpu.h @ 3aa5029

4.104.114.84.95
Last change on this file since 3aa5029 was 3aa5029, checked in by Joel Sherrill <joel.sherrill@…>, on Jan 29, 1997 at 12:14:15 AM

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1/*  cpu.h
2 *
3 *  This include file contains information pertaining to the HP
4 *  PA-RISC processor (Level 1.1).
5 *
6 *  COPYRIGHT (c) 1994 by Division Incorporated
7 *
8 *  To anyone who acknowledges that this file is provided "AS IS"
9 *  without any express or implied warranty:
10 *      permission to use, copy, modify, and distribute this file
11 *      for any purpose is hereby granted without fee, provided that
12 *      the above copyright notice and this notice appears in all
13 *      copies, and that the name of Division Incorporated not be
14 *      used in advertising or publicity pertaining to distribution
15 *      of the software without specific, written prior permission.
16 *      Division Incorporated makes no representations about the
17 *      suitability of this software for any purpose.
18 *
19 *  $Id$
20 */
21
22#ifndef __CPU_h
23#define __CPU_h
24
25#ifdef __cplusplus
26extern "C" {
27#endif
28
29#include <rtems/score/unix.h>              /* pick up machine definitions */
30#ifndef ASM
31#include <rtems/score/unixtypes.h>
32#endif
33
34#include <rtems/score/unixsize.h>
35
36#if defined(solaris2)
37#undef  _POSIX_C_SOURCE
38#define _POSIX_C_SOURCE 3
39#undef  __STRICT_ANSI__
40#define __STRICT_ANSI__
41#endif
42
43#if defined(linux)
44#define MALLOC_0_RETURNS_NULL
45#endif
46
47/* conditional compilation parameters */
48
49/*
50 *  Should the calls to _Thread_Enable_dispatch be inlined?
51 *
52 *  If TRUE, then they are inlined.
53 *  If FALSE, then a subroutine call is made.
54 *
55 *  Basically this is an example of the classic trade-off of size
56 *  versus speed.  Inlining the call (TRUE) typically increases the
57 *  size of RTEMS while speeding up the enabling of dispatching.
58 *  [NOTE: In general, the _Thread_Dispatch_disable_level will
59 *  only be 0 or 1 unless you are in an interrupt handler and that
60 *  interrupt handler invokes the executive.]  When not inlined
61 *  something calls _Thread_Enable_dispatch which in turns calls
62 *  _Thread_Dispatch.  If the enable dispatch is inlined, then
63 *  one subroutine call is avoided entirely.]
64 */
65
66#define CPU_INLINE_ENABLE_DISPATCH       FALSE
67
68/*
69 *  Should the body of the search loops in _Thread_queue_Enqueue_priority
70 *  be unrolled one time?  In unrolled each iteration of the loop examines
71 *  two "nodes" on the chain being searched.  Otherwise, only one node
72 *  is examined per iteration.
73 *
74 *  If TRUE, then the loops are unrolled.
75 *  If FALSE, then the loops are not unrolled.
76 *
77 *  The primary factor in making this decision is the cost of disabling
78 *  and enabling interrupts (_ISR_Flash) versus the cost of rest of the
79 *  body of the loop.  On some CPUs, the flash is more expensive than
80 *  one iteration of the loop body.  In this case, it might be desirable
81 *  to unroll the loop.  It is important to note that on some CPUs, this
82 *  code is the longest interrupt disable period in RTEMS.  So it is
83 *  necessary to strike a balance when setting this parameter.
84 */
85
86#define CPU_UNROLL_ENQUEUE_PRIORITY      TRUE
87
88/*
89 *  Does RTEMS manage a dedicated interrupt stack in software?
90 *
91 *  If TRUE, then a stack is allocated in _Interrupt_Manager_initialization.
92 *  If FALSE, nothing is done.
93 *
94 *  If the CPU supports a dedicated interrupt stack in hardware,
95 *  then it is generally the responsibility of the BSP to allocate it
96 *  and set it up.
97 *
98 *  If the CPU does not support a dedicated interrupt stack, then
99 *  the porter has two options: (1) execute interrupts on the
100 *  stack of the interrupted task, and (2) have RTEMS manage a dedicated
101 *  interrupt stack.
102 *
103 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
104 *
105 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
106 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
107 *  possible that both are FALSE for a particular CPU.  Although it
108 *  is unclear what that would imply about the interrupt processing
109 *  procedure on that CPU.
110 */
111
112#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE
113
114/*
115 *  Does this CPU have hardware support for a dedicated interrupt stack?
116 *
117 *  If TRUE, then it must be installed during initialization.
118 *  If FALSE, then no installation is performed.
119 *
120 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
121 *
122 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
123 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
124 *  possible that both are FALSE for a particular CPU.  Although it
125 *  is unclear what that would imply about the interrupt processing
126 *  procedure on that CPU.
127 */
128
129#define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE
130
131/*
132 *  Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
133 *
134 *  If TRUE, then the memory is allocated during initialization.
135 *  If FALSE, then the memory is allocated during initialization.
136 *
137 *  This should be TRUE if CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE
138 *  or CPU_INSTALL_HARDWARE_INTERRUPT_STACK is TRUE.
139 */
140
141#define CPU_ALLOCATE_INTERRUPT_STACK FALSE
142
143/*
144 *  Does the CPU have hardware floating point?
145 *
146 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
147 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
148 *
149 *  If there is a FP coprocessor such as the i387 or mc68881, then
150 *  the answer is TRUE.
151 *
152 *  The macro name "NO_CPU_HAS_FPU" should be made CPU specific.
153 *  It indicates whether or not this CPU model has FP support.  For
154 *  example, it would be possible to have an i386_nofp CPU model
155 *  which set this to false to indicate that you have an i386 without
156 *  an i387 and wish to leave floating point support out of RTEMS.
157 */
158
159#define CPU_HARDWARE_FP     TRUE
160
161/*
162 *  Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
163 *
164 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
165 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
166 *
167 *  So far, the only CPU in which this option has been used is the
168 *  HP PA-RISC.  The HP C compiler and gcc both implicitly use the
169 *  floating point registers to perform integer multiplies.  If
170 *  a function which you would not think utilize the FP unit DOES,
171 *  then one can not easily predict which tasks will use the FP hardware.
172 *  In this case, this option should be TRUE.
173 *
174 *  If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
175 */
176
177#define CPU_ALL_TASKS_ARE_FP     FALSE
178
179/*
180 *  Should the IDLE task have a floating point context?
181 *
182 *  If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
183 *  and it has a floating point context which is switched in and out.
184 *  If FALSE, then the IDLE task does not have a floating point context.
185 *
186 *  Setting this to TRUE negatively impacts the time required to preempt
187 *  the IDLE task from an interrupt because the floating point context
188 *  must be saved as part of the preemption.
189 */
190
191#define CPU_IDLE_TASK_IS_FP      FALSE
192
193/*
194 *  Should the saving of the floating point registers be deferred
195 *  until a context switch is made to another different floating point
196 *  task?
197 *
198 *  If TRUE, then the floating point context will not be stored until
199 *  necessary.  It will remain in the floating point registers and not
200 *  disturned until another floating point task is switched to.
201 *
202 *  If FALSE, then the floating point context is saved when a floating
203 *  point task is switched out and restored when the next floating point
204 *  task is restored.  The state of the floating point registers between
205 *  those two operations is not specified.
206 *
207 *  If the floating point context does NOT have to be saved as part of
208 *  interrupt dispatching, then it should be safe to set this to TRUE.
209 *
210 *  Setting this flag to TRUE results in using a different algorithm
211 *  for deciding when to save and restore the floating point context.
212 *  The deferred FP switch algorithm minimizes the number of times
213 *  the FP context is saved and restored.  The FP context is not saved
214 *  until a context switch is made to another, different FP task.
215 *  Thus in a system with only one FP task, the FP context will never
216 *  be saved or restored.
217 */
218
219#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
220
221/*
222 *  Does this port provide a CPU dependent IDLE task implementation?
223 *
224 *  If TRUE, then the routine _CPU_Thread_Idle_body
225 *  must be provided and is the default IDLE thread body instead of
226 *  _CPU_Thread_Idle_body.
227 *
228 *  If FALSE, then use the generic IDLE thread body if the BSP does
229 *  not provide one.
230 *
231 *  This is intended to allow for supporting processors which have
232 *  a low power or idle mode.  When the IDLE thread is executed, then
233 *  the CPU can be powered down.
234 *
235 *  The order of precedence for selecting the IDLE thread body is:
236 *
237 *    1.  BSP provided
238 *    2.  CPU dependent (if provided)
239 *    3.  generic (if no BSP and no CPU dependent)
240 */
241
242#define CPU_PROVIDES_IDLE_THREAD_BODY    TRUE
243
244/*
245 *  Does the stack grow up (toward higher addresses) or down
246 *  (toward lower addresses)?
247 *
248 *  If TRUE, then the grows upward.
249 *  If FALSE, then the grows toward smaller addresses.
250 */
251
252#if defined(hppa1_1)
253#define CPU_STACK_GROWS_UP               TRUE
254#elif defined(sparc) || defined(i386)
255#define CPU_STACK_GROWS_UP               FALSE
256#else
257#error "unknown CPU!!"
258#endif
259
260
261/*
262 *  The following is the variable attribute used to force alignment
263 *  of critical RTEMS structures.  On some processors it may make
264 *  sense to have these aligned on tighter boundaries than
265 *  the minimum requirements of the compiler in order to have as
266 *  much of the critical data area as possible in a cache line.
267 *
268 *  The placement of this macro in the declaration of the variables
269 *  is based on the syntactically requirements of the GNU C
270 *  "__attribute__" extension.  For example with GNU C, use
271 *  the following to force a structures to a 32 byte boundary.
272 *
273 *      __attribute__ ((aligned (32)))
274 *
275 *  NOTE:  Currently only the Priority Bit Map table uses this feature.
276 *         To benefit from using this, the data must be heavily
277 *         used so it will stay in the cache and used frequently enough
278 *         in the executive to justify turning this on.
279 */
280
281#ifdef __GNUC__
282#define CPU_STRUCTURE_ALIGNMENT          __attribute__ ((aligned (32)))
283#else
284#define CPU_STRUCTURE_ALIGNMENT
285#endif
286
287/*
288 *  The following defines the number of bits actually used in the
289 *  interrupt field of the task mode.  How those bits map to the
290 *  CPU interrupt levels is defined by the routine _CPU_ISR_Set_level().
291 */
292
293#define CPU_MODES_INTERRUPT_MASK   0x00000001
294
295#define CPU_NAME "UNIX"
296
297/*
298 *  Processor defined structures
299 *
300 *  Examples structures include the descriptor tables from the i386
301 *  and the processor control structure on the i960ca.
302 */
303
304/* may need to put some structures here.  */
305
306#if defined(hppa1_1)
307/*
308 * Word indices within a jmp_buf structure
309 */
310
311#ifdef RTEMS_NEWLIB_SETJMP
312#define RP_OFF       6
313#define SP_OFF       2
314#define R3_OFF      10
315#define R4_OFF      11
316#define R5_OFF      12
317#define R6_OFF      13
318#define R7_OFF      14
319#define R8_OFF      15
320#define R9_OFF      16
321#define R10_OFF     17
322#define R11_OFF     18
323#define R12_OFF     19
324#define R13_OFF     20
325#define R14_OFF     21
326#define R15_OFF     22
327#define R16_OFF     23
328#define R17_OFF     24
329#define R18_OFF     25
330#define DP_OFF      26
331#endif
332
333#ifdef RTEMS_UNIXLIB_SETJMP
334#define RP_OFF       0
335#define SP_OFF       1
336#define R3_OFF       4
337#define R4_OFF       5
338#define R5_OFF       6
339#define R6_OFF       7
340#define R7_OFF       8
341#define R8_OFF       9
342#define R9_OFF      10
343#define R10_OFF     11
344#define R11_OFF     12
345#define R12_OFF     13
346#define R13_OFF     14
347#define R14_OFF     15
348#define R15_OFF     16
349#define R16_OFF     17
350#define R17_OFF     18
351#define R18_OFF     19
352#define DP_OFF      20
353#endif
354#endif
355
356#if defined(i386)
357 
358#ifdef RTEMS_NEWLIB
359#error "Newlib not installed"
360#endif
361 
362/*
363 *  For Linux 1.1
364 */
365 
366#ifdef RTEMS_UNIXLIB
367#define EBX_OFF    0
368#define ESI_OFF    1
369#define EDI_OFF    2
370#define EBP_OFF    3
371#define ESP_OFF    4
372#define RET_OFF    5
373#endif
374 
375#endif
376 
377#if defined(sparc)
378
379/*
380 *  Word indices within a jmp_buf structure
381 */
382 
383#ifdef RTEMS_NEWLIB
384#define ADDR_ADJ_OFFSET -8
385#define SP_OFF    0
386#define RP_OFF    1
387#define FP_OFF    2
388#endif
389
390#ifdef RTEMS_UNIXLIB
391#define ADDR_ADJ_OFFSET 0
392#define G0_OFF    0
393#define SP_OFF    1
394#define RP_OFF    2   
395#define FP_OFF    3
396#define I7_OFF    4
397#endif
398
399#endif
400
401/*
402 * Contexts
403 *
404 *  Generally there are 2 types of context to save.
405 *     1. Interrupt registers to save
406 *     2. Task level registers to save
407 *
408 *  This means we have the following 3 context items:
409 *     1. task level context stuff::  Context_Control
410 *     2. floating point task stuff:: Context_Control_fp
411 *     3. special interrupt level context :: Context_Control_interrupt
412 *
413 *  On some processors, it is cost-effective to save only the callee
414 *  preserved registers during a task context switch.  This means
415 *  that the ISR code needs to save those registers which do not
416 *  persist across function calls.  It is not mandatory to make this
417 *  distinctions between the caller/callee saves registers for the
418 *  purpose of minimizing context saved during task switch and on interrupts.
419 *  If the cost of saving extra registers is minimal, simplicity is the
420 *  choice.  Save the same context on interrupt entry as for tasks in
421 *  this case.
422 *
423 *  Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
424 *  care should be used in designing the context area.
425 *
426 *  On some CPUs with hardware floating point support, the Context_Control_fp
427 *  structure will not be used or it simply consist of an array of a
428 *  fixed number of bytes.   This is done when the floating point context
429 *  is dumped by a "FP save context" type instruction and the format
430 *  is not really defined by the CPU.  In this case, there is no need
431 *  to figure out the exact format -- only the size.  Of course, although
432 *  this is enough information for RTEMS, it is probably not enough for
433 *  a debugger such as gdb.  But that is another problem.
434 */
435
436/*
437 *  This is really just the area for the following fields.
438 *
439 *    jmp_buf    regs;
440 *    unsigned32 isr_level;
441 *
442 *  Doing it this way avoids conflicts between the native stuff and the
443 *  RTEMS stuff.
444 *
445 *  NOTE:
446 *      hpux9 setjmp is optimized for the case where the setjmp buffer
447 *      is 8 byte aligned.  In a RISC world, this seems likely to enable
448 *      8 byte copies, especially for the float registers.
449 *      So we always align them on 8 byte boundaries.
450 */
451
452#ifdef __GNUC__
453#define CONTEXT_STRUCTURE_ALIGNMENT          __attribute__ ((aligned (8)))
454#else
455#define CONTEXT_STRUCTURE_ALIGNMENT
456#endif
457
458typedef struct {
459  char      Area[ CPU_CONTEXT_SIZE_IN_BYTES ] CONTEXT_STRUCTURE_ALIGNMENT;
460} Context_Control;
461
462typedef struct {
463} Context_Control_fp;
464
465typedef struct {
466} CPU_Interrupt_frame;
467
468
469/*
470 *  The following table contains the information required to configure
471 *  the UNIX Simulator specific parameters.
472 */
473
474typedef struct {
475  void       (*pretasking_hook)( void );
476  void       (*predriver_hook)( void );
477  void       (*postdriver_hook)( void );
478  void       (*idle_task)( void );
479  boolean      do_zero_of_workspace;
480  unsigned32   interrupt_stack_size;
481  unsigned32   extra_mpci_receive_server_stack;
482  void *     (*stack_allocate_hook)( unsigned32 );
483  void       (*stack_free_hook)( void* );
484  /* end of required fields */
485}   rtems_cpu_table;
486
487/*
488 *  This variable is optional.  It is used on CPUs on which it is difficult
489 *  to generate an "uninitialized" FP context.  It is filled in by
490 *  _CPU_Initialize and copied into the task's FP context area during
491 *  _CPU_Context_Initialize.
492 */
493
494SCORE_EXTERN Context_Control_fp  _CPU_Null_fp_context;
495
496/*
497 *  On some CPUs, RTEMS supports a software managed interrupt stack.
498 *  This stack is allocated by the Interrupt Manager and the switch
499 *  is performed in _ISR_Handler.  These variables contain pointers
500 *  to the lowest and highest addresses in the chunk of memory allocated
501 *  for the interrupt stack.  Since it is unknown whether the stack
502 *  grows up or down (in general), this give the CPU dependent
503 *  code the option of picking the version it wants to use.
504 *
505 *  NOTE: These two variables are required if the macro
506 *        CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
507 */
508
509SCORE_EXTERN void               *_CPU_Interrupt_stack_low;
510SCORE_EXTERN void               *_CPU_Interrupt_stack_high;
511
512/*
513 *  With some compilation systems, it is difficult if not impossible to
514 *  call a high-level language routine from assembly language.  This
515 *  is especially true of commercial Ada compilers and name mangling
516 *  C++ ones.  This variable can be optionally defined by the CPU porter
517 *  and contains the address of the routine _Thread_Dispatch.  This
518 *  can make it easier to invoke that routine at the end of the interrupt
519 *  sequence (if a dispatch is necessary).
520 */
521
522SCORE_EXTERN void           (*_CPU_Thread_dispatch_pointer)();
523
524/*
525 *  Nothing prevents the porter from declaring more CPU specific variables.
526 */
527
528/* XXX: if needed, put more variables here */
529
530/*
531 *  The size of the floating point context area.  On some CPUs this
532 *  will not be a "sizeof" because the format of the floating point
533 *  area is not defined -- only the size is.  This is usually on
534 *  CPUs with a "floating point save context" instruction.
535 */
536
537#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
538
539/*
540 * The size of a frame on the stack
541 */
542
543#if defined(hppa1_1)
544#define CPU_FRAME_SIZE  (32 * 4)
545#elif defined(sparc)
546#define CPU_FRAME_SIZE  (112)   /* based on disassembled test code */
547#elif defined(i386)
548#define CPU_FRAME_SIZE  (24)  /* return address, sp, and bp pushed plus fudge */
549#else
550#error "Unknown CPU!!!"
551#endif
552
553/*
554 *  Amount of extra stack (above minimum stack size) required by
555 *  MPCI receive server thread.  Remember that in a multiprocessor
556 *  system this thread must exist and be able to process all directives.
557 */
558
559#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
560
561/*
562 *  This defines the number of entries in the ISR_Vector_table managed
563 *  by RTEMS.
564 */
565
566#define CPU_INTERRUPT_NUMBER_OF_VECTORS      64
567#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
568
569/*
570 *  Should be large enough to run all RTEMS tests.  This insures
571 *  that a "reasonable" small application should not have any problems.
572 */
573
574#define CPU_STACK_MINIMUM_SIZE          (16 * 1024)
575
576/*
577 *  CPU's worst alignment requirement for data types on a byte boundary.  This
578 *  alignment does not take into account the requirements for the stack.
579 */
580
581#define CPU_ALIGNMENT              8
582
583/*
584 *  This number corresponds to the byte alignment requirement for the
585 *  heap handler.  This alignment requirement may be stricter than that
586 *  for the data types alignment specified by CPU_ALIGNMENT.  It is
587 *  common for the heap to follow the same alignment requirement as
588 *  CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict enough for the heap,
589 *  then this should be set to CPU_ALIGNMENT.
590 *
591 *  NOTE:  This does not have to be a power of 2.  It does have to
592 *         be greater or equal to than CPU_ALIGNMENT.
593 */
594
595#define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT
596
597/*
598 *  This number corresponds to the byte alignment requirement for memory
599 *  buffers allocated by the partition manager.  This alignment requirement
600 *  may be stricter than that for the data types alignment specified by
601 *  CPU_ALIGNMENT.  It is common for the partition to follow the same
602 *  alignment requirement as CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict
603 *  enough for the partition, then this should be set to CPU_ALIGNMENT.
604 *
605 *  NOTE:  This does not have to be a power of 2.  It does have to
606 *         be greater or equal to than CPU_ALIGNMENT.
607 */
608
609#define CPU_PARTITION_ALIGNMENT    CPU_ALIGNMENT
610
611/*
612 *  This number corresponds to the byte alignment requirement for the
613 *  stack.  This alignment requirement may be stricter than that for the
614 *  data types alignment specified by CPU_ALIGNMENT.  If the CPU_ALIGNMENT
615 *  is strict enough for the stack, then this should be set to 0.
616 *
617 *  NOTE:  This must be a power of 2 either 0 or greater than CPU_ALIGNMENT.
618 */
619
620#define CPU_STACK_ALIGNMENT        64
621
622/* ISR handler macros */
623
624/*
625 *  Disable all interrupts for an RTEMS critical section.  The previous
626 *  level is returned in _level.
627 */
628
629extern unsigned32 _CPU_ISR_Disable_support(void);
630
631#define _CPU_ISR_Disable( _level ) \
632    do { \
633      (_level) = _CPU_ISR_Disable_support(); \
634    } while ( 0 )
635
636/*
637 *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
638 *  This indicates the end of an RTEMS critical section.  The parameter
639 *  _level is not modified.
640 */
641
642void _CPU_ISR_Enable(unsigned32 level);
643
644/*
645 *  This temporarily restores the interrupt to _level before immediately
646 *  disabling them again.  This is used to divide long RTEMS critical
647 *  sections into two or more parts.  The parameter _level is not
648 * modified.
649 */
650
651#define _CPU_ISR_Flash( _level ) \
652  do { \
653      register _ignored = 0; \
654      _CPU_ISR_Enable( (_level) ); \
655      _CPU_ISR_Disable( _ignored ); \
656  } while ( 0 )
657
658/*
659 *  Map interrupt level in task mode onto the hardware that the CPU
660 *  actually provides.  Currently, interrupt levels which do not
661 *  map onto the CPU in a generic fashion are undefined.  Someday,
662 *  it would be nice if these were "mapped" by the application
663 *  via a callout.  For example, m68k has 8 levels 0 - 7, levels
664 *  8 - 255 would be available for bsp/application specific meaning.
665 *  This could be used to manage a programmable interrupt controller
666 *  via the rtems_task_mode directive.
667 */
668
669#define _CPU_ISR_Set_level( new_level ) \
670  { \
671    if ( new_level == 0 ) _CPU_ISR_Enable( 0 ); \
672    else                  _CPU_ISR_Enable( 1 ); \
673  }
674
675unsigned32 _CPU_ISR_Get_level( void );
676
677/* end of ISR handler macros */
678
679/* Context handler macros */
680
681/*
682 *  This routine is responsible for somehow restarting the currently
683 *  executing task.  If you are lucky, then all that is necessary
684 *  is restoring the context.  Otherwise, there will need to be
685 *  a special assembly routine which does something special in this
686 *  case.  Context_Restore should work most of the time.  It will
687 *  not work if restarting self conflicts with the stack frame
688 *  assumptions of restoring a context.
689 */
690
691#define _CPU_Context_Restart_self( _the_context ) \
692   _CPU_Context_restore( (_the_context) );
693
694/*
695 *  The purpose of this macro is to allow the initial pointer into
696 *  a floating point context area (used to save the floating point
697 *  context) to be at an arbitrary place in the floating point
698 *  context area.
699 *
700 *  This is necessary because some FP units are designed to have
701 *  their context saved as a stack which grows into lower addresses.
702 *  Other FP units can be saved by simply moving registers into offsets
703 *  from the base of the context area.  Finally some FP units provide
704 *  a "dump context" instruction which could fill in from high to low
705 *  or low to high based on the whim of the CPU designers.
706 */
707
708#define _CPU_Context_Fp_start( _base, _offset ) \
709   ( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
710
711/*
712 *  This routine initializes the FP context area passed to it to.
713 *  There are a few standard ways in which to initialize the
714 *  floating point context.  The code included for this macro assumes
715 *  that this is a CPU in which a "initial" FP context was saved into
716 *  _CPU_Null_fp_context and it simply copies it to the destination
717 *  context passed to it.
718 *
719 *  Other models include (1) not doing anything, and (2) putting
720 *  a "null FP status word" in the correct place in the FP context.
721 */
722
723#define _CPU_Context_Initialize_fp( _destination ) \
724  { \
725   *((Context_Control_fp *) *((void **) _destination)) = _CPU_Null_fp_context; \
726  }
727
728#define _CPU_Context_save_fp( _fp_context ) \
729    _CPU_Save_float_context( *(Context_Control_fp **)(_fp_context))
730
731#define _CPU_Context_restore_fp( _fp_context ) \
732    _CPU_Restore_float_context( *(Context_Control_fp **)(_fp_context))
733
734extern void _CPU_Context_Initialize(
735  Context_Control  *_the_context,
736  unsigned32       *_stack_base,
737  unsigned32        _size,
738  unsigned32        _new_level,
739  void             *_entry_point,
740  boolean           _is_fp
741);
742
743/* end of Context handler macros */
744
745/* Fatal Error manager macros */
746
747/*
748 *  This routine copies _error into a known place -- typically a stack
749 *  location or a register, optionally disables interrupts, and
750 *  halts/stops the CPU.
751 */
752
753#define _CPU_Fatal_halt( _error ) \
754    _CPU_Fatal_error( _error )
755
756/* end of Fatal Error manager macros */
757
758/* Bitfield handler macros */
759
760/*
761 *  This routine sets _output to the bit number of the first bit
762 *  set in _value.  _value is of CPU dependent type Priority_Bit_map_control.
763 *  This type may be either 16 or 32 bits wide although only the 16
764 *  least significant bits will be used.
765 *
766 *  There are a number of variables in using a "find first bit" type
767 *  instruction.
768 *
769 *    (1) What happens when run on a value of zero?
770 *    (2) Bits may be numbered from MSB to LSB or vice-versa.
771 *    (3) The numbering may be zero or one based.
772 *    (4) The "find first bit" instruction may search from MSB or LSB.
773 *
774 *  RTEMS guarantees that (1) will never happen so it is not a concern.
775 *  (2),(3), (4) are handled by the macros _CPU_Priority_mask() and
776 *  _CPU_Priority_bits_index().  These three form a set of routines
777 *  which must logically operate together.  Bits in the _value are
778 *  set and cleared based on masks built by _CPU_Priority_mask().
779 *  The basic major and minor values calculated by _Priority_Major()
780 *  and _Priority_Minor() are "massaged" by _CPU_Priority_bits_index()
781 *  to properly range between the values returned by the "find first bit"
782 *  instruction.  This makes it possible for _Priority_Get_highest() to
783 *  calculate the major and directly index into the minor table.
784 *  This mapping is necessary to ensure that 0 (a high priority major/minor)
785 *  is the first bit found.
786 *
787 *  This entire "find first bit" and mapping process depends heavily
788 *  on the manner in which a priority is broken into a major and minor
789 *  components with the major being the 4 MSB of a priority and minor
790 *  the 4 LSB.  Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
791 *  priority.  And (15 << 4) + 14 corresponds to priority 254 -- the next
792 *  to the lowest priority.
793 *
794 *  If your CPU does not have a "find first bit" instruction, then
795 *  there are ways to make do without it.  Here are a handful of ways
796 *  to implement this in software:
797 *
798 *    - a series of 16 bit test instructions
799 *    - a "binary search using if's"
800 *    - _number = 0
801 *      if _value > 0x00ff
802 *        _value >>=8
803 *        _number = 8;
804 *
805 *      if _value > 0x0000f
806 *        _value >=8
807 *        _number += 4
808 *
809 *      _number += bit_set_table[ _value ]
810 *
811 *    where bit_set_table[ 16 ] has values which indicate the first
812 *      bit set
813 */
814
815/*
816 *  The UNIX port uses the generic C algorithm for bitfield scan to avoid
817 *  dependencies on either a native bitscan instruction or an ffs() in the
818 *  C library.
819 */
820 
821#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
822#define CPU_USE_GENERIC_BITFIELD_DATA TRUE
823 
824/* end of Bitfield handler macros */
825 
826/* Priority handler handler macros */
827 
828/*
829 *  The UNIX port uses the generic C algorithm for bitfield scan to avoid
830 *  dependencies on either a native bitscan instruction or an ffs() in the
831 *  C library.
832 */
833 
834/* end of Priority handler macros */
835
836/* functions */
837
838/*
839 *  _CPU_Initialize
840 *
841 *  This routine performs CPU dependent initialization.
842 */
843
844void _CPU_Initialize(
845  rtems_cpu_table  *cpu_table,
846  void      (*thread_dispatch)
847);
848
849/*
850 *  _CPU_ISR_install_raw_handler
851 *
852 *  This routine installs a "raw" interrupt handler directly into the
853 *  processor's vector table.
854 */
855 
856void _CPU_ISR_install_raw_handler(
857  unsigned32  vector,
858  proc_ptr    new_handler,
859  proc_ptr   *old_handler
860);
861
862/*
863 *  _CPU_ISR_install_vector
864 *
865 *  This routine installs an interrupt vector.
866 */
867
868void _CPU_ISR_install_vector(
869  unsigned32  vector,
870  proc_ptr    new_handler,
871  proc_ptr   *old_handler
872);
873
874/*
875 *  _CPU_Install_interrupt_stack
876 *
877 *  This routine installs the hardware interrupt stack pointer.
878 *
879 *  NOTE:  It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK
880 *         is TRUE.
881 */
882
883void _CPU_Install_interrupt_stack( void );
884
885/*
886 *  _CPU_Thread_Idle_body
887 *
888 *  This routine is the CPU dependent IDLE thread body.
889 *
890 *  NOTE:  It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY
891 *         is TRUE.
892 */
893
894void _CPU_Thread_Idle_body( void );
895
896/*
897 *  _CPU_Context_switch
898 *
899 *  This routine switches from the run context to the heir context.
900 */
901
902void _CPU_Context_switch(
903  Context_Control  *run,
904  Context_Control  *heir
905);
906
907/*
908 *  _CPU_Context_restore
909 *
910 *  This routine is generallu used only to restart self in an
911 *  efficient manner.  It may simply be a label in _CPU_Context_switch.
912 *
913 *  NOTE: May be unnecessary to reload some registers.
914 */
915
916void _CPU_Context_restore(
917  Context_Control *new_context
918);
919
920/*
921 *  _CPU_Save_float_context
922 *
923 *  This routine saves the floating point context passed to it.
924 */
925
926void _CPU_Save_float_context(
927  Context_Control_fp *fp_context_ptr
928);
929
930/*
931 *  _CPU_Restore_float_context
932 *
933 *  This routine restores the floating point context passed to it.
934 */
935
936void _CPU_Restore_float_context(
937  Context_Control_fp *fp_context_ptr
938);
939
940
941void _CPU_ISR_Set_signal_level(
942  unsigned32 level
943);
944
945void _CPU_Fatal_error(
946  unsigned32 _error
947);
948
949/*  The following routine swaps the endian format of an unsigned int.
950 *  It must be static because it is referenced indirectly.
951 *
952 *  This version will work on any processor, but if there is a better
953 *  way for your CPU PLEASE use it.  The most common way to do this is to:
954 *
955 *     swap least significant two bytes with 16-bit rotate
956 *     swap upper and lower 16-bits
957 *     swap most significant two bytes with 16-bit rotate
958 *
959 *  Some CPUs have special instructions which swap a 32-bit quantity in
960 *  a single instruction (e.g. i486).  It is probably best to avoid
961 *  an "endian swapping control bit" in the CPU.  One good reason is
962 *  that interrupts would probably have to be disabled to insure that
963 *  an interrupt does not try to access the same "chunk" with the wrong
964 *  endian.  Another good reason is that on some CPUs, the endian bit
965 *  endianness for ALL fetches -- both code and data -- so the code
966 *  will be fetched incorrectly.
967 */
968 
969static inline unsigned int CPU_swap_u32(
970  unsigned int value
971)
972{
973  unsigned32 byte1, byte2, byte3, byte4, swapped;
974 
975  byte4 = (value >> 24) & 0xff;
976  byte3 = (value >> 16) & 0xff;
977  byte2 = (value >> 8)  & 0xff;
978  byte1 =  value        & 0xff;
979 
980  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
981  return( swapped );
982}
983
984/*
985 *  Special Purpose Routines to hide the use of UNIX system calls.
986 */
987
988int _CPU_Get_clock_vector( void );
989
990void _CPU_Start_clock( 
991  int microseconds
992);
993
994void _CPU_Stop_clock( void );
995
996void _CPU_SHM_Init( 
997  unsigned32   maximum_nodes,
998  boolean      is_master_node,
999  void       **shm_address,
1000  unsigned32  *shm_length
1001);
1002
1003int _CPU_Get_pid( void );
1004 
1005int _CPU_SHM_Get_vector( void );
1006 
1007void _CPU_SHM_Send_interrupt(
1008  int pid,
1009  int vector
1010);
1011 
1012void _CPU_SHM_Lock( 
1013  int semaphore
1014);
1015
1016void _CPU_SHM_Unlock(
1017  int semaphore
1018);
1019
1020#ifdef __cplusplus
1021}
1022#endif
1023
1024#endif
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