source: rtems/c/src/exec/score/cpu/unix/cpu.h @ 37f4c2d

4.104.114.84.95
Last change on this file since 37f4c2d was 37f4c2d, checked in by Joel Sherrill <joel.sherrill@…>, on Sep 27, 1995 at 8:53:58 PM

Modified UNIX simulator port so all references to native unix
stuff is in the executive source proper in the file cpu.c. This
should help avoid conflicts between RTEMS POSIX files and UNIX files.

  • Property mode set to 100644
File size: 30.5 KB
Line 
1/*  cpu.h
2 *
3 *  This include file contains information pertaining to the HP
4 *  PA-RISC processor (Level 1.1).
5 *
6 *  COPYRIGHT (c) 1994 by Division Incorporated
7 *
8 *  To anyone who acknowledges that this file is provided "AS IS"
9 *  without any express or implied warranty:
10 *      permission to use, copy, modify, and distribute this file
11 *      for any purpose is hereby granted without fee, provided that
12 *      the above copyright notice and this notice appears in all
13 *      copies, and that the name of Division Incorporated not be
14 *      used in advertising or publicity pertaining to distribution
15 *      of the software without specific, written prior permission.
16 *      Division Incorporated makes no representations about the
17 *      suitability of this software for any purpose.
18 *
19 *  $Id$
20 */
21
22#ifndef __CPU_h
23#define __CPU_h
24
25#ifdef __cplusplus
26extern "C" {
27#endif
28
29#include <rtems/score/unix.h>
30#ifndef ASM
31#include <rtems/score/unixtypes.h>
32#endif
33
34#include <rtems/score/unixsize.h>
35
36#if defined(solaris2)
37#undef  _POSIX_C_SOURCE
38#define _POSIX_C_SOURCE 3
39#undef  __STRICT_ANSI__
40#define __STRICT_ANSI__
41#endif
42
43#if defined(linux)
44#define MALLOC_0_RETURNS_NULL
45#endif
46
47/* conditional compilation parameters */
48
49/*
50 *  Should the calls to _Thread_Enable_dispatch be inlined?
51 *
52 *  If TRUE, then they are inlined.
53 *  If FALSE, then a subroutine call is made.
54 *
55 *  Basically this is an example of the classic trade-off of size
56 *  versus speed.  Inlining the call (TRUE) typically increases the
57 *  size of RTEMS while speeding up the enabling of dispatching.
58 *  [NOTE: In general, the _Thread_Dispatch_disable_level will
59 *  only be 0 or 1 unless you are in an interrupt handler and that
60 *  interrupt handler invokes the executive.]  When not inlined
61 *  something calls _Thread_Enable_dispatch which in turns calls
62 *  _Thread_Dispatch.  If the enable dispatch is inlined, then
63 *  one subroutine call is avoided entirely.]
64 */
65
66#define CPU_INLINE_ENABLE_DISPATCH       FALSE
67
68/*
69 *  Should the body of the search loops in _Thread_queue_Enqueue_priority
70 *  be unrolled one time?  In unrolled each iteration of the loop examines
71 *  two "nodes" on the chain being searched.  Otherwise, only one node
72 *  is examined per iteration.
73 *
74 *  If TRUE, then the loops are unrolled.
75 *  If FALSE, then the loops are not unrolled.
76 *
77 *  The primary factor in making this decision is the cost of disabling
78 *  and enabling interrupts (_ISR_Flash) versus the cost of rest of the
79 *  body of the loop.  On some CPUs, the flash is more expensive than
80 *  one iteration of the loop body.  In this case, it might be desirable
81 *  to unroll the loop.  It is important to note that on some CPUs, this
82 *  code is the longest interrupt disable period in RTEMS.  So it is
83 *  necessary to strike a balance when setting this parameter.
84 */
85
86#define CPU_UNROLL_ENQUEUE_PRIORITY      TRUE
87
88/*
89 *  Does RTEMS manage a dedicated interrupt stack in software?
90 *
91 *  If TRUE, then a stack is allocated in _Interrupt_Manager_initialization.
92 *  If FALSE, nothing is done.
93 *
94 *  If the CPU supports a dedicated interrupt stack in hardware,
95 *  then it is generally the responsibility of the BSP to allocate it
96 *  and set it up.
97 *
98 *  If the CPU does not support a dedicated interrupt stack, then
99 *  the porter has two options: (1) execute interrupts on the
100 *  stack of the interrupted task, and (2) have RTEMS manage a dedicated
101 *  interrupt stack.
102 *
103 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
104 *
105 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
106 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
107 *  possible that both are FALSE for a particular CPU.  Although it
108 *  is unclear what that would imply about the interrupt processing
109 *  procedure on that CPU.
110 */
111
112#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE
113
114/*
115 *  Does this CPU have hardware support for a dedicated interrupt stack?
116 *
117 *  If TRUE, then it must be installed during initialization.
118 *  If FALSE, then no installation is performed.
119 *
120 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
121 *
122 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
123 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
124 *  possible that both are FALSE for a particular CPU.  Although it
125 *  is unclear what that would imply about the interrupt processing
126 *  procedure on that CPU.
127 */
128
129#define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE
130
131/*
132 *  Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
133 *
134 *  If TRUE, then the memory is allocated during initialization.
135 *  If FALSE, then the memory is allocated during initialization.
136 *
137 *  This should be TRUE if CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE
138 *  or CPU_INSTALL_HARDWARE_INTERRUPT_STACK is TRUE.
139 */
140
141#define CPU_ALLOCATE_INTERRUPT_STACK FALSE
142
143/*
144 *  Does the CPU have hardware floating point?
145 *
146 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
147 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
148 *
149 *  If there is a FP coprocessor such as the i387 or mc68881, then
150 *  the answer is TRUE.
151 *
152 *  The macro name "NO_CPU_HAS_FPU" should be made CPU specific.
153 *  It indicates whether or not this CPU model has FP support.  For
154 *  example, it would be possible to have an i386_nofp CPU model
155 *  which set this to false to indicate that you have an i386 without
156 *  an i387 and wish to leave floating point support out of RTEMS.
157 */
158
159#define CPU_HARDWARE_FP     TRUE
160
161/*
162 *  Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
163 *
164 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
165 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
166 *
167 *  So far, the only CPU in which this option has been used is the
168 *  HP PA-RISC.  The HP C compiler and gcc both implicitly use the
169 *  floating point registers to perform integer multiplies.  If
170 *  a function which you would not think utilize the FP unit DOES,
171 *  then one can not easily predict which tasks will use the FP hardware.
172 *  In this case, this option should be TRUE.
173 *
174 *  If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
175 */
176
177#define CPU_ALL_TASKS_ARE_FP     FALSE
178
179/*
180 *  Should the IDLE task have a floating point context?
181 *
182 *  If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
183 *  and it has a floating point context which is switched in and out.
184 *  If FALSE, then the IDLE task does not have a floating point context.
185 *
186 *  Setting this to TRUE negatively impacts the time required to preempt
187 *  the IDLE task from an interrupt because the floating point context
188 *  must be saved as part of the preemption.
189 */
190
191#define CPU_IDLE_TASK_IS_FP      FALSE
192
193/*
194 *  Should the saving of the floating point registers be deferred
195 *  until a context switch is made to another different floating point
196 *  task?
197 *
198 *  If TRUE, then the floating point context will not be stored until
199 *  necessary.  It will remain in the floating point registers and not
200 *  disturned until another floating point task is switched to.
201 *
202 *  If FALSE, then the floating point context is saved when a floating
203 *  point task is switched out and restored when the next floating point
204 *  task is restored.  The state of the floating point registers between
205 *  those two operations is not specified.
206 *
207 *  If the floating point context does NOT have to be saved as part of
208 *  interrupt dispatching, then it should be safe to set this to TRUE.
209 *
210 *  Setting this flag to TRUE results in using a different algorithm
211 *  for deciding when to save and restore the floating point context.
212 *  The deferred FP switch algorithm minimizes the number of times
213 *  the FP context is saved and restored.  The FP context is not saved
214 *  until a context switch is made to another, different FP task.
215 *  Thus in a system with only one FP task, the FP context will never
216 *  be saved or restored.
217 */
218
219#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
220
221/*
222 *  Does this port provide a CPU dependent IDLE task implementation?
223 *
224 *  If TRUE, then the routine _CPU_Internal_threads_Idle_thread_body
225 *  must be provided and is the default IDLE thread body instead of
226 *  _Internal_threads_Idle_thread_body.
227 *
228 *  If FALSE, then use the generic IDLE thread body if the BSP does
229 *  not provide one.
230 *
231 *  This is intended to allow for supporting processors which have
232 *  a low power or idle mode.  When the IDLE thread is executed, then
233 *  the CPU can be powered down.
234 *
235 *  The order of precedence for selecting the IDLE thread body is:
236 *
237 *    1.  BSP provided
238 *    2.  CPU dependent (if provided)
239 *    3.  generic (if no BSP and no CPU dependent)
240 */
241
242#define CPU_PROVIDES_IDLE_THREAD_BODY    TRUE
243
244/*
245 *  Does the stack grow up (toward higher addresses) or down
246 *  (toward lower addresses)?
247 *
248 *  If TRUE, then the grows upward.
249 *  If FALSE, then the grows toward smaller addresses.
250 */
251
252#if defined(hppa1_1)
253#define CPU_STACK_GROWS_UP               TRUE
254#elif defined(sparc) || defined(i386)
255#define CPU_STACK_GROWS_UP               FALSE
256#else
257#error "unknown CPU!!"
258#endif
259
260
261/*
262 *  The following is the variable attribute used to force alignment
263 *  of critical RTEMS structures.  On some processors it may make
264 *  sense to have these aligned on tighter boundaries than
265 *  the minimum requirements of the compiler in order to have as
266 *  much of the critical data area as possible in a cache line.
267 *
268 *  The placement of this macro in the declaration of the variables
269 *  is based on the syntactically requirements of the GNU C
270 *  "__attribute__" extension.  For example with GNU C, use
271 *  the following to force a structures to a 32 byte boundary.
272 *
273 *      __attribute__ ((aligned (32)))
274 *
275 *  NOTE:  Currently only the Priority Bit Map table uses this feature.
276 *         To benefit from using this, the data must be heavily
277 *         used so it will stay in the cache and used frequently enough
278 *         in the executive to justify turning this on.
279 */
280
281#define CPU_STRUCTURE_ALIGNMENT          __attribute__ ((aligned (32)))
282
283/*
284 *  The following defines the number of bits actually used in the
285 *  interrupt field of the task mode.  How those bits map to the
286 *  CPU interrupt levels is defined by the routine _CPU_ISR_Set_level().
287 */
288
289#define CPU_MODES_INTERRUPT_MASK   0x00000001
290
291#define CPU_NAME "UNIX"
292
293/*
294 *  Processor defined structures
295 *
296 *  Examples structures include the descriptor tables from the i386
297 *  and the processor control structure on the i960ca.
298 */
299
300/* may need to put some structures here.  */
301
302#if defined(hppa1_1)
303/*
304 * Word indices within a jmp_buf structure
305 */
306
307#ifdef RTEMS_NEWLIB_SETJMP
308#define RP_OFF       6
309#define SP_OFF       2
310#define R3_OFF      10
311#define R4_OFF      11
312#define R5_OFF      12
313#define R6_OFF      13
314#define R7_OFF      14
315#define R8_OFF      15
316#define R9_OFF      16
317#define R10_OFF     17
318#define R11_OFF     18
319#define R12_OFF     19
320#define R13_OFF     20
321#define R14_OFF     21
322#define R15_OFF     22
323#define R16_OFF     23
324#define R17_OFF     24
325#define R18_OFF     25
326#define DP_OFF      26
327#endif
328
329#ifdef RTEMS_UNIXLIB_SETJMP
330#define RP_OFF       0
331#define SP_OFF       1
332#define R3_OFF       4
333#define R4_OFF       5
334#define R5_OFF       6
335#define R6_OFF       7
336#define R7_OFF       8
337#define R8_OFF       9
338#define R9_OFF      10
339#define R10_OFF     11
340#define R11_OFF     12
341#define R12_OFF     13
342#define R13_OFF     14
343#define R14_OFF     15
344#define R15_OFF     16
345#define R16_OFF     17
346#define R17_OFF     18
347#define R18_OFF     19
348#define DP_OFF      20
349#endif
350#endif
351
352#if defined(i386)
353 
354#ifdef RTEMS_NEWLIB
355#error "Newlib not installed"
356#endif
357 
358/*
359 *  For Linux 1.1
360 */
361 
362#ifdef RTEMS_UNIXLIB
363#define EBX_OFF    0
364#define ESI_OFF    1
365#define EDI_OFF    2
366#define EBP_OFF    3
367#define ESP_OFF    4
368#define RET_OFF    5
369#endif
370 
371#endif
372 
373#if defined(sparc)
374
375/*
376 *  Word indices within a jmp_buf structure
377 */
378 
379#ifdef RTEMS_NEWLIB
380#define ADDR_ADJ_OFFSET -8
381#define SP_OFF    0
382#define RP_OFF    1
383#define FP_OFF    2
384#endif
385
386#ifdef RTEMS_UNIXLIB
387#define ADDR_ADJ_OFFSET 0
388#define G0_OFF    0
389#define SP_OFF    1
390#define RP_OFF    2   
391#define FP_OFF    3
392#define I7_OFF    4
393#endif
394
395#endif
396
397/*
398 * Contexts
399 *
400 *  Generally there are 2 types of context to save.
401 *     1. Interrupt registers to save
402 *     2. Task level registers to save
403 *
404 *  This means we have the following 3 context items:
405 *     1. task level context stuff::  Context_Control
406 *     2. floating point task stuff:: Context_Control_fp
407 *     3. special interrupt level context :: Context_Control_interrupt
408 *
409 *  On some processors, it is cost-effective to save only the callee
410 *  preserved registers during a task context switch.  This means
411 *  that the ISR code needs to save those registers which do not
412 *  persist across function calls.  It is not mandatory to make this
413 *  distinctions between the caller/callee saves registers for the
414 *  purpose of minimizing context saved during task switch and on interrupts.
415 *  If the cost of saving extra registers is minimal, simplicity is the
416 *  choice.  Save the same context on interrupt entry as for tasks in
417 *  this case.
418 *
419 *  Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
420 *  care should be used in designing the context area.
421 *
422 *  On some CPUs with hardware floating point support, the Context_Control_fp
423 *  structure will not be used or it simply consist of an array of a
424 *  fixed number of bytes.   This is done when the floating point context
425 *  is dumped by a "FP save context" type instruction and the format
426 *  is not really defined by the CPU.  In this case, there is no need
427 *  to figure out the exact format -- only the size.  Of course, although
428 *  this is enough information for RTEMS, it is probably not enough for
429 *  a debugger such as gdb.  But that is another problem.
430 */
431
432/*
433 *  This is really just the area for the following fields.
434 *
435 *    jmp_buf   regs;
436 *    sigset_t  isr_level;
437 *
438 *  Doing it this way avoids conflicts between the native stuff and the
439 *  RTEMS stuff.
440 */
441typedef struct {
442  char      Area[ CPU_CONTEXT_SIZE_IN_BYTES ];
443} Context_Control;
444
445typedef struct {
446} Context_Control_fp;
447
448typedef struct {
449} CPU_Interrupt_frame;
450
451
452/*
453 *  The following table contains the information required to configure
454 *  the XXX processor specific parameters.
455 *
456 *  NOTE: The interrupt_stack_size field is required if
457 *        CPU_ALLOCATE_INTERRUPT_STACK is defined as TRUE.
458 *
459 *        The pretasking_hook, predriver_hook, and postdriver_hook,
460 *        and the do_zero_of_workspace fields are required on ALL CPUs.
461 */
462
463typedef struct {
464  void       (*pretasking_hook)( void );
465  void       (*predriver_hook)( void );
466  void       (*postdriver_hook)( void );
467  void       (*idle_task)( void );
468  boolean      do_zero_of_workspace;
469  unsigned32   interrupt_stack_size;
470  unsigned32   extra_system_initialization_stack;
471}   rtems_cpu_table;
472
473/*
474 *  This variable is optional.  It is used on CPUs on which it is difficult
475 *  to generate an "uninitialized" FP context.  It is filled in by
476 *  _CPU_Initialize and copied into the task's FP context area during
477 *  _CPU_Context_Initialize.
478 */
479
480EXTERN Context_Control_fp  _CPU_Null_fp_context;
481
482/*
483 *  On some CPUs, RTEMS supports a software managed interrupt stack.
484 *  This stack is allocated by the Interrupt Manager and the switch
485 *  is performed in _ISR_Handler.  These variables contain pointers
486 *  to the lowest and highest addresses in the chunk of memory allocated
487 *  for the interrupt stack.  Since it is unknown whether the stack
488 *  grows up or down (in general), this give the CPU dependent
489 *  code the option of picking the version it wants to use.
490 *
491 *  NOTE: These two variables are required if the macro
492 *        CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
493 */
494
495EXTERN void               *_CPU_Interrupt_stack_low;
496EXTERN void               *_CPU_Interrupt_stack_high;
497
498/*
499 *  With some compilation systems, it is difficult if not impossible to
500 *  call a high-level language routine from assembly language.  This
501 *  is especially true of commercial Ada compilers and name mangling
502 *  C++ ones.  This variable can be optionally defined by the CPU porter
503 *  and contains the address of the routine _Thread_Dispatch.  This
504 *  can make it easier to invoke that routine at the end of the interrupt
505 *  sequence (if a dispatch is necessary).
506 */
507
508EXTERN void           (*_CPU_Thread_dispatch_pointer)();
509
510/*
511 *  Nothing prevents the porter from declaring more CPU specific variables.
512 */
513
514/* XXX: if needed, put more variables here */
515
516/*
517 *  The size of the floating point context area.  On some CPUs this
518 *  will not be a "sizeof" because the format of the floating point
519 *  area is not defined -- only the size is.  This is usually on
520 *  CPUs with a "floating point save context" instruction.
521 */
522
523#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
524
525/*
526 * The size of a frame on the stack
527 */
528
529#if defined(hppa1_1)
530#define CPU_FRAME_SIZE  (32 * 4)
531#elif defined(sparc)
532#define CPU_FRAME_SIZE  (112)   /* based on disassembled test code */
533#elif defined(i386)
534#define CPU_FRAME_SIZE  (24)  /* return address, sp, and bp pushed plus fudge */
535#else
536#error "Unknown CPU!!!"
537#endif
538
539/*
540 *  Amount of extra stack (above minimum stack size) required by
541 *  system initialization thread.  Remember that in a multiprocessor
542 *  system the system intialization thread becomes the MP server thread.
543 */
544
545#define CPU_SYSTEM_INITIALIZATION_THREAD_EXTRA_STACK 0
546
547/*
548 *  This defines the number of entries in the ISR_Vector_table managed
549 *  by RTEMS.
550 */
551
552#define CPU_INTERRUPT_NUMBER_OF_VECTORS  64
553
554/*
555 *  Should be large enough to run all RTEMS tests.  This insures
556 *  that a "reasonable" small application should not have any problems.
557 */
558
559#define CPU_STACK_MINIMUM_SIZE          (16 * 1024)
560
561/*
562 *  CPU's worst alignment requirement for data types on a byte boundary.  This
563 *  alignment does not take into account the requirements for the stack.
564 */
565
566#define CPU_ALIGNMENT              8
567
568/*
569 *  This number corresponds to the byte alignment requirement for the
570 *  heap handler.  This alignment requirement may be stricter than that
571 *  for the data types alignment specified by CPU_ALIGNMENT.  It is
572 *  common for the heap to follow the same alignment requirement as
573 *  CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict enough for the heap,
574 *  then this should be set to CPU_ALIGNMENT.
575 *
576 *  NOTE:  This does not have to be a power of 2.  It does have to
577 *         be greater or equal to than CPU_ALIGNMENT.
578 */
579
580#define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT
581
582/*
583 *  This number corresponds to the byte alignment requirement for memory
584 *  buffers allocated by the partition manager.  This alignment requirement
585 *  may be stricter than that for the data types alignment specified by
586 *  CPU_ALIGNMENT.  It is common for the partition to follow the same
587 *  alignment requirement as CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict
588 *  enough for the partition, then this should be set to CPU_ALIGNMENT.
589 *
590 *  NOTE:  This does not have to be a power of 2.  It does have to
591 *         be greater or equal to than CPU_ALIGNMENT.
592 */
593
594#define CPU_PARTITION_ALIGNMENT    CPU_ALIGNMENT
595
596/*
597 *  This number corresponds to the byte alignment requirement for the
598 *  stack.  This alignment requirement may be stricter than that for the
599 *  data types alignment specified by CPU_ALIGNMENT.  If the CPU_ALIGNMENT
600 *  is strict enough for the stack, then this should be set to 0.
601 *
602 *  NOTE:  This must be a power of 2 either 0 or greater than CPU_ALIGNMENT.
603 */
604
605#define CPU_STACK_ALIGNMENT        64
606
607/* ISR handler macros */
608
609/*
610 *  Disable all interrupts for an RTEMS critical section.  The previous
611 *  level is returned in _level.
612 */
613
614extern unsigned32 _CPU_ISR_Disable_support(void);
615
616#define _CPU_ISR_Disable( _level ) \
617    do { \
618      (_level) = _CPU_ISR_Disable_support(); \
619    } while ( 0 )
620
621/*
622 *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
623 *  This indicates the end of an RTEMS critical section.  The parameter
624 *  _level is not modified.
625 */
626
627void _CPU_ISR_Enable(unsigned32 level);
628
629/*
630 *  This temporarily restores the interrupt to _level before immediately
631 *  disabling them again.  This is used to divide long RTEMS critical
632 *  sections into two or more parts.  The parameter _level is not
633 * modified.
634 */
635
636#define _CPU_ISR_Flash( _level ) \
637  do { \
638      register _ignored = 0; \
639      _CPU_ISR_Enable( (_level) ); \
640      _CPU_ISR_Disable( _ignored ); \
641  } while ( 0 )
642
643/*
644 *  Map interrupt level in task mode onto the hardware that the CPU
645 *  actually provides.  Currently, interrupt levels which do not
646 *  map onto the CPU in a generic fashion are undefined.  Someday,
647 *  it would be nice if these were "mapped" by the application
648 *  via a callout.  For example, m68k has 8 levels 0 - 7, levels
649 *  8 - 255 would be available for bsp/application specific meaning.
650 *  This could be used to manage a programmable interrupt controller
651 *  via the rtems_task_mode directive.
652 */
653
654#define _CPU_ISR_Set_level( new_level ) \
655  { \
656    if ( new_level == 0 ) _CPU_ISR_Enable( 0 ); \
657    else                  _CPU_ISR_Enable( 1 ); \
658  }
659
660unsigned32 _CPU_ISR_Get_level( void );
661
662/* end of ISR handler macros */
663
664/* Context handler macros */
665
666/*
667 *  This routine is responsible for somehow restarting the currently
668 *  executing task.  If you are lucky, then all that is necessary
669 *  is restoring the context.  Otherwise, there will need to be
670 *  a special assembly routine which does something special in this
671 *  case.  Context_Restore should work most of the time.  It will
672 *  not work if restarting self conflicts with the stack frame
673 *  assumptions of restoring a context.
674 */
675
676#define _CPU_Context_Restart_self( _the_context ) \
677   _CPU_Context_restore( (_the_context) );
678
679/*
680 *  The purpose of this macro is to allow the initial pointer into
681 *  a floating point context area (used to save the floating point
682 *  context) to be at an arbitrary place in the floating point
683 *  context area.
684 *
685 *  This is necessary because some FP units are designed to have
686 *  their context saved as a stack which grows into lower addresses.
687 *  Other FP units can be saved by simply moving registers into offsets
688 *  from the base of the context area.  Finally some FP units provide
689 *  a "dump context" instruction which could fill in from high to low
690 *  or low to high based on the whim of the CPU designers.
691 */
692
693#define _CPU_Context_Fp_start( _base, _offset ) \
694   ( (void *) (_base) + (_offset) )
695
696/*
697 *  This routine initializes the FP context area passed to it to.
698 *  There are a few standard ways in which to initialize the
699 *  floating point context.  The code included for this macro assumes
700 *  that this is a CPU in which a "initial" FP context was saved into
701 *  _CPU_Null_fp_context and it simply copies it to the destination
702 *  context passed to it.
703 *
704 *  Other models include (1) not doing anything, and (2) putting
705 *  a "null FP status word" in the correct place in the FP context.
706 */
707
708#define _CPU_Context_Initialize_fp( _destination ) \
709  { \
710   *((Context_Control_fp *) *((void **) _destination)) = _CPU_Null_fp_context; \
711  }
712
713#define _CPU_Context_save_fp( _fp_context ) \
714    _CPU_Save_float_context( *(Context_Control_fp **)(_fp_context))
715
716#define _CPU_Context_restore_fp( _fp_context ) \
717    _CPU_Restore_float_context( *(Context_Control_fp **)(_fp_context))
718
719extern void _CPU_Context_Initialize(
720  Context_Control  *_the_context,
721  unsigned32       *_stack_base,
722  unsigned32        _size,
723  unsigned32        _new_level,
724  void             *_entry_point
725);
726
727/* end of Context handler macros */
728
729/* Fatal Error manager macros */
730
731/*
732 *  This routine copies _error into a known place -- typically a stack
733 *  location or a register, optionally disables interrupts, and
734 *  halts/stops the CPU.
735 */
736
737#define _CPU_Fatal_halt( _error ) \
738    _CPU_Fatal_error( _error )
739
740/* end of Fatal Error manager macros */
741
742/* Bitfield handler macros */
743
744/*
745 *  This routine sets _output to the bit number of the first bit
746 *  set in _value.  _value is of CPU dependent type Priority_Bit_map_control.
747 *  This type may be either 16 or 32 bits wide although only the 16
748 *  least significant bits will be used.
749 *
750 *  There are a number of variables in using a "find first bit" type
751 *  instruction.
752 *
753 *    (1) What happens when run on a value of zero?
754 *    (2) Bits may be numbered from MSB to LSB or vice-versa.
755 *    (3) The numbering may be zero or one based.
756 *    (4) The "find first bit" instruction may search from MSB or LSB.
757 *
758 *  RTEMS guarantees that (1) will never happen so it is not a concern.
759 *  (2),(3), (4) are handled by the macros _CPU_Priority_mask() and
760 *  _CPU_Priority_Bits_index().  These three form a set of routines
761 *  which must logically operate together.  Bits in the _value are
762 *  set and cleared based on masks built by _CPU_Priority_mask().
763 *  The basic major and minor values calculated by _Priority_Major()
764 *  and _Priority_Minor() are "massaged" by _CPU_Priority_Bits_index()
765 *  to properly range between the values returned by the "find first bit"
766 *  instruction.  This makes it possible for _Priority_Get_highest() to
767 *  calculate the major and directly index into the minor table.
768 *  This mapping is necessary to ensure that 0 (a high priority major/minor)
769 *  is the first bit found.
770 *
771 *  This entire "find first bit" and mapping process depends heavily
772 *  on the manner in which a priority is broken into a major and minor
773 *  components with the major being the 4 MSB of a priority and minor
774 *  the 4 LSB.  Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
775 *  priority.  And (15 << 4) + 14 corresponds to priority 254 -- the next
776 *  to the lowest priority.
777 *
778 *  If your CPU does not have a "find first bit" instruction, then
779 *  there are ways to make do without it.  Here are a handful of ways
780 *  to implement this in software:
781 *
782 *    - a series of 16 bit test instructions
783 *    - a "binary search using if's"
784 *    - _number = 0
785 *      if _value > 0x00ff
786 *        _value >>=8
787 *        _number = 8;
788 *
789 *      if _value > 0x0000f
790 *        _value >=8
791 *        _number += 4
792 *
793 *      _number += bit_set_table[ _value ]
794 *
795 *    where bit_set_table[ 16 ] has values which indicate the first
796 *      bit set
797 */
798
799#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
800    _output = _CPU_ffs( _value )
801
802/* end of Bitfield handler macros */
803
804/*
805 *  This routine builds the mask which corresponds to the bit fields
806 *  as searched by _CPU_Bitfield_Find_first_bit().  See the discussion
807 *  for that routine.
808 */
809
810#define _CPU_Priority_Mask( _bit_number ) \
811  ( 1 << (_bit_number) )
812
813/*
814 *  This routine translates the bit numbers returned by
815 *  _CPU_Bitfield_Find_first_bit() into something suitable for use as
816 *  a major or minor component of a priority.  See the discussion
817 *  for that routine.
818 */
819
820#define _CPU_Priority_Bits_index( _priority ) \
821  (_priority)
822
823/* end of Priority handler macros */
824
825/* functions */
826
827/*
828 *  _CPU_Initialize
829 *
830 *  This routine performs CPU dependent initialization.
831 */
832
833void _CPU_Initialize(
834  rtems_cpu_table  *cpu_table,
835  void      (*thread_dispatch)
836);
837
838/*
839 *  _CPU_ISR_install_raw_handler
840 *
841 *  This routine installs a "raw" interrupt handler directly into the
842 *  processor's vector table.
843 */
844 
845void _CPU_ISR_install_raw_handler(
846  unsigned32  vector,
847  proc_ptr    new_handler,
848  proc_ptr   *old_handler
849);
850
851/*
852 *  _CPU_ISR_install_vector
853 *
854 *  This routine installs an interrupt vector.
855 */
856
857void _CPU_ISR_install_vector(
858  unsigned32  vector,
859  proc_ptr    new_handler,
860  proc_ptr   *old_handler
861);
862
863/*
864 *  _CPU_Install_interrupt_stack
865 *
866 *  This routine installs the hardware interrupt stack pointer.
867 *
868 *  NOTE:  It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK
869 *         is TRUE.
870 */
871
872void _CPU_Install_interrupt_stack( void );
873
874/*
875 *  _CPU_Internal_threads_Idle_thread_body
876 *
877 *  This routine is the CPU dependent IDLE thread body.
878 *
879 *  NOTE:  It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY
880 *         is TRUE.
881 */
882
883void _CPU_Internal_threads_Idle_thread_body( void );
884
885/*
886 *  _CPU_Context_switch
887 *
888 *  This routine switches from the run context to the heir context.
889 */
890
891void _CPU_Context_switch(
892  Context_Control  *run,
893  Context_Control  *heir
894);
895
896/*
897 *  _CPU_Context_restore
898 *
899 *  This routine is generallu used only to restart self in an
900 *  efficient manner.  It may simply be a label in _CPU_Context_switch.
901 *
902 *  NOTE: May be unnecessary to reload some registers.
903 */
904
905void _CPU_Context_restore(
906  Context_Control *new_context
907);
908
909/*
910 *  _CPU_Save_float_context
911 *
912 *  This routine saves the floating point context passed to it.
913 */
914
915void _CPU_Save_float_context(
916  Context_Control_fp *fp_context_ptr
917);
918
919/*
920 *  _CPU_Restore_float_context
921 *
922 *  This routine restores the floating point context passed to it.
923 */
924
925void _CPU_Restore_float_context(
926  Context_Control_fp *fp_context_ptr
927);
928
929
930void _CPU_ISR_Set_signal_level(
931  unsigned32 level
932);
933
934void _CPU_Fatal_error(
935  unsigned32 _error
936);
937
938int _CPU_ffs(
939  unsigned32 _value
940);
941
942/*  The following routine swaps the endian format of an unsigned int.
943 *  It must be static because it is referenced indirectly.
944 *
945 *  This version will work on any processor, but if there is a better
946 *  way for your CPU PLEASE use it.  The most common way to do this is to:
947 *
948 *     swap least significant two bytes with 16-bit rotate
949 *     swap upper and lower 16-bits
950 *     swap most significant two bytes with 16-bit rotate
951 *
952 *  Some CPUs have special instructions which swap a 32-bit quantity in
953 *  a single instruction (e.g. i486).  It is probably best to avoid
954 *  an "endian swapping control bit" in the CPU.  One good reason is
955 *  that interrupts would probably have to be disabled to insure that
956 *  an interrupt does not try to access the same "chunk" with the wrong
957 *  endian.  Another good reason is that on some CPUs, the endian bit
958 *  endianness for ALL fetches -- both code and data -- so the code
959 *  will be fetched incorrectly.
960 */
961 
962static inline unsigned int CPU_swap_u32(
963  unsigned int value
964)
965{
966  unsigned32 byte1, byte2, byte3, byte4, swapped;
967 
968  byte4 = (value >> 24) & 0xff;
969  byte3 = (value >> 16) & 0xff;
970  byte2 = (value >> 8)  & 0xff;
971  byte1 =  value        & 0xff;
972 
973  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
974  return( swapped );
975}
976
977/*
978 *  Special Purpose Routines to hide the use of UNIX system calls.
979 */
980
981int _CPU_Get_clock_vector( void );
982
983void _CPU_Start_clock( 
984  int microseconds
985);
986
987void _CPU_Stop_clock( void );
988
989void _CPU_SHM_Init( 
990  unsigned32   maximum_nodes,
991  boolean      is_master_node,
992  void       **shm_address,
993  unsigned32  *shm_length
994);
995
996int _CPU_Get_pid( void );
997 
998int _CPU_SHM_Get_vector( void );
999 
1000void _CPU_SHM_Send_interrupt(
1001  int pid,
1002  int vector
1003);
1004 
1005void _CPU_SHM_Lock( 
1006  int semaphore
1007);
1008
1009void _CPU_SHM_Unlock(
1010  int semaphore
1011);
1012
1013#ifdef __cplusplus
1014}
1015#endif
1016
1017#endif
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