source: rtems/c/src/exec/score/cpu/unix/cpu.h @ 0d55427

4.104.114.84.95
Last change on this file since 0d55427 was 0d55427, checked in by Joel Sherrill <joel.sherrill@…>, on Aug 2, 1995 at 8:01:26 PM

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1/*  cpu.h
2 *
3 *  This include file contains information pertaining to the HP
4 *  PA-RISC processor (Level 1.1).
5 *
6 *  COPYRIGHT (c) 1994 by Division Incorporated
7 *
8 *  To anyone who acknowledges that this file is provided "AS IS"
9 *  without any express or implied warranty:
10 *      permission to use, copy, modify, and distribute this file
11 *      for any purpose is hereby granted without fee, provided that
12 *      the above copyright notice and this notice appears in all
13 *      copies, and that the name of Division Incorporated not be
14 *      used in advertising or publicity pertaining to distribution
15 *      of the software without specific, written prior permission.
16 *      Division Incorporated makes no representations about the
17 *      suitability of this software for any purpose.
18 *
19 *  $Id$
20 */
21
22#ifndef __CPU_h
23#define __CPU_h
24
25#ifdef __cplusplus
26extern "C" {
27#endif
28
29#include <rtems/unix.h>
30#ifndef ASM
31#include <rtems/unixtypes.h>
32#endif
33
34#if defined(solaris2)
35#undef  _POSIX_C_SOURCE
36#define _POSIX_C_SOURCE 3
37#undef  __STRICT_ANSI__
38#define __STRICT_ANSI__
39#endif
40
41#if defined(linux)
42#define MALLOC_0_RETURNS_NULL
43#endif
44
45#if 0
46
47/*
48 *  In order to get the types and prototypes used in this file under
49 *  Solaris 2.3, it is necessary to pull the following magic.
50 */
51
52#if defined(solaris2)
53#warning "Ignore the undefining __STDC__ warning"
54#undef __STDC__
55#define __STDC__ 0
56#undef  _POSIX_C_SOURCE
57#endif
58
59#endif
60
61#if 0
62static inline X()
63{
64#ifdef _POSIX_C_SOURCE
65  printf( "_POSIX_C_SOURCE", _POSIX_C_SOURCE );
66#endif
67#ifdef __STRICT_ANSI__
68  printf( "__STRICT_ANSI__", __STRICT_ANSI__ );
69#endif
70}
71#endif
72
73#include <unistd.h>
74#include <setjmp.h>
75#include <signal.h>
76
77/* conditional compilation parameters */
78
79/*
80 *  Should the calls to _Thread_Enable_dispatch be inlined?
81 *
82 *  If TRUE, then they are inlined.
83 *  If FALSE, then a subroutine call is made.
84 *
85 *  Basically this is an example of the classic trade-off of size
86 *  versus speed.  Inlining the call (TRUE) typically increases the
87 *  size of RTEMS while speeding up the enabling of dispatching.
88 *  [NOTE: In general, the _Thread_Dispatch_disable_level will
89 *  only be 0 or 1 unless you are in an interrupt handler and that
90 *  interrupt handler invokes the executive.]  When not inlined
91 *  something calls _Thread_Enable_dispatch which in turns calls
92 *  _Thread_Dispatch.  If the enable dispatch is inlined, then
93 *  one subroutine call is avoided entirely.]
94 */
95
96#define CPU_INLINE_ENABLE_DISPATCH       FALSE
97
98/*
99 *  Should the body of the search loops in _Thread_queue_Enqueue_priority
100 *  be unrolled one time?  In unrolled each iteration of the loop examines
101 *  two "nodes" on the chain being searched.  Otherwise, only one node
102 *  is examined per iteration.
103 *
104 *  If TRUE, then the loops are unrolled.
105 *  If FALSE, then the loops are not unrolled.
106 *
107 *  The primary factor in making this decision is the cost of disabling
108 *  and enabling interrupts (_ISR_Flash) versus the cost of rest of the
109 *  body of the loop.  On some CPUs, the flash is more expensive than
110 *  one iteration of the loop body.  In this case, it might be desirable
111 *  to unroll the loop.  It is important to note that on some CPUs, this
112 *  code is the longest interrupt disable period in RTEMS.  So it is
113 *  necessary to strike a balance when setting this parameter.
114 */
115
116#define CPU_UNROLL_ENQUEUE_PRIORITY      TRUE
117
118/*
119 *  Does RTEMS manage a dedicated interrupt stack in software?
120 *
121 *  If TRUE, then a stack is allocated in _Interrupt_Manager_initialization.
122 *  If FALSE, nothing is done.
123 *
124 *  If the CPU supports a dedicated interrupt stack in hardware,
125 *  then it is generally the responsibility of the BSP to allocate it
126 *  and set it up.
127 *
128 *  If the CPU does not support a dedicated interrupt stack, then
129 *  the porter has two options: (1) execute interrupts on the
130 *  stack of the interrupted task, and (2) have RTEMS manage a dedicated
131 *  interrupt stack.
132 *
133 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
134 *
135 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
136 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
137 *  possible that both are FALSE for a particular CPU.  Although it
138 *  is unclear what that would imply about the interrupt processing
139 *  procedure on that CPU.
140 */
141
142#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE
143
144/*
145 *  Does this CPU have hardware support for a dedicated interrupt stack?
146 *
147 *  If TRUE, then it must be installed during initialization.
148 *  If FALSE, then no installation is performed.
149 *
150 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
151 *
152 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
153 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
154 *  possible that both are FALSE for a particular CPU.  Although it
155 *  is unclear what that would imply about the interrupt processing
156 *  procedure on that CPU.
157 */
158
159#define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE
160
161/*
162 *  Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
163 *
164 *  If TRUE, then the memory is allocated during initialization.
165 *  If FALSE, then the memory is allocated during initialization.
166 *
167 *  This should be TRUE if CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE
168 *  or CPU_INSTALL_HARDWARE_INTERRUPT_STACK is TRUE.
169 */
170
171#define CPU_ALLOCATE_INTERRUPT_STACK FALSE
172
173/*
174 *  Does the CPU have hardware floating point?
175 *
176 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
177 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
178 *
179 *  If there is a FP coprocessor such as the i387 or mc68881, then
180 *  the answer is TRUE.
181 *
182 *  The macro name "NO_CPU_HAS_FPU" should be made CPU specific.
183 *  It indicates whether or not this CPU model has FP support.  For
184 *  example, it would be possible to have an i386_nofp CPU model
185 *  which set this to false to indicate that you have an i386 without
186 *  an i387 and wish to leave floating point support out of RTEMS.
187 */
188
189#define CPU_HARDWARE_FP     TRUE
190
191/*
192 *  Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
193 *
194 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
195 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
196 *
197 *  So far, the only CPU in which this option has been used is the
198 *  HP PA-RISC.  The HP C compiler and gcc both implicitly use the
199 *  floating point registers to perform integer multiplies.  If
200 *  a function which you would not think utilize the FP unit DOES,
201 *  then one can not easily predict which tasks will use the FP hardware.
202 *  In this case, this option should be TRUE.
203 *
204 *  If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
205 */
206
207#define CPU_ALL_TASKS_ARE_FP     FALSE
208
209/*
210 *  Should the IDLE task have a floating point context?
211 *
212 *  If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
213 *  and it has a floating point context which is switched in and out.
214 *  If FALSE, then the IDLE task does not have a floating point context.
215 *
216 *  Setting this to TRUE negatively impacts the time required to preempt
217 *  the IDLE task from an interrupt because the floating point context
218 *  must be saved as part of the preemption.
219 */
220
221#define CPU_IDLE_TASK_IS_FP      FALSE
222
223/*
224 *  Should the saving of the floating point registers be deferred
225 *  until a context switch is made to another different floating point
226 *  task?
227 *
228 *  If TRUE, then the floating point context will not be stored until
229 *  necessary.  It will remain in the floating point registers and not
230 *  disturned until another floating point task is switched to.
231 *
232 *  If FALSE, then the floating point context is saved when a floating
233 *  point task is switched out and restored when the next floating point
234 *  task is restored.  The state of the floating point registers between
235 *  those two operations is not specified.
236 *
237 *  If the floating point context does NOT have to be saved as part of
238 *  interrupt dispatching, then it should be safe to set this to TRUE.
239 *
240 *  Setting this flag to TRUE results in using a different algorithm
241 *  for deciding when to save and restore the floating point context.
242 *  The deferred FP switch algorithm minimizes the number of times
243 *  the FP context is saved and restored.  The FP context is not saved
244 *  until a context switch is made to another, different FP task.
245 *  Thus in a system with only one FP task, the FP context will never
246 *  be saved or restored.
247 */
248
249#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
250
251/*
252 *  Does this port provide a CPU dependent IDLE task implementation?
253 *
254 *  If TRUE, then the routine _CPU_Internal_threads_Idle_thread_body
255 *  must be provided and is the default IDLE thread body instead of
256 *  _Internal_threads_Idle_thread_body.
257 *
258 *  If FALSE, then use the generic IDLE thread body if the BSP does
259 *  not provide one.
260 *
261 *  This is intended to allow for supporting processors which have
262 *  a low power or idle mode.  When the IDLE thread is executed, then
263 *  the CPU can be powered down.
264 *
265 *  The order of precedence for selecting the IDLE thread body is:
266 *
267 *    1.  BSP provided
268 *    2.  CPU dependent (if provided)
269 *    3.  generic (if no BSP and no CPU dependent)
270 */
271
272#define CPU_PROVIDES_IDLE_THREAD_BODY    TRUE
273
274/*
275 *  Does the stack grow up (toward higher addresses) or down
276 *  (toward lower addresses)?
277 *
278 *  If TRUE, then the grows upward.
279 *  If FALSE, then the grows toward smaller addresses.
280 */
281
282#if defined(hppa1_1)
283#define CPU_STACK_GROWS_UP               TRUE
284#elif defined(sparc) || defined(i386)
285#define CPU_STACK_GROWS_UP               FALSE
286#else
287#error "unknown CPU!!"
288#endif
289
290
291/*
292 *  The following is the variable attribute used to force alignment
293 *  of critical RTEMS structures.  On some processors it may make
294 *  sense to have these aligned on tighter boundaries than
295 *  the minimum requirements of the compiler in order to have as
296 *  much of the critical data area as possible in a cache line.
297 *
298 *  The placement of this macro in the declaration of the variables
299 *  is based on the syntactically requirements of the GNU C
300 *  "__attribute__" extension.  For example with GNU C, use
301 *  the following to force a structures to a 32 byte boundary.
302 *
303 *      __attribute__ ((aligned (32)))
304 *
305 *  NOTE:  Currently only the Priority Bit Map table uses this feature.
306 *         To benefit from using this, the data must be heavily
307 *         used so it will stay in the cache and used frequently enough
308 *         in the executive to justify turning this on.
309 */
310
311#define CPU_STRUCTURE_ALIGNMENT          __attribute__ ((aligned (32)))
312
313/*
314 *  The following defines the number of bits actually used in the
315 *  interrupt field of the task mode.  How those bits map to the
316 *  CPU interrupt levels is defined by the routine _CPU_ISR_Set_level().
317 */
318
319#define CPU_MODES_INTERRUPT_MASK   0x00000001
320
321#define CPU_NAME "UNIX"
322
323/*
324 *  Processor defined structures
325 *
326 *  Examples structures include the descriptor tables from the i386
327 *  and the processor control structure on the i960ca.
328 */
329
330/* may need to put some structures here.  */
331
332#if defined(hppa1_1)
333/*
334 * Word indices within a jmp_buf structure
335 */
336
337#ifdef RTEMS_NEWLIB
338#define RP_OFF       6
339#define SP_OFF       2
340#define R3_OFF      10
341#define R4_OFF      11
342#define R5_OFF      12
343#define R6_OFF      13
344#define R7_OFF      14
345#define R8_OFF      15
346#define R9_OFF      16
347#define R10_OFF     17
348#define R11_OFF     18
349#define R12_OFF     19
350#define R13_OFF     20
351#define R14_OFF     21
352#define R15_OFF     22
353#define R16_OFF     23
354#define R17_OFF     24
355#define R18_OFF     25
356#define DP_OFF      26
357#endif
358
359#ifdef RTEMS_UNIXLIB
360#define RP_OFF       0
361#define SP_OFF       1
362#define R3_OFF       4
363#define R4_OFF       5
364#define R5_OFF       6
365#define R6_OFF       7
366#define R7_OFF       8
367#define R8_OFF       9
368#define R9_OFF      10
369#define R10_OFF     11
370#define R11_OFF     12
371#define R12_OFF     13
372#define R13_OFF     14
373#define R14_OFF     15
374#define R15_OFF     16
375#define R16_OFF     17
376#define R17_OFF     18
377#define R18_OFF     19
378#define DP_OFF      20
379#endif
380#endif
381
382#if defined(i386)
383 
384#ifdef RTEMS_NEWLIB
385#error "Newlib not installed"
386#endif
387 
388/*
389 *  For Linux 1.1
390 */
391 
392#ifdef RTEMS_UNIXLIB
393#define EBX_OFF    0
394#define ESI_OFF    1
395#define EDI_OFF    2
396#define EBP_OFF    3
397#define ESP_OFF    4
398#define RET_OFF    5
399#endif
400 
401#endif
402 
403#if defined(sparc)
404
405/*
406 *  Word indices within a jmp_buf structure
407 */
408 
409#ifdef RTEMS_NEWLIB
410#define ADDR_ADJ_OFFSET -8
411#define SP_OFF    0
412#define RP_OFF    1
413#define FP_OFF    2
414#endif
415
416#ifdef RTEMS_UNIXLIB
417#define ADDR_ADJ_OFFSET 0
418#define G0_OFF    0
419#define SP_OFF    1
420#define RP_OFF    2   
421#define FP_OFF    3
422#define I7_OFF    4
423#endif
424
425#endif
426
427/*
428 * Contexts
429 *
430 *  Generally there are 2 types of context to save.
431 *     1. Interrupt registers to save
432 *     2. Task level registers to save
433 *
434 *  This means we have the following 3 context items:
435 *     1. task level context stuff::  Context_Control
436 *     2. floating point task stuff:: Context_Control_fp
437 *     3. special interrupt level context :: Context_Control_interrupt
438 *
439 *  On some processors, it is cost-effective to save only the callee
440 *  preserved registers during a task context switch.  This means
441 *  that the ISR code needs to save those registers which do not
442 *  persist across function calls.  It is not mandatory to make this
443 *  distinctions between the caller/callee saves registers for the
444 *  purpose of minimizing context saved during task switch and on interrupts.
445 *  If the cost of saving extra registers is minimal, simplicity is the
446 *  choice.  Save the same context on interrupt entry as for tasks in
447 *  this case.
448 *
449 *  Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
450 *  care should be used in designing the context area.
451 *
452 *  On some CPUs with hardware floating point support, the Context_Control_fp
453 *  structure will not be used or it simply consist of an array of a
454 *  fixed number of bytes.   This is done when the floating point context
455 *  is dumped by a "FP save context" type instruction and the format
456 *  is not really defined by the CPU.  In this case, there is no need
457 *  to figure out the exact format -- only the size.  Of course, although
458 *  this is enough information for RTEMS, it is probably not enough for
459 *  a debugger such as gdb.  But that is another problem.
460 */
461
462typedef struct {
463  jmp_buf   regs;
464  sigset_t  isr_level;
465} Context_Control;
466
467typedef struct {
468} Context_Control_fp;
469
470typedef struct {
471} CPU_Interrupt_frame;
472
473
474/*
475 *  The following table contains the information required to configure
476 *  the XXX processor specific parameters.
477 *
478 *  NOTE: The interrupt_stack_size field is required if
479 *        CPU_ALLOCATE_INTERRUPT_STACK is defined as TRUE.
480 *
481 *        The pretasking_hook, predriver_hook, and postdriver_hook,
482 *        and the do_zero_of_workspace fields are required on ALL CPUs.
483 */
484
485typedef struct {
486  void       (*pretasking_hook)( void );
487  void       (*predriver_hook)( void );
488  void       (*postdriver_hook)( void );
489  void       (*idle_task)( void );
490  boolean      do_zero_of_workspace;
491  unsigned32   interrupt_stack_size;
492  unsigned32   extra_system_initialization_stack;
493}   rtems_cpu_table;
494
495/*
496 *  This variable is optional.  It is used on CPUs on which it is difficult
497 *  to generate an "uninitialized" FP context.  It is filled in by
498 *  _CPU_Initialize and copied into the task's FP context area during
499 *  _CPU_Context_Initialize.
500 */
501
502EXTERN Context_Control_fp  _CPU_Null_fp_context;
503
504/*
505 *  On some CPUs, RTEMS supports a software managed interrupt stack.
506 *  This stack is allocated by the Interrupt Manager and the switch
507 *  is performed in _ISR_Handler.  These variables contain pointers
508 *  to the lowest and highest addresses in the chunk of memory allocated
509 *  for the interrupt stack.  Since it is unknown whether the stack
510 *  grows up or down (in general), this give the CPU dependent
511 *  code the option of picking the version it wants to use.
512 *
513 *  NOTE: These two variables are required if the macro
514 *        CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
515 */
516
517EXTERN void               *_CPU_Interrupt_stack_low;
518EXTERN void               *_CPU_Interrupt_stack_high;
519
520/*
521 *  With some compilation systems, it is difficult if not impossible to
522 *  call a high-level language routine from assembly language.  This
523 *  is especially true of commercial Ada compilers and name mangling
524 *  C++ ones.  This variable can be optionally defined by the CPU porter
525 *  and contains the address of the routine _Thread_Dispatch.  This
526 *  can make it easier to invoke that routine at the end of the interrupt
527 *  sequence (if a dispatch is necessary).
528 */
529
530EXTERN void           (*_CPU_Thread_dispatch_pointer)();
531
532/*
533 *  Nothing prevents the porter from declaring more CPU specific variables.
534 */
535
536/* XXX: if needed, put more variables here */
537
538/*
539 *  The size of the floating point context area.  On some CPUs this
540 *  will not be a "sizeof" because the format of the floating point
541 *  area is not defined -- only the size is.  This is usually on
542 *  CPUs with a "floating point save context" instruction.
543 */
544
545#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
546
547/*
548 * The size of a frame on the stack
549 */
550
551#if defined(hppa1_1)
552#define CPU_FRAME_SIZE  (32 * 4)
553#elif defined(sparc)
554#define CPU_FRAME_SIZE  (112)   /* based on disassembled test code */
555#elif defined(i386)
556#define CPU_FRAME_SIZE  (24)  /* return address, sp, and bp pushed plus fudge */
557#else
558#error "Unknown CPU!!!"
559#endif
560
561/*
562 *  Amount of extra stack (above minimum stack size) required by
563 *  system initialization thread.  Remember that in a multiprocessor
564 *  system the system intialization thread becomes the MP server thread.
565 */
566
567#define CPU_SYSTEM_INITIALIZATION_THREAD_EXTRA_STACK 0
568
569/*
570 *  This defines the number of entries in the ISR_Vector_table managed
571 *  by RTEMS.
572 */
573
574#define CPU_INTERRUPT_NUMBER_OF_VECTORS  64
575
576/*
577 *  Should be large enough to run all RTEMS tests.  This insures
578 *  that a "reasonable" small application should not have any problems.
579 */
580
581#define CPU_STACK_MINIMUM_SIZE          (16 * 1024)
582
583/*
584 *  CPU's worst alignment requirement for data types on a byte boundary.  This
585 *  alignment does not take into account the requirements for the stack.
586 */
587
588#define CPU_ALIGNMENT              8
589
590/*
591 *  This number corresponds to the byte alignment requirement for the
592 *  heap handler.  This alignment requirement may be stricter than that
593 *  for the data types alignment specified by CPU_ALIGNMENT.  It is
594 *  common for the heap to follow the same alignment requirement as
595 *  CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict enough for the heap,
596 *  then this should be set to CPU_ALIGNMENT.
597 *
598 *  NOTE:  This does not have to be a power of 2.  It does have to
599 *         be greater or equal to than CPU_ALIGNMENT.
600 */
601
602#define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT
603
604/*
605 *  This number corresponds to the byte alignment requirement for memory
606 *  buffers allocated by the partition manager.  This alignment requirement
607 *  may be stricter than that for the data types alignment specified by
608 *  CPU_ALIGNMENT.  It is common for the partition to follow the same
609 *  alignment requirement as CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict
610 *  enough for the partition, then this should be set to CPU_ALIGNMENT.
611 *
612 *  NOTE:  This does not have to be a power of 2.  It does have to
613 *         be greater or equal to than CPU_ALIGNMENT.
614 */
615
616#define CPU_PARTITION_ALIGNMENT    CPU_ALIGNMENT
617
618/*
619 *  This number corresponds to the byte alignment requirement for the
620 *  stack.  This alignment requirement may be stricter than that for the
621 *  data types alignment specified by CPU_ALIGNMENT.  If the CPU_ALIGNMENT
622 *  is strict enough for the stack, then this should be set to 0.
623 *
624 *  NOTE:  This must be a power of 2 either 0 or greater than CPU_ALIGNMENT.
625 */
626
627#define CPU_STACK_ALIGNMENT        64
628
629/* ISR handler macros */
630
631/*
632 *  Disable all interrupts for an RTEMS critical section.  The previous
633 *  level is returned in _level.
634 */
635
636extern unsigned32 _CPU_ISR_Disable_support(void);
637
638#define _CPU_ISR_Disable( _level ) \
639    do { \
640      (_level) = _CPU_ISR_Disable_support(); \
641    } while ( 0 )
642
643/*
644 *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
645 *  This indicates the end of an RTEMS critical section.  The parameter
646 *  _level is not modified.
647 */
648
649void _CPU_ISR_Enable(unsigned32 level);
650
651/*
652 *  This temporarily restores the interrupt to _level before immediately
653 *  disabling them again.  This is used to divide long RTEMS critical
654 *  sections into two or more parts.  The parameter _level is not
655 * modified.
656 */
657
658#define _CPU_ISR_Flash( _level ) \
659  do { \
660      register _ignored = 0; \
661      _CPU_ISR_Enable( (_level) ); \
662      _CPU_ISR_Disable( _ignored ); \
663  } while ( 0 )
664
665/*
666 *  Map interrupt level in task mode onto the hardware that the CPU
667 *  actually provides.  Currently, interrupt levels which do not
668 *  map onto the CPU in a generic fashion are undefined.  Someday,
669 *  it would be nice if these were "mapped" by the application
670 *  via a callout.  For example, m68k has 8 levels 0 - 7, levels
671 *  8 - 255 would be available for bsp/application specific meaning.
672 *  This could be used to manage a programmable interrupt controller
673 *  via the rtems_task_mode directive.
674 */
675
676#define _CPU_ISR_Set_level( new_level ) \
677  { \
678    if ( new_level == 0 ) _CPU_ISR_Enable( 0 ); \
679    else                  _CPU_ISR_Enable( 1 ); \
680  }
681
682/* end of ISR handler macros */
683
684/* Context handler macros */
685
686/*
687 *  This routine is responsible for somehow restarting the currently
688 *  executing task.  If you are lucky, then all that is necessary
689 *  is restoring the context.  Otherwise, there will need to be
690 *  a special assembly routine which does something special in this
691 *  case.  Context_Restore should work most of the time.  It will
692 *  not work if restarting self conflicts with the stack frame
693 *  assumptions of restoring a context.
694 */
695
696#define _CPU_Context_Restart_self( _the_context ) \
697   _CPU_Context_restore( (_the_context) );
698
699/*
700 *  The purpose of this macro is to allow the initial pointer into
701 *  a floating point context area (used to save the floating point
702 *  context) to be at an arbitrary place in the floating point
703 *  context area.
704 *
705 *  This is necessary because some FP units are designed to have
706 *  their context saved as a stack which grows into lower addresses.
707 *  Other FP units can be saved by simply moving registers into offsets
708 *  from the base of the context area.  Finally some FP units provide
709 *  a "dump context" instruction which could fill in from high to low
710 *  or low to high based on the whim of the CPU designers.
711 */
712
713#define _CPU_Context_Fp_start( _base, _offset ) \
714   ( (void *) (_base) + (_offset) )
715
716/*
717 *  This routine initializes the FP context area passed to it to.
718 *  There are a few standard ways in which to initialize the
719 *  floating point context.  The code included for this macro assumes
720 *  that this is a CPU in which a "initial" FP context was saved into
721 *  _CPU_Null_fp_context and it simply copies it to the destination
722 *  context passed to it.
723 *
724 *  Other models include (1) not doing anything, and (2) putting
725 *  a "null FP status word" in the correct place in the FP context.
726 */
727
728#define _CPU_Context_Initialize_fp( _destination ) \
729  { \
730   *((Context_Control_fp *) *((void **) _destination)) = _CPU_Null_fp_context; \
731  }
732
733#define _CPU_Context_save_fp( _fp_context ) \
734    _CPU_Save_float_context( *(Context_Control_fp **)(_fp_context))
735
736#define _CPU_Context_restore_fp( _fp_context ) \
737    _CPU_Restore_float_context( *(Context_Control_fp **)(_fp_context))
738
739extern void _CPU_Context_Initialize(
740  Context_Control  *_the_context,
741  unsigned32       *_stack_base,
742  unsigned32        _size,
743  unsigned32        _new_level,
744  void             *_entry_point
745);
746
747/* end of Context handler macros */
748
749/* Fatal Error manager macros */
750
751/*
752 *  This routine copies _error into a known place -- typically a stack
753 *  location or a register, optionally disables interrupts, and
754 *  halts/stops the CPU.
755 */
756
757#define _CPU_Fatal_halt( _error ) \
758    _CPU_Fatal_error( _error )
759
760/* end of Fatal Error manager macros */
761
762/* Bitfield handler macros */
763
764/*
765 *  This routine sets _output to the bit number of the first bit
766 *  set in _value.  _value is of CPU dependent type Priority_Bit_map_control.
767 *  This type may be either 16 or 32 bits wide although only the 16
768 *  least significant bits will be used.
769 *
770 *  There are a number of variables in using a "find first bit" type
771 *  instruction.
772 *
773 *    (1) What happens when run on a value of zero?
774 *    (2) Bits may be numbered from MSB to LSB or vice-versa.
775 *    (3) The numbering may be zero or one based.
776 *    (4) The "find first bit" instruction may search from MSB or LSB.
777 *
778 *  RTEMS guarantees that (1) will never happen so it is not a concern.
779 *  (2),(3), (4) are handled by the macros _CPU_Priority_mask() and
780 *  _CPU_Priority_Bits_index().  These three form a set of routines
781 *  which must logically operate together.  Bits in the _value are
782 *  set and cleared based on masks built by _CPU_Priority_mask().
783 *  The basic major and minor values calculated by _Priority_Major()
784 *  and _Priority_Minor() are "massaged" by _CPU_Priority_Bits_index()
785 *  to properly range between the values returned by the "find first bit"
786 *  instruction.  This makes it possible for _Priority_Get_highest() to
787 *  calculate the major and directly index into the minor table.
788 *  This mapping is necessary to ensure that 0 (a high priority major/minor)
789 *  is the first bit found.
790 *
791 *  This entire "find first bit" and mapping process depends heavily
792 *  on the manner in which a priority is broken into a major and minor
793 *  components with the major being the 4 MSB of a priority and minor
794 *  the 4 LSB.  Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
795 *  priority.  And (15 << 4) + 14 corresponds to priority 254 -- the next
796 *  to the lowest priority.
797 *
798 *  If your CPU does not have a "find first bit" instruction, then
799 *  there are ways to make do without it.  Here are a handful of ways
800 *  to implement this in software:
801 *
802 *    - a series of 16 bit test instructions
803 *    - a "binary search using if's"
804 *    - _number = 0
805 *      if _value > 0x00ff
806 *        _value >>=8
807 *        _number = 8;
808 *
809 *      if _value > 0x0000f
810 *        _value >=8
811 *        _number += 4
812 *
813 *      _number += bit_set_table[ _value ]
814 *
815 *    where bit_set_table[ 16 ] has values which indicate the first
816 *      bit set
817 */
818
819#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
820    _output = _CPU_ffs( _value )
821
822/* end of Bitfield handler macros */
823
824/*
825 *  This routine builds the mask which corresponds to the bit fields
826 *  as searched by _CPU_Bitfield_Find_first_bit().  See the discussion
827 *  for that routine.
828 */
829
830#define _CPU_Priority_Mask( _bit_number ) \
831  ( 1 << (_bit_number) )
832
833/*
834 *  This routine translates the bit numbers returned by
835 *  _CPU_Bitfield_Find_first_bit() into something suitable for use as
836 *  a major or minor component of a priority.  See the discussion
837 *  for that routine.
838 */
839
840#define _CPU_Priority_Bits_index( _priority ) \
841  (_priority)
842
843/* end of Priority handler macros */
844
845/* functions */
846
847/*
848 *  _CPU_Initialize
849 *
850 *  This routine performs CPU dependent initialization.
851 */
852
853void _CPU_Initialize(
854  rtems_cpu_table  *cpu_table,
855  void      (*thread_dispatch)
856);
857
858/*
859 *  _CPU_ISR_install_raw_handler
860 *
861 *  This routine installs a "raw" interrupt handler directly into the
862 *  processor's vector table.
863 */
864 
865void _CPU_ISR_install_raw_handler(
866  unsigned32  vector,
867  proc_ptr    new_handler,
868  proc_ptr   *old_handler
869);
870
871/*
872 *  _CPU_ISR_install_vector
873 *
874 *  This routine installs an interrupt vector.
875 */
876
877void _CPU_ISR_install_vector(
878  unsigned32  vector,
879  proc_ptr    new_handler,
880  proc_ptr   *old_handler
881);
882
883/*
884 *  _CPU_Install_interrupt_stack
885 *
886 *  This routine installs the hardware interrupt stack pointer.
887 *
888 *  NOTE:  It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK
889 *         is TRUE.
890 */
891
892void _CPU_Install_interrupt_stack( void );
893
894/*
895 *  _CPU_Internal_threads_Idle_thread_body
896 *
897 *  This routine is the CPU dependent IDLE thread body.
898 *
899 *  NOTE:  It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY
900 *         is TRUE.
901 */
902
903void _CPU_Internal_threads_Idle_thread_body( void );
904
905/*
906 *  _CPU_Context_switch
907 *
908 *  This routine switches from the run context to the heir context.
909 */
910
911void _CPU_Context_switch(
912  Context_Control  *run,
913  Context_Control  *heir
914);
915
916/*
917 *  _CPU_Context_restore
918 *
919 *  This routine is generallu used only to restart self in an
920 *  efficient manner.  It may simply be a label in _CPU_Context_switch.
921 *
922 *  NOTE: May be unnecessary to reload some registers.
923 */
924
925void _CPU_Context_restore(
926  Context_Control *new_context
927);
928
929/*
930 *  _CPU_Save_float_context
931 *
932 *  This routine saves the floating point context passed to it.
933 */
934
935void _CPU_Save_float_context(
936  Context_Control_fp *fp_context_ptr
937);
938
939/*
940 *  _CPU_Restore_float_context
941 *
942 *  This routine restores the floating point context passed to it.
943 */
944
945void _CPU_Restore_float_context(
946  Context_Control_fp *fp_context_ptr
947);
948
949
950void _CPU_ISR_Set_signal_level(
951  unsigned32 level
952);
953
954void _CPU_Fatal_error(
955  unsigned32 _error
956);
957
958int _CPU_ffs(
959  unsigned32 _value
960);
961
962/*  The following routine swaps the endian format of an unsigned int.
963 *  It must be static because it is referenced indirectly.
964 *
965 *  This version will work on any processor, but if there is a better
966 *  way for your CPU PLEASE use it.  The most common way to do this is to:
967 *
968 *     swap least significant two bytes with 16-bit rotate
969 *     swap upper and lower 16-bits
970 *     swap most significant two bytes with 16-bit rotate
971 *
972 *  Some CPUs have special instructions which swap a 32-bit quantity in
973 *  a single instruction (e.g. i486).  It is probably best to avoid
974 *  an "endian swapping control bit" in the CPU.  One good reason is
975 *  that interrupts would probably have to be disabled to insure that
976 *  an interrupt does not try to access the same "chunk" with the wrong
977 *  endian.  Another good reason is that on some CPUs, the endian bit
978 *  endianness for ALL fetches -- both code and data -- so the code
979 *  will be fetched incorrectly.
980 */
981 
982static inline unsigned int CPU_swap_u32(
983  unsigned int value
984)
985{
986  unsigned32 byte1, byte2, byte3, byte4, swapped;
987 
988  byte4 = (value >> 24) & 0xff;
989  byte3 = (value >> 16) & 0xff;
990  byte2 = (value >> 8)  & 0xff;
991  byte1 =  value        & 0xff;
992 
993  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
994  return( swapped );
995}
996
997#ifdef __cplusplus
998}
999#endif
1000
1001#endif
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