[ac7d5ef0] | 1 | /* cpu.h |
---|
| 2 | * |
---|
| 3 | * This include file contains information pertaining to the HP |
---|
| 4 | * PA-RISC processor (Level 1.1). |
---|
| 5 | * |
---|
| 6 | * COPYRIGHT (c) 1994 by Division Incorporated |
---|
| 7 | * |
---|
| 8 | * To anyone who acknowledges that this file is provided "AS IS" |
---|
| 9 | * without any express or implied warranty: |
---|
| 10 | * permission to use, copy, modify, and distribute this file |
---|
| 11 | * for any purpose is hereby granted without fee, provided that |
---|
| 12 | * the above copyright notice and this notice appears in all |
---|
| 13 | * copies, and that the name of Division Incorporated not be |
---|
| 14 | * used in advertising or publicity pertaining to distribution |
---|
| 15 | * of the software without specific, written prior permission. |
---|
| 16 | * Division Incorporated makes no representations about the |
---|
| 17 | * suitability of this software for any purpose. |
---|
| 18 | * |
---|
| 19 | * $Id$ |
---|
| 20 | */ |
---|
| 21 | |
---|
| 22 | #ifndef __CPU_h |
---|
| 23 | #define __CPU_h |
---|
| 24 | |
---|
| 25 | #ifdef __cplusplus |
---|
| 26 | extern "C" { |
---|
| 27 | #endif |
---|
| 28 | |
---|
[3a4ae6c] | 29 | #include <rtems/core/unix.h> |
---|
[88d594a] | 30 | #ifndef ASM |
---|
[3a4ae6c] | 31 | #include <rtems/core/unixtypes.h> |
---|
[88d594a] | 32 | #endif |
---|
[ac7d5ef0] | 33 | |
---|
[637df35] | 34 | #if defined(solaris2) |
---|
| 35 | #undef _POSIX_C_SOURCE |
---|
| 36 | #define _POSIX_C_SOURCE 3 |
---|
| 37 | #undef __STRICT_ANSI__ |
---|
| 38 | #define __STRICT_ANSI__ |
---|
| 39 | #endif |
---|
| 40 | |
---|
[217d2e7] | 41 | #if defined(linux) |
---|
| 42 | #define MALLOC_0_RETURNS_NULL |
---|
| 43 | #endif |
---|
| 44 | |
---|
[637df35] | 45 | #if 0 |
---|
| 46 | |
---|
| 47 | /* |
---|
| 48 | * In order to get the types and prototypes used in this file under |
---|
| 49 | * Solaris 2.3, it is necessary to pull the following magic. |
---|
| 50 | */ |
---|
| 51 | |
---|
| 52 | #if defined(solaris2) |
---|
| 53 | #warning "Ignore the undefining __STDC__ warning" |
---|
| 54 | #undef __STDC__ |
---|
| 55 | #define __STDC__ 0 |
---|
| 56 | #undef _POSIX_C_SOURCE |
---|
| 57 | #endif |
---|
| 58 | |
---|
| 59 | #endif |
---|
| 60 | |
---|
[0d55427] | 61 | #include <unistd.h> |
---|
[637df35] | 62 | #include <setjmp.h> |
---|
| 63 | #include <signal.h> |
---|
| 64 | |
---|
[ac7d5ef0] | 65 | /* conditional compilation parameters */ |
---|
| 66 | |
---|
| 67 | /* |
---|
| 68 | * Should the calls to _Thread_Enable_dispatch be inlined? |
---|
| 69 | * |
---|
| 70 | * If TRUE, then they are inlined. |
---|
| 71 | * If FALSE, then a subroutine call is made. |
---|
| 72 | * |
---|
| 73 | * Basically this is an example of the classic trade-off of size |
---|
| 74 | * versus speed. Inlining the call (TRUE) typically increases the |
---|
| 75 | * size of RTEMS while speeding up the enabling of dispatching. |
---|
| 76 | * [NOTE: In general, the _Thread_Dispatch_disable_level will |
---|
| 77 | * only be 0 or 1 unless you are in an interrupt handler and that |
---|
| 78 | * interrupt handler invokes the executive.] When not inlined |
---|
| 79 | * something calls _Thread_Enable_dispatch which in turns calls |
---|
| 80 | * _Thread_Dispatch. If the enable dispatch is inlined, then |
---|
| 81 | * one subroutine call is avoided entirely.] |
---|
| 82 | */ |
---|
| 83 | |
---|
| 84 | #define CPU_INLINE_ENABLE_DISPATCH FALSE |
---|
| 85 | |
---|
| 86 | /* |
---|
| 87 | * Should the body of the search loops in _Thread_queue_Enqueue_priority |
---|
| 88 | * be unrolled one time? In unrolled each iteration of the loop examines |
---|
| 89 | * two "nodes" on the chain being searched. Otherwise, only one node |
---|
| 90 | * is examined per iteration. |
---|
| 91 | * |
---|
| 92 | * If TRUE, then the loops are unrolled. |
---|
| 93 | * If FALSE, then the loops are not unrolled. |
---|
| 94 | * |
---|
| 95 | * The primary factor in making this decision is the cost of disabling |
---|
| 96 | * and enabling interrupts (_ISR_Flash) versus the cost of rest of the |
---|
| 97 | * body of the loop. On some CPUs, the flash is more expensive than |
---|
| 98 | * one iteration of the loop body. In this case, it might be desirable |
---|
| 99 | * to unroll the loop. It is important to note that on some CPUs, this |
---|
| 100 | * code is the longest interrupt disable period in RTEMS. So it is |
---|
| 101 | * necessary to strike a balance when setting this parameter. |
---|
| 102 | */ |
---|
| 103 | |
---|
| 104 | #define CPU_UNROLL_ENQUEUE_PRIORITY TRUE |
---|
| 105 | |
---|
| 106 | /* |
---|
| 107 | * Does RTEMS manage a dedicated interrupt stack in software? |
---|
| 108 | * |
---|
| 109 | * If TRUE, then a stack is allocated in _Interrupt_Manager_initialization. |
---|
| 110 | * If FALSE, nothing is done. |
---|
| 111 | * |
---|
| 112 | * If the CPU supports a dedicated interrupt stack in hardware, |
---|
| 113 | * then it is generally the responsibility of the BSP to allocate it |
---|
| 114 | * and set it up. |
---|
| 115 | * |
---|
| 116 | * If the CPU does not support a dedicated interrupt stack, then |
---|
| 117 | * the porter has two options: (1) execute interrupts on the |
---|
| 118 | * stack of the interrupted task, and (2) have RTEMS manage a dedicated |
---|
| 119 | * interrupt stack. |
---|
| 120 | * |
---|
| 121 | * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. |
---|
| 122 | * |
---|
| 123 | * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and |
---|
| 124 | * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is |
---|
| 125 | * possible that both are FALSE for a particular CPU. Although it |
---|
| 126 | * is unclear what that would imply about the interrupt processing |
---|
| 127 | * procedure on that CPU. |
---|
| 128 | */ |
---|
| 129 | |
---|
| 130 | #define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE |
---|
| 131 | |
---|
| 132 | /* |
---|
| 133 | * Does this CPU have hardware support for a dedicated interrupt stack? |
---|
| 134 | * |
---|
| 135 | * If TRUE, then it must be installed during initialization. |
---|
| 136 | * If FALSE, then no installation is performed. |
---|
| 137 | * |
---|
| 138 | * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. |
---|
| 139 | * |
---|
| 140 | * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and |
---|
| 141 | * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is |
---|
| 142 | * possible that both are FALSE for a particular CPU. Although it |
---|
| 143 | * is unclear what that would imply about the interrupt processing |
---|
| 144 | * procedure on that CPU. |
---|
| 145 | */ |
---|
| 146 | |
---|
| 147 | #define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE |
---|
| 148 | |
---|
| 149 | /* |
---|
| 150 | * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager? |
---|
| 151 | * |
---|
| 152 | * If TRUE, then the memory is allocated during initialization. |
---|
| 153 | * If FALSE, then the memory is allocated during initialization. |
---|
| 154 | * |
---|
| 155 | * This should be TRUE if CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE |
---|
| 156 | * or CPU_INSTALL_HARDWARE_INTERRUPT_STACK is TRUE. |
---|
| 157 | */ |
---|
| 158 | |
---|
| 159 | #define CPU_ALLOCATE_INTERRUPT_STACK FALSE |
---|
| 160 | |
---|
| 161 | /* |
---|
| 162 | * Does the CPU have hardware floating point? |
---|
| 163 | * |
---|
| 164 | * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported. |
---|
| 165 | * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored. |
---|
| 166 | * |
---|
| 167 | * If there is a FP coprocessor such as the i387 or mc68881, then |
---|
| 168 | * the answer is TRUE. |
---|
| 169 | * |
---|
| 170 | * The macro name "NO_CPU_HAS_FPU" should be made CPU specific. |
---|
| 171 | * It indicates whether or not this CPU model has FP support. For |
---|
| 172 | * example, it would be possible to have an i386_nofp CPU model |
---|
| 173 | * which set this to false to indicate that you have an i386 without |
---|
| 174 | * an i387 and wish to leave floating point support out of RTEMS. |
---|
| 175 | */ |
---|
| 176 | |
---|
| 177 | #define CPU_HARDWARE_FP TRUE |
---|
| 178 | |
---|
| 179 | /* |
---|
| 180 | * Are all tasks RTEMS_FLOATING_POINT tasks implicitly? |
---|
| 181 | * |
---|
| 182 | * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed. |
---|
| 183 | * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed. |
---|
| 184 | * |
---|
| 185 | * So far, the only CPU in which this option has been used is the |
---|
| 186 | * HP PA-RISC. The HP C compiler and gcc both implicitly use the |
---|
| 187 | * floating point registers to perform integer multiplies. If |
---|
| 188 | * a function which you would not think utilize the FP unit DOES, |
---|
| 189 | * then one can not easily predict which tasks will use the FP hardware. |
---|
| 190 | * In this case, this option should be TRUE. |
---|
| 191 | * |
---|
| 192 | * If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well. |
---|
| 193 | */ |
---|
| 194 | |
---|
| 195 | #define CPU_ALL_TASKS_ARE_FP FALSE |
---|
| 196 | |
---|
| 197 | /* |
---|
| 198 | * Should the IDLE task have a floating point context? |
---|
| 199 | * |
---|
| 200 | * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task |
---|
| 201 | * and it has a floating point context which is switched in and out. |
---|
| 202 | * If FALSE, then the IDLE task does not have a floating point context. |
---|
| 203 | * |
---|
| 204 | * Setting this to TRUE negatively impacts the time required to preempt |
---|
| 205 | * the IDLE task from an interrupt because the floating point context |
---|
| 206 | * must be saved as part of the preemption. |
---|
| 207 | */ |
---|
| 208 | |
---|
| 209 | #define CPU_IDLE_TASK_IS_FP FALSE |
---|
| 210 | |
---|
| 211 | /* |
---|
| 212 | * Should the saving of the floating point registers be deferred |
---|
| 213 | * until a context switch is made to another different floating point |
---|
| 214 | * task? |
---|
| 215 | * |
---|
| 216 | * If TRUE, then the floating point context will not be stored until |
---|
| 217 | * necessary. It will remain in the floating point registers and not |
---|
| 218 | * disturned until another floating point task is switched to. |
---|
| 219 | * |
---|
| 220 | * If FALSE, then the floating point context is saved when a floating |
---|
| 221 | * point task is switched out and restored when the next floating point |
---|
| 222 | * task is restored. The state of the floating point registers between |
---|
| 223 | * those two operations is not specified. |
---|
| 224 | * |
---|
| 225 | * If the floating point context does NOT have to be saved as part of |
---|
| 226 | * interrupt dispatching, then it should be safe to set this to TRUE. |
---|
| 227 | * |
---|
| 228 | * Setting this flag to TRUE results in using a different algorithm |
---|
| 229 | * for deciding when to save and restore the floating point context. |
---|
| 230 | * The deferred FP switch algorithm minimizes the number of times |
---|
| 231 | * the FP context is saved and restored. The FP context is not saved |
---|
| 232 | * until a context switch is made to another, different FP task. |
---|
| 233 | * Thus in a system with only one FP task, the FP context will never |
---|
| 234 | * be saved or restored. |
---|
| 235 | */ |
---|
| 236 | |
---|
| 237 | #define CPU_USE_DEFERRED_FP_SWITCH TRUE |
---|
| 238 | |
---|
| 239 | /* |
---|
| 240 | * Does this port provide a CPU dependent IDLE task implementation? |
---|
| 241 | * |
---|
| 242 | * If TRUE, then the routine _CPU_Internal_threads_Idle_thread_body |
---|
| 243 | * must be provided and is the default IDLE thread body instead of |
---|
| 244 | * _Internal_threads_Idle_thread_body. |
---|
| 245 | * |
---|
| 246 | * If FALSE, then use the generic IDLE thread body if the BSP does |
---|
| 247 | * not provide one. |
---|
| 248 | * |
---|
| 249 | * This is intended to allow for supporting processors which have |
---|
| 250 | * a low power or idle mode. When the IDLE thread is executed, then |
---|
| 251 | * the CPU can be powered down. |
---|
| 252 | * |
---|
| 253 | * The order of precedence for selecting the IDLE thread body is: |
---|
| 254 | * |
---|
| 255 | * 1. BSP provided |
---|
| 256 | * 2. CPU dependent (if provided) |
---|
| 257 | * 3. generic (if no BSP and no CPU dependent) |
---|
| 258 | */ |
---|
| 259 | |
---|
| 260 | #define CPU_PROVIDES_IDLE_THREAD_BODY TRUE |
---|
| 261 | |
---|
| 262 | /* |
---|
| 263 | * Does the stack grow up (toward higher addresses) or down |
---|
| 264 | * (toward lower addresses)? |
---|
| 265 | * |
---|
| 266 | * If TRUE, then the grows upward. |
---|
| 267 | * If FALSE, then the grows toward smaller addresses. |
---|
| 268 | */ |
---|
| 269 | |
---|
| 270 | #if defined(hppa1_1) |
---|
| 271 | #define CPU_STACK_GROWS_UP TRUE |
---|
[8044533] | 272 | #elif defined(sparc) || defined(i386) |
---|
[ac7d5ef0] | 273 | #define CPU_STACK_GROWS_UP FALSE |
---|
| 274 | #else |
---|
| 275 | #error "unknown CPU!!" |
---|
| 276 | #endif |
---|
| 277 | |
---|
| 278 | |
---|
| 279 | /* |
---|
| 280 | * The following is the variable attribute used to force alignment |
---|
| 281 | * of critical RTEMS structures. On some processors it may make |
---|
| 282 | * sense to have these aligned on tighter boundaries than |
---|
| 283 | * the minimum requirements of the compiler in order to have as |
---|
| 284 | * much of the critical data area as possible in a cache line. |
---|
| 285 | * |
---|
| 286 | * The placement of this macro in the declaration of the variables |
---|
| 287 | * is based on the syntactically requirements of the GNU C |
---|
| 288 | * "__attribute__" extension. For example with GNU C, use |
---|
| 289 | * the following to force a structures to a 32 byte boundary. |
---|
| 290 | * |
---|
| 291 | * __attribute__ ((aligned (32))) |
---|
| 292 | * |
---|
| 293 | * NOTE: Currently only the Priority Bit Map table uses this feature. |
---|
| 294 | * To benefit from using this, the data must be heavily |
---|
| 295 | * used so it will stay in the cache and used frequently enough |
---|
| 296 | * in the executive to justify turning this on. |
---|
| 297 | */ |
---|
| 298 | |
---|
| 299 | #define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned (32))) |
---|
| 300 | |
---|
| 301 | /* |
---|
| 302 | * The following defines the number of bits actually used in the |
---|
| 303 | * interrupt field of the task mode. How those bits map to the |
---|
| 304 | * CPU interrupt levels is defined by the routine _CPU_ISR_Set_level(). |
---|
| 305 | */ |
---|
| 306 | |
---|
| 307 | #define CPU_MODES_INTERRUPT_MASK 0x00000001 |
---|
| 308 | |
---|
| 309 | #define CPU_NAME "UNIX" |
---|
| 310 | |
---|
| 311 | /* |
---|
| 312 | * Processor defined structures |
---|
| 313 | * |
---|
| 314 | * Examples structures include the descriptor tables from the i386 |
---|
| 315 | * and the processor control structure on the i960ca. |
---|
| 316 | */ |
---|
| 317 | |
---|
| 318 | /* may need to put some structures here. */ |
---|
| 319 | |
---|
| 320 | #if defined(hppa1_1) |
---|
| 321 | /* |
---|
| 322 | * Word indices within a jmp_buf structure |
---|
| 323 | */ |
---|
| 324 | |
---|
[e7e016f] | 325 | #ifdef RTEMS_NEWLIB_SETJMP |
---|
[ac7d5ef0] | 326 | #define RP_OFF 6 |
---|
| 327 | #define SP_OFF 2 |
---|
| 328 | #define R3_OFF 10 |
---|
| 329 | #define R4_OFF 11 |
---|
| 330 | #define R5_OFF 12 |
---|
| 331 | #define R6_OFF 13 |
---|
| 332 | #define R7_OFF 14 |
---|
| 333 | #define R8_OFF 15 |
---|
| 334 | #define R9_OFF 16 |
---|
| 335 | #define R10_OFF 17 |
---|
| 336 | #define R11_OFF 18 |
---|
| 337 | #define R12_OFF 19 |
---|
| 338 | #define R13_OFF 20 |
---|
| 339 | #define R14_OFF 21 |
---|
| 340 | #define R15_OFF 22 |
---|
| 341 | #define R16_OFF 23 |
---|
| 342 | #define R17_OFF 24 |
---|
| 343 | #define R18_OFF 25 |
---|
| 344 | #define DP_OFF 26 |
---|
| 345 | #endif |
---|
| 346 | |
---|
[e7e016f] | 347 | #ifdef RTEMS_UNIXLIB_SETJMP |
---|
[ac7d5ef0] | 348 | #define RP_OFF 0 |
---|
| 349 | #define SP_OFF 1 |
---|
| 350 | #define R3_OFF 4 |
---|
| 351 | #define R4_OFF 5 |
---|
| 352 | #define R5_OFF 6 |
---|
| 353 | #define R6_OFF 7 |
---|
| 354 | #define R7_OFF 8 |
---|
| 355 | #define R8_OFF 9 |
---|
| 356 | #define R9_OFF 10 |
---|
| 357 | #define R10_OFF 11 |
---|
| 358 | #define R11_OFF 12 |
---|
| 359 | #define R12_OFF 13 |
---|
| 360 | #define R13_OFF 14 |
---|
| 361 | #define R14_OFF 15 |
---|
| 362 | #define R15_OFF 16 |
---|
| 363 | #define R16_OFF 17 |
---|
| 364 | #define R17_OFF 18 |
---|
| 365 | #define R18_OFF 19 |
---|
| 366 | #define DP_OFF 20 |
---|
| 367 | #endif |
---|
| 368 | #endif |
---|
| 369 | |
---|
[8044533] | 370 | #if defined(i386) |
---|
| 371 | |
---|
| 372 | #ifdef RTEMS_NEWLIB |
---|
| 373 | #error "Newlib not installed" |
---|
| 374 | #endif |
---|
| 375 | |
---|
| 376 | /* |
---|
| 377 | * For Linux 1.1 |
---|
| 378 | */ |
---|
| 379 | |
---|
| 380 | #ifdef RTEMS_UNIXLIB |
---|
| 381 | #define EBX_OFF 0 |
---|
| 382 | #define ESI_OFF 1 |
---|
| 383 | #define EDI_OFF 2 |
---|
| 384 | #define EBP_OFF 3 |
---|
| 385 | #define ESP_OFF 4 |
---|
| 386 | #define RET_OFF 5 |
---|
| 387 | #endif |
---|
| 388 | |
---|
| 389 | #endif |
---|
| 390 | |
---|
[ac7d5ef0] | 391 | #if defined(sparc) |
---|
| 392 | |
---|
| 393 | /* |
---|
| 394 | * Word indices within a jmp_buf structure |
---|
| 395 | */ |
---|
| 396 | |
---|
| 397 | #ifdef RTEMS_NEWLIB |
---|
| 398 | #define ADDR_ADJ_OFFSET -8 |
---|
| 399 | #define SP_OFF 0 |
---|
| 400 | #define RP_OFF 1 |
---|
| 401 | #define FP_OFF 2 |
---|
| 402 | #endif |
---|
| 403 | |
---|
| 404 | #ifdef RTEMS_UNIXLIB |
---|
| 405 | #define ADDR_ADJ_OFFSET 0 |
---|
| 406 | #define G0_OFF 0 |
---|
| 407 | #define SP_OFF 1 |
---|
| 408 | #define RP_OFF 2 |
---|
| 409 | #define FP_OFF 3 |
---|
| 410 | #define I7_OFF 4 |
---|
| 411 | #endif |
---|
| 412 | |
---|
| 413 | #endif |
---|
| 414 | |
---|
| 415 | /* |
---|
| 416 | * Contexts |
---|
| 417 | * |
---|
| 418 | * Generally there are 2 types of context to save. |
---|
| 419 | * 1. Interrupt registers to save |
---|
| 420 | * 2. Task level registers to save |
---|
| 421 | * |
---|
| 422 | * This means we have the following 3 context items: |
---|
| 423 | * 1. task level context stuff:: Context_Control |
---|
| 424 | * 2. floating point task stuff:: Context_Control_fp |
---|
| 425 | * 3. special interrupt level context :: Context_Control_interrupt |
---|
| 426 | * |
---|
| 427 | * On some processors, it is cost-effective to save only the callee |
---|
| 428 | * preserved registers during a task context switch. This means |
---|
| 429 | * that the ISR code needs to save those registers which do not |
---|
| 430 | * persist across function calls. It is not mandatory to make this |
---|
| 431 | * distinctions between the caller/callee saves registers for the |
---|
| 432 | * purpose of minimizing context saved during task switch and on interrupts. |
---|
| 433 | * If the cost of saving extra registers is minimal, simplicity is the |
---|
| 434 | * choice. Save the same context on interrupt entry as for tasks in |
---|
| 435 | * this case. |
---|
| 436 | * |
---|
| 437 | * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then |
---|
| 438 | * care should be used in designing the context area. |
---|
| 439 | * |
---|
| 440 | * On some CPUs with hardware floating point support, the Context_Control_fp |
---|
| 441 | * structure will not be used or it simply consist of an array of a |
---|
| 442 | * fixed number of bytes. This is done when the floating point context |
---|
| 443 | * is dumped by a "FP save context" type instruction and the format |
---|
| 444 | * is not really defined by the CPU. In this case, there is no need |
---|
| 445 | * to figure out the exact format -- only the size. Of course, although |
---|
| 446 | * this is enough information for RTEMS, it is probably not enough for |
---|
| 447 | * a debugger such as gdb. But that is another problem. |
---|
| 448 | */ |
---|
| 449 | |
---|
| 450 | typedef struct { |
---|
[637df35] | 451 | jmp_buf regs; |
---|
| 452 | sigset_t isr_level; |
---|
[ac7d5ef0] | 453 | } Context_Control; |
---|
| 454 | |
---|
| 455 | typedef struct { |
---|
| 456 | } Context_Control_fp; |
---|
| 457 | |
---|
| 458 | typedef struct { |
---|
| 459 | } CPU_Interrupt_frame; |
---|
| 460 | |
---|
| 461 | |
---|
| 462 | /* |
---|
| 463 | * The following table contains the information required to configure |
---|
| 464 | * the XXX processor specific parameters. |
---|
| 465 | * |
---|
| 466 | * NOTE: The interrupt_stack_size field is required if |
---|
| 467 | * CPU_ALLOCATE_INTERRUPT_STACK is defined as TRUE. |
---|
| 468 | * |
---|
| 469 | * The pretasking_hook, predriver_hook, and postdriver_hook, |
---|
| 470 | * and the do_zero_of_workspace fields are required on ALL CPUs. |
---|
| 471 | */ |
---|
| 472 | |
---|
| 473 | typedef struct { |
---|
| 474 | void (*pretasking_hook)( void ); |
---|
| 475 | void (*predriver_hook)( void ); |
---|
| 476 | void (*postdriver_hook)( void ); |
---|
| 477 | void (*idle_task)( void ); |
---|
| 478 | boolean do_zero_of_workspace; |
---|
| 479 | unsigned32 interrupt_stack_size; |
---|
| 480 | unsigned32 extra_system_initialization_stack; |
---|
| 481 | } rtems_cpu_table; |
---|
| 482 | |
---|
| 483 | /* |
---|
| 484 | * This variable is optional. It is used on CPUs on which it is difficult |
---|
| 485 | * to generate an "uninitialized" FP context. It is filled in by |
---|
| 486 | * _CPU_Initialize and copied into the task's FP context area during |
---|
| 487 | * _CPU_Context_Initialize. |
---|
| 488 | */ |
---|
| 489 | |
---|
| 490 | EXTERN Context_Control_fp _CPU_Null_fp_context; |
---|
| 491 | |
---|
| 492 | /* |
---|
| 493 | * On some CPUs, RTEMS supports a software managed interrupt stack. |
---|
| 494 | * This stack is allocated by the Interrupt Manager and the switch |
---|
| 495 | * is performed in _ISR_Handler. These variables contain pointers |
---|
| 496 | * to the lowest and highest addresses in the chunk of memory allocated |
---|
| 497 | * for the interrupt stack. Since it is unknown whether the stack |
---|
| 498 | * grows up or down (in general), this give the CPU dependent |
---|
| 499 | * code the option of picking the version it wants to use. |
---|
| 500 | * |
---|
| 501 | * NOTE: These two variables are required if the macro |
---|
| 502 | * CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE. |
---|
| 503 | */ |
---|
| 504 | |
---|
| 505 | EXTERN void *_CPU_Interrupt_stack_low; |
---|
| 506 | EXTERN void *_CPU_Interrupt_stack_high; |
---|
| 507 | |
---|
| 508 | /* |
---|
| 509 | * With some compilation systems, it is difficult if not impossible to |
---|
| 510 | * call a high-level language routine from assembly language. This |
---|
| 511 | * is especially true of commercial Ada compilers and name mangling |
---|
| 512 | * C++ ones. This variable can be optionally defined by the CPU porter |
---|
| 513 | * and contains the address of the routine _Thread_Dispatch. This |
---|
| 514 | * can make it easier to invoke that routine at the end of the interrupt |
---|
| 515 | * sequence (if a dispatch is necessary). |
---|
| 516 | */ |
---|
| 517 | |
---|
| 518 | EXTERN void (*_CPU_Thread_dispatch_pointer)(); |
---|
| 519 | |
---|
| 520 | /* |
---|
| 521 | * Nothing prevents the porter from declaring more CPU specific variables. |
---|
| 522 | */ |
---|
| 523 | |
---|
| 524 | /* XXX: if needed, put more variables here */ |
---|
| 525 | |
---|
| 526 | /* |
---|
| 527 | * The size of the floating point context area. On some CPUs this |
---|
| 528 | * will not be a "sizeof" because the format of the floating point |
---|
| 529 | * area is not defined -- only the size is. This is usually on |
---|
| 530 | * CPUs with a "floating point save context" instruction. |
---|
| 531 | */ |
---|
| 532 | |
---|
| 533 | #define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) |
---|
| 534 | |
---|
| 535 | /* |
---|
| 536 | * The size of a frame on the stack |
---|
| 537 | */ |
---|
| 538 | |
---|
| 539 | #if defined(hppa1_1) |
---|
| 540 | #define CPU_FRAME_SIZE (32 * 4) |
---|
| 541 | #elif defined(sparc) |
---|
| 542 | #define CPU_FRAME_SIZE (112) /* based on disassembled test code */ |
---|
[8044533] | 543 | #elif defined(i386) |
---|
| 544 | #define CPU_FRAME_SIZE (24) /* return address, sp, and bp pushed plus fudge */ |
---|
[ac7d5ef0] | 545 | #else |
---|
| 546 | #error "Unknown CPU!!!" |
---|
| 547 | #endif |
---|
| 548 | |
---|
| 549 | /* |
---|
| 550 | * Amount of extra stack (above minimum stack size) required by |
---|
| 551 | * system initialization thread. Remember that in a multiprocessor |
---|
| 552 | * system the system intialization thread becomes the MP server thread. |
---|
| 553 | */ |
---|
| 554 | |
---|
| 555 | #define CPU_SYSTEM_INITIALIZATION_THREAD_EXTRA_STACK 0 |
---|
| 556 | |
---|
| 557 | /* |
---|
| 558 | * This defines the number of entries in the ISR_Vector_table managed |
---|
| 559 | * by RTEMS. |
---|
| 560 | */ |
---|
| 561 | |
---|
| 562 | #define CPU_INTERRUPT_NUMBER_OF_VECTORS 64 |
---|
| 563 | |
---|
| 564 | /* |
---|
| 565 | * Should be large enough to run all RTEMS tests. This insures |
---|
| 566 | * that a "reasonable" small application should not have any problems. |
---|
| 567 | */ |
---|
| 568 | |
---|
| 569 | #define CPU_STACK_MINIMUM_SIZE (16 * 1024) |
---|
| 570 | |
---|
| 571 | /* |
---|
| 572 | * CPU's worst alignment requirement for data types on a byte boundary. This |
---|
| 573 | * alignment does not take into account the requirements for the stack. |
---|
| 574 | */ |
---|
| 575 | |
---|
| 576 | #define CPU_ALIGNMENT 8 |
---|
| 577 | |
---|
| 578 | /* |
---|
| 579 | * This number corresponds to the byte alignment requirement for the |
---|
| 580 | * heap handler. This alignment requirement may be stricter than that |
---|
| 581 | * for the data types alignment specified by CPU_ALIGNMENT. It is |
---|
| 582 | * common for the heap to follow the same alignment requirement as |
---|
| 583 | * CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict enough for the heap, |
---|
| 584 | * then this should be set to CPU_ALIGNMENT. |
---|
| 585 | * |
---|
| 586 | * NOTE: This does not have to be a power of 2. It does have to |
---|
| 587 | * be greater or equal to than CPU_ALIGNMENT. |
---|
| 588 | */ |
---|
| 589 | |
---|
| 590 | #define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT |
---|
| 591 | |
---|
| 592 | /* |
---|
| 593 | * This number corresponds to the byte alignment requirement for memory |
---|
| 594 | * buffers allocated by the partition manager. This alignment requirement |
---|
| 595 | * may be stricter than that for the data types alignment specified by |
---|
| 596 | * CPU_ALIGNMENT. It is common for the partition to follow the same |
---|
| 597 | * alignment requirement as CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict |
---|
| 598 | * enough for the partition, then this should be set to CPU_ALIGNMENT. |
---|
| 599 | * |
---|
| 600 | * NOTE: This does not have to be a power of 2. It does have to |
---|
| 601 | * be greater or equal to than CPU_ALIGNMENT. |
---|
| 602 | */ |
---|
| 603 | |
---|
| 604 | #define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT |
---|
| 605 | |
---|
| 606 | /* |
---|
| 607 | * This number corresponds to the byte alignment requirement for the |
---|
| 608 | * stack. This alignment requirement may be stricter than that for the |
---|
| 609 | * data types alignment specified by CPU_ALIGNMENT. If the CPU_ALIGNMENT |
---|
| 610 | * is strict enough for the stack, then this should be set to 0. |
---|
| 611 | * |
---|
| 612 | * NOTE: This must be a power of 2 either 0 or greater than CPU_ALIGNMENT. |
---|
| 613 | */ |
---|
| 614 | |
---|
| 615 | #define CPU_STACK_ALIGNMENT 64 |
---|
| 616 | |
---|
| 617 | /* ISR handler macros */ |
---|
| 618 | |
---|
| 619 | /* |
---|
| 620 | * Disable all interrupts for an RTEMS critical section. The previous |
---|
| 621 | * level is returned in _level. |
---|
| 622 | */ |
---|
| 623 | |
---|
[637df35] | 624 | extern unsigned32 _CPU_ISR_Disable_support(void); |
---|
| 625 | |
---|
[ac7d5ef0] | 626 | #define _CPU_ISR_Disable( _level ) \ |
---|
| 627 | do { \ |
---|
[637df35] | 628 | (_level) = _CPU_ISR_Disable_support(); \ |
---|
[ac7d5ef0] | 629 | } while ( 0 ) |
---|
| 630 | |
---|
| 631 | /* |
---|
| 632 | * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). |
---|
| 633 | * This indicates the end of an RTEMS critical section. The parameter |
---|
| 634 | * _level is not modified. |
---|
| 635 | */ |
---|
| 636 | |
---|
[637df35] | 637 | void _CPU_ISR_Enable(unsigned32 level); |
---|
[ac7d5ef0] | 638 | |
---|
| 639 | /* |
---|
| 640 | * This temporarily restores the interrupt to _level before immediately |
---|
| 641 | * disabling them again. This is used to divide long RTEMS critical |
---|
| 642 | * sections into two or more parts. The parameter _level is not |
---|
| 643 | * modified. |
---|
| 644 | */ |
---|
| 645 | |
---|
| 646 | #define _CPU_ISR_Flash( _level ) \ |
---|
| 647 | do { \ |
---|
| 648 | register _ignored = 0; \ |
---|
| 649 | _CPU_ISR_Enable( (_level) ); \ |
---|
| 650 | _CPU_ISR_Disable( _ignored ); \ |
---|
| 651 | } while ( 0 ) |
---|
| 652 | |
---|
| 653 | /* |
---|
| 654 | * Map interrupt level in task mode onto the hardware that the CPU |
---|
| 655 | * actually provides. Currently, interrupt levels which do not |
---|
| 656 | * map onto the CPU in a generic fashion are undefined. Someday, |
---|
| 657 | * it would be nice if these were "mapped" by the application |
---|
| 658 | * via a callout. For example, m68k has 8 levels 0 - 7, levels |
---|
| 659 | * 8 - 255 would be available for bsp/application specific meaning. |
---|
| 660 | * This could be used to manage a programmable interrupt controller |
---|
| 661 | * via the rtems_task_mode directive. |
---|
| 662 | */ |
---|
| 663 | |
---|
| 664 | #define _CPU_ISR_Set_level( new_level ) \ |
---|
| 665 | { \ |
---|
[637df35] | 666 | if ( new_level == 0 ) _CPU_ISR_Enable( 0 ); \ |
---|
| 667 | else _CPU_ISR_Enable( 1 ); \ |
---|
[ac7d5ef0] | 668 | } |
---|
| 669 | |
---|
[3a4ae6c] | 670 | unsigned32 _CPU_ISR_Get_level( void ); |
---|
| 671 | |
---|
[ac7d5ef0] | 672 | /* end of ISR handler macros */ |
---|
| 673 | |
---|
| 674 | /* Context handler macros */ |
---|
| 675 | |
---|
| 676 | /* |
---|
| 677 | * This routine is responsible for somehow restarting the currently |
---|
| 678 | * executing task. If you are lucky, then all that is necessary |
---|
| 679 | * is restoring the context. Otherwise, there will need to be |
---|
| 680 | * a special assembly routine which does something special in this |
---|
| 681 | * case. Context_Restore should work most of the time. It will |
---|
| 682 | * not work if restarting self conflicts with the stack frame |
---|
| 683 | * assumptions of restoring a context. |
---|
| 684 | */ |
---|
| 685 | |
---|
| 686 | #define _CPU_Context_Restart_self( _the_context ) \ |
---|
| 687 | _CPU_Context_restore( (_the_context) ); |
---|
| 688 | |
---|
| 689 | /* |
---|
| 690 | * The purpose of this macro is to allow the initial pointer into |
---|
| 691 | * a floating point context area (used to save the floating point |
---|
| 692 | * context) to be at an arbitrary place in the floating point |
---|
| 693 | * context area. |
---|
| 694 | * |
---|
| 695 | * This is necessary because some FP units are designed to have |
---|
| 696 | * their context saved as a stack which grows into lower addresses. |
---|
| 697 | * Other FP units can be saved by simply moving registers into offsets |
---|
| 698 | * from the base of the context area. Finally some FP units provide |
---|
| 699 | * a "dump context" instruction which could fill in from high to low |
---|
| 700 | * or low to high based on the whim of the CPU designers. |
---|
| 701 | */ |
---|
| 702 | |
---|
| 703 | #define _CPU_Context_Fp_start( _base, _offset ) \ |
---|
| 704 | ( (void *) (_base) + (_offset) ) |
---|
| 705 | |
---|
| 706 | /* |
---|
| 707 | * This routine initializes the FP context area passed to it to. |
---|
| 708 | * There are a few standard ways in which to initialize the |
---|
| 709 | * floating point context. The code included for this macro assumes |
---|
| 710 | * that this is a CPU in which a "initial" FP context was saved into |
---|
| 711 | * _CPU_Null_fp_context and it simply copies it to the destination |
---|
| 712 | * context passed to it. |
---|
| 713 | * |
---|
| 714 | * Other models include (1) not doing anything, and (2) putting |
---|
| 715 | * a "null FP status word" in the correct place in the FP context. |
---|
| 716 | */ |
---|
| 717 | |
---|
| 718 | #define _CPU_Context_Initialize_fp( _destination ) \ |
---|
| 719 | { \ |
---|
| 720 | *((Context_Control_fp *) *((void **) _destination)) = _CPU_Null_fp_context; \ |
---|
| 721 | } |
---|
| 722 | |
---|
| 723 | #define _CPU_Context_save_fp( _fp_context ) \ |
---|
| 724 | _CPU_Save_float_context( *(Context_Control_fp **)(_fp_context)) |
---|
| 725 | |
---|
| 726 | #define _CPU_Context_restore_fp( _fp_context ) \ |
---|
| 727 | _CPU_Restore_float_context( *(Context_Control_fp **)(_fp_context)) |
---|
| 728 | |
---|
| 729 | extern void _CPU_Context_Initialize( |
---|
| 730 | Context_Control *_the_context, |
---|
| 731 | unsigned32 *_stack_base, |
---|
| 732 | unsigned32 _size, |
---|
| 733 | unsigned32 _new_level, |
---|
[88d594a] | 734 | void *_entry_point |
---|
[ac7d5ef0] | 735 | ); |
---|
| 736 | |
---|
| 737 | /* end of Context handler macros */ |
---|
| 738 | |
---|
| 739 | /* Fatal Error manager macros */ |
---|
| 740 | |
---|
| 741 | /* |
---|
| 742 | * This routine copies _error into a known place -- typically a stack |
---|
| 743 | * location or a register, optionally disables interrupts, and |
---|
| 744 | * halts/stops the CPU. |
---|
| 745 | */ |
---|
| 746 | |
---|
| 747 | #define _CPU_Fatal_halt( _error ) \ |
---|
| 748 | _CPU_Fatal_error( _error ) |
---|
| 749 | |
---|
| 750 | /* end of Fatal Error manager macros */ |
---|
| 751 | |
---|
| 752 | /* Bitfield handler macros */ |
---|
| 753 | |
---|
| 754 | /* |
---|
| 755 | * This routine sets _output to the bit number of the first bit |
---|
| 756 | * set in _value. _value is of CPU dependent type Priority_Bit_map_control. |
---|
| 757 | * This type may be either 16 or 32 bits wide although only the 16 |
---|
| 758 | * least significant bits will be used. |
---|
| 759 | * |
---|
| 760 | * There are a number of variables in using a "find first bit" type |
---|
| 761 | * instruction. |
---|
| 762 | * |
---|
| 763 | * (1) What happens when run on a value of zero? |
---|
| 764 | * (2) Bits may be numbered from MSB to LSB or vice-versa. |
---|
| 765 | * (3) The numbering may be zero or one based. |
---|
| 766 | * (4) The "find first bit" instruction may search from MSB or LSB. |
---|
| 767 | * |
---|
| 768 | * RTEMS guarantees that (1) will never happen so it is not a concern. |
---|
| 769 | * (2),(3), (4) are handled by the macros _CPU_Priority_mask() and |
---|
| 770 | * _CPU_Priority_Bits_index(). These three form a set of routines |
---|
| 771 | * which must logically operate together. Bits in the _value are |
---|
| 772 | * set and cleared based on masks built by _CPU_Priority_mask(). |
---|
| 773 | * The basic major and minor values calculated by _Priority_Major() |
---|
| 774 | * and _Priority_Minor() are "massaged" by _CPU_Priority_Bits_index() |
---|
| 775 | * to properly range between the values returned by the "find first bit" |
---|
| 776 | * instruction. This makes it possible for _Priority_Get_highest() to |
---|
| 777 | * calculate the major and directly index into the minor table. |
---|
| 778 | * This mapping is necessary to ensure that 0 (a high priority major/minor) |
---|
| 779 | * is the first bit found. |
---|
| 780 | * |
---|
| 781 | * This entire "find first bit" and mapping process depends heavily |
---|
| 782 | * on the manner in which a priority is broken into a major and minor |
---|
| 783 | * components with the major being the 4 MSB of a priority and minor |
---|
| 784 | * the 4 LSB. Thus (0 << 4) + 0 corresponds to priority 0 -- the highest |
---|
| 785 | * priority. And (15 << 4) + 14 corresponds to priority 254 -- the next |
---|
| 786 | * to the lowest priority. |
---|
| 787 | * |
---|
| 788 | * If your CPU does not have a "find first bit" instruction, then |
---|
| 789 | * there are ways to make do without it. Here are a handful of ways |
---|
| 790 | * to implement this in software: |
---|
| 791 | * |
---|
| 792 | * - a series of 16 bit test instructions |
---|
| 793 | * - a "binary search using if's" |
---|
| 794 | * - _number = 0 |
---|
| 795 | * if _value > 0x00ff |
---|
| 796 | * _value >>=8 |
---|
| 797 | * _number = 8; |
---|
| 798 | * |
---|
| 799 | * if _value > 0x0000f |
---|
| 800 | * _value >=8 |
---|
| 801 | * _number += 4 |
---|
| 802 | * |
---|
| 803 | * _number += bit_set_table[ _value ] |
---|
| 804 | * |
---|
| 805 | * where bit_set_table[ 16 ] has values which indicate the first |
---|
| 806 | * bit set |
---|
| 807 | */ |
---|
| 808 | |
---|
| 809 | #define _CPU_Bitfield_Find_first_bit( _value, _output ) \ |
---|
| 810 | _output = _CPU_ffs( _value ) |
---|
| 811 | |
---|
| 812 | /* end of Bitfield handler macros */ |
---|
| 813 | |
---|
| 814 | /* |
---|
| 815 | * This routine builds the mask which corresponds to the bit fields |
---|
| 816 | * as searched by _CPU_Bitfield_Find_first_bit(). See the discussion |
---|
| 817 | * for that routine. |
---|
| 818 | */ |
---|
| 819 | |
---|
| 820 | #define _CPU_Priority_Mask( _bit_number ) \ |
---|
| 821 | ( 1 << (_bit_number) ) |
---|
| 822 | |
---|
| 823 | /* |
---|
| 824 | * This routine translates the bit numbers returned by |
---|
| 825 | * _CPU_Bitfield_Find_first_bit() into something suitable for use as |
---|
| 826 | * a major or minor component of a priority. See the discussion |
---|
| 827 | * for that routine. |
---|
| 828 | */ |
---|
| 829 | |
---|
| 830 | #define _CPU_Priority_Bits_index( _priority ) \ |
---|
| 831 | (_priority) |
---|
| 832 | |
---|
| 833 | /* end of Priority handler macros */ |
---|
| 834 | |
---|
| 835 | /* functions */ |
---|
| 836 | |
---|
| 837 | /* |
---|
| 838 | * _CPU_Initialize |
---|
| 839 | * |
---|
| 840 | * This routine performs CPU dependent initialization. |
---|
| 841 | */ |
---|
| 842 | |
---|
| 843 | void _CPU_Initialize( |
---|
| 844 | rtems_cpu_table *cpu_table, |
---|
| 845 | void (*thread_dispatch) |
---|
| 846 | ); |
---|
| 847 | |
---|
[637df35] | 848 | /* |
---|
| 849 | * _CPU_ISR_install_raw_handler |
---|
| 850 | * |
---|
| 851 | * This routine installs a "raw" interrupt handler directly into the |
---|
| 852 | * processor's vector table. |
---|
| 853 | */ |
---|
| 854 | |
---|
| 855 | void _CPU_ISR_install_raw_handler( |
---|
| 856 | unsigned32 vector, |
---|
| 857 | proc_ptr new_handler, |
---|
| 858 | proc_ptr *old_handler |
---|
| 859 | ); |
---|
| 860 | |
---|
[ac7d5ef0] | 861 | /* |
---|
| 862 | * _CPU_ISR_install_vector |
---|
| 863 | * |
---|
| 864 | * This routine installs an interrupt vector. |
---|
| 865 | */ |
---|
| 866 | |
---|
| 867 | void _CPU_ISR_install_vector( |
---|
| 868 | unsigned32 vector, |
---|
| 869 | proc_ptr new_handler, |
---|
| 870 | proc_ptr *old_handler |
---|
| 871 | ); |
---|
| 872 | |
---|
| 873 | /* |
---|
| 874 | * _CPU_Install_interrupt_stack |
---|
| 875 | * |
---|
| 876 | * This routine installs the hardware interrupt stack pointer. |
---|
| 877 | * |
---|
| 878 | * NOTE: It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK |
---|
| 879 | * is TRUE. |
---|
| 880 | */ |
---|
| 881 | |
---|
| 882 | void _CPU_Install_interrupt_stack( void ); |
---|
| 883 | |
---|
| 884 | /* |
---|
| 885 | * _CPU_Internal_threads_Idle_thread_body |
---|
| 886 | * |
---|
| 887 | * This routine is the CPU dependent IDLE thread body. |
---|
| 888 | * |
---|
| 889 | * NOTE: It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY |
---|
| 890 | * is TRUE. |
---|
| 891 | */ |
---|
| 892 | |
---|
| 893 | void _CPU_Internal_threads_Idle_thread_body( void ); |
---|
| 894 | |
---|
| 895 | /* |
---|
| 896 | * _CPU_Context_switch |
---|
| 897 | * |
---|
| 898 | * This routine switches from the run context to the heir context. |
---|
| 899 | */ |
---|
| 900 | |
---|
| 901 | void _CPU_Context_switch( |
---|
| 902 | Context_Control *run, |
---|
| 903 | Context_Control *heir |
---|
| 904 | ); |
---|
| 905 | |
---|
| 906 | /* |
---|
| 907 | * _CPU_Context_restore |
---|
| 908 | * |
---|
| 909 | * This routine is generallu used only to restart self in an |
---|
| 910 | * efficient manner. It may simply be a label in _CPU_Context_switch. |
---|
| 911 | * |
---|
| 912 | * NOTE: May be unnecessary to reload some registers. |
---|
| 913 | */ |
---|
| 914 | |
---|
| 915 | void _CPU_Context_restore( |
---|
| 916 | Context_Control *new_context |
---|
| 917 | ); |
---|
| 918 | |
---|
| 919 | /* |
---|
| 920 | * _CPU_Save_float_context |
---|
| 921 | * |
---|
| 922 | * This routine saves the floating point context passed to it. |
---|
| 923 | */ |
---|
| 924 | |
---|
| 925 | void _CPU_Save_float_context( |
---|
| 926 | Context_Control_fp *fp_context_ptr |
---|
| 927 | ); |
---|
| 928 | |
---|
| 929 | /* |
---|
| 930 | * _CPU_Restore_float_context |
---|
| 931 | * |
---|
| 932 | * This routine restores the floating point context passed to it. |
---|
| 933 | */ |
---|
| 934 | |
---|
| 935 | void _CPU_Restore_float_context( |
---|
| 936 | Context_Control_fp *fp_context_ptr |
---|
| 937 | ); |
---|
| 938 | |
---|
| 939 | |
---|
| 940 | void _CPU_ISR_Set_signal_level( |
---|
| 941 | unsigned32 level |
---|
| 942 | ); |
---|
| 943 | |
---|
| 944 | void _CPU_Fatal_error( |
---|
| 945 | unsigned32 _error |
---|
| 946 | ); |
---|
| 947 | |
---|
| 948 | int _CPU_ffs( |
---|
| 949 | unsigned32 _value |
---|
| 950 | ); |
---|
| 951 | |
---|
| 952 | /* The following routine swaps the endian format of an unsigned int. |
---|
| 953 | * It must be static because it is referenced indirectly. |
---|
| 954 | * |
---|
| 955 | * This version will work on any processor, but if there is a better |
---|
| 956 | * way for your CPU PLEASE use it. The most common way to do this is to: |
---|
| 957 | * |
---|
| 958 | * swap least significant two bytes with 16-bit rotate |
---|
| 959 | * swap upper and lower 16-bits |
---|
| 960 | * swap most significant two bytes with 16-bit rotate |
---|
| 961 | * |
---|
| 962 | * Some CPUs have special instructions which swap a 32-bit quantity in |
---|
| 963 | * a single instruction (e.g. i486). It is probably best to avoid |
---|
| 964 | * an "endian swapping control bit" in the CPU. One good reason is |
---|
| 965 | * that interrupts would probably have to be disabled to insure that |
---|
| 966 | * an interrupt does not try to access the same "chunk" with the wrong |
---|
| 967 | * endian. Another good reason is that on some CPUs, the endian bit |
---|
| 968 | * endianness for ALL fetches -- both code and data -- so the code |
---|
| 969 | * will be fetched incorrectly. |
---|
| 970 | */ |
---|
| 971 | |
---|
| 972 | static inline unsigned int CPU_swap_u32( |
---|
| 973 | unsigned int value |
---|
| 974 | ) |
---|
| 975 | { |
---|
| 976 | unsigned32 byte1, byte2, byte3, byte4, swapped; |
---|
| 977 | |
---|
| 978 | byte4 = (value >> 24) & 0xff; |
---|
| 979 | byte3 = (value >> 16) & 0xff; |
---|
| 980 | byte2 = (value >> 8) & 0xff; |
---|
| 981 | byte1 = value & 0xff; |
---|
| 982 | |
---|
| 983 | swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; |
---|
| 984 | return( swapped ); |
---|
| 985 | } |
---|
| 986 | |
---|
| 987 | #ifdef __cplusplus |
---|
| 988 | } |
---|
| 989 | #endif |
---|
| 990 | |
---|
| 991 | #endif |
---|