[ac7d5ef0] | 1 | /* cpu.h |
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| 2 | * |
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| 3 | * This include file contains information pertaining to the HP |
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| 4 | * PA-RISC processor (Level 1.1). |
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| 5 | * |
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| 6 | * COPYRIGHT (c) 1994 by Division Incorporated |
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| 7 | * |
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| 8 | * To anyone who acknowledges that this file is provided "AS IS" |
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| 9 | * without any express or implied warranty: |
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| 10 | * permission to use, copy, modify, and distribute this file |
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| 11 | * for any purpose is hereby granted without fee, provided that |
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| 12 | * the above copyright notice and this notice appears in all |
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| 13 | * copies, and that the name of Division Incorporated not be |
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| 14 | * used in advertising or publicity pertaining to distribution |
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| 15 | * of the software without specific, written prior permission. |
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| 16 | * Division Incorporated makes no representations about the |
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| 17 | * suitability of this software for any purpose. |
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| 18 | * |
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| 19 | * $Id$ |
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| 20 | */ |
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| 21 | |
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| 22 | #ifndef __CPU_h |
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| 23 | #define __CPU_h |
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| 24 | |
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| 25 | #ifdef __cplusplus |
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| 26 | extern "C" { |
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| 27 | #endif |
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| 28 | |
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[5e9b32b] | 29 | #include <rtems/score/unix.h> |
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[88d594a] | 30 | #ifndef ASM |
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[5e9b32b] | 31 | #include <rtems/score/unixtypes.h> |
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[88d594a] | 32 | #endif |
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[ac7d5ef0] | 33 | |
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[37f4c2d] | 34 | #include <rtems/score/unixsize.h> |
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| 35 | |
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[637df35] | 36 | #if defined(solaris2) |
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| 37 | #undef _POSIX_C_SOURCE |
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| 38 | #define _POSIX_C_SOURCE 3 |
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| 39 | #undef __STRICT_ANSI__ |
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| 40 | #define __STRICT_ANSI__ |
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| 41 | #endif |
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| 42 | |
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[217d2e7] | 43 | #if defined(linux) |
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| 44 | #define MALLOC_0_RETURNS_NULL |
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| 45 | #endif |
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| 46 | |
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[ac7d5ef0] | 47 | /* conditional compilation parameters */ |
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| 48 | |
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| 49 | /* |
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| 50 | * Should the calls to _Thread_Enable_dispatch be inlined? |
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| 51 | * |
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| 52 | * If TRUE, then they are inlined. |
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| 53 | * If FALSE, then a subroutine call is made. |
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| 54 | * |
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| 55 | * Basically this is an example of the classic trade-off of size |
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| 56 | * versus speed. Inlining the call (TRUE) typically increases the |
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| 57 | * size of RTEMS while speeding up the enabling of dispatching. |
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| 58 | * [NOTE: In general, the _Thread_Dispatch_disable_level will |
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| 59 | * only be 0 or 1 unless you are in an interrupt handler and that |
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| 60 | * interrupt handler invokes the executive.] When not inlined |
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| 61 | * something calls _Thread_Enable_dispatch which in turns calls |
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| 62 | * _Thread_Dispatch. If the enable dispatch is inlined, then |
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| 63 | * one subroutine call is avoided entirely.] |
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| 64 | */ |
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| 65 | |
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| 66 | #define CPU_INLINE_ENABLE_DISPATCH FALSE |
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| 67 | |
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| 68 | /* |
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| 69 | * Should the body of the search loops in _Thread_queue_Enqueue_priority |
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| 70 | * be unrolled one time? In unrolled each iteration of the loop examines |
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| 71 | * two "nodes" on the chain being searched. Otherwise, only one node |
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| 72 | * is examined per iteration. |
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| 73 | * |
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| 74 | * If TRUE, then the loops are unrolled. |
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| 75 | * If FALSE, then the loops are not unrolled. |
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| 76 | * |
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| 77 | * The primary factor in making this decision is the cost of disabling |
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| 78 | * and enabling interrupts (_ISR_Flash) versus the cost of rest of the |
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| 79 | * body of the loop. On some CPUs, the flash is more expensive than |
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| 80 | * one iteration of the loop body. In this case, it might be desirable |
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| 81 | * to unroll the loop. It is important to note that on some CPUs, this |
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| 82 | * code is the longest interrupt disable period in RTEMS. So it is |
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| 83 | * necessary to strike a balance when setting this parameter. |
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| 84 | */ |
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| 85 | |
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| 86 | #define CPU_UNROLL_ENQUEUE_PRIORITY TRUE |
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| 87 | |
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| 88 | /* |
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| 89 | * Does RTEMS manage a dedicated interrupt stack in software? |
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| 90 | * |
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| 91 | * If TRUE, then a stack is allocated in _Interrupt_Manager_initialization. |
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| 92 | * If FALSE, nothing is done. |
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| 93 | * |
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| 94 | * If the CPU supports a dedicated interrupt stack in hardware, |
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| 95 | * then it is generally the responsibility of the BSP to allocate it |
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| 96 | * and set it up. |
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| 97 | * |
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| 98 | * If the CPU does not support a dedicated interrupt stack, then |
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| 99 | * the porter has two options: (1) execute interrupts on the |
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| 100 | * stack of the interrupted task, and (2) have RTEMS manage a dedicated |
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| 101 | * interrupt stack. |
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| 102 | * |
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| 103 | * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. |
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| 104 | * |
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| 105 | * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and |
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| 106 | * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is |
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| 107 | * possible that both are FALSE for a particular CPU. Although it |
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| 108 | * is unclear what that would imply about the interrupt processing |
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| 109 | * procedure on that CPU. |
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| 110 | */ |
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| 111 | |
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| 112 | #define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE |
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| 113 | |
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| 114 | /* |
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| 115 | * Does this CPU have hardware support for a dedicated interrupt stack? |
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| 116 | * |
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| 117 | * If TRUE, then it must be installed during initialization. |
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| 118 | * If FALSE, then no installation is performed. |
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| 119 | * |
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| 120 | * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. |
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| 121 | * |
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| 122 | * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and |
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| 123 | * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is |
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| 124 | * possible that both are FALSE for a particular CPU. Although it |
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| 125 | * is unclear what that would imply about the interrupt processing |
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| 126 | * procedure on that CPU. |
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| 127 | */ |
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| 128 | |
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| 129 | #define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE |
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| 130 | |
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| 131 | /* |
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| 132 | * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager? |
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| 133 | * |
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| 134 | * If TRUE, then the memory is allocated during initialization. |
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| 135 | * If FALSE, then the memory is allocated during initialization. |
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| 136 | * |
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| 137 | * This should be TRUE if CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE |
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| 138 | * or CPU_INSTALL_HARDWARE_INTERRUPT_STACK is TRUE. |
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| 139 | */ |
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| 140 | |
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| 141 | #define CPU_ALLOCATE_INTERRUPT_STACK FALSE |
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| 142 | |
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| 143 | /* |
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| 144 | * Does the CPU have hardware floating point? |
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| 145 | * |
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| 146 | * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported. |
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| 147 | * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored. |
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| 148 | * |
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| 149 | * If there is a FP coprocessor such as the i387 or mc68881, then |
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| 150 | * the answer is TRUE. |
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| 151 | * |
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| 152 | * The macro name "NO_CPU_HAS_FPU" should be made CPU specific. |
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| 153 | * It indicates whether or not this CPU model has FP support. For |
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| 154 | * example, it would be possible to have an i386_nofp CPU model |
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| 155 | * which set this to false to indicate that you have an i386 without |
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| 156 | * an i387 and wish to leave floating point support out of RTEMS. |
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| 157 | */ |
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| 158 | |
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| 159 | #define CPU_HARDWARE_FP TRUE |
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| 160 | |
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| 161 | /* |
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| 162 | * Are all tasks RTEMS_FLOATING_POINT tasks implicitly? |
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| 163 | * |
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| 164 | * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed. |
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| 165 | * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed. |
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| 166 | * |
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| 167 | * So far, the only CPU in which this option has been used is the |
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| 168 | * HP PA-RISC. The HP C compiler and gcc both implicitly use the |
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| 169 | * floating point registers to perform integer multiplies. If |
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| 170 | * a function which you would not think utilize the FP unit DOES, |
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| 171 | * then one can not easily predict which tasks will use the FP hardware. |
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| 172 | * In this case, this option should be TRUE. |
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| 173 | * |
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| 174 | * If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well. |
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| 175 | */ |
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| 176 | |
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| 177 | #define CPU_ALL_TASKS_ARE_FP FALSE |
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| 178 | |
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| 179 | /* |
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| 180 | * Should the IDLE task have a floating point context? |
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| 181 | * |
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| 182 | * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task |
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| 183 | * and it has a floating point context which is switched in and out. |
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| 184 | * If FALSE, then the IDLE task does not have a floating point context. |
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| 185 | * |
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| 186 | * Setting this to TRUE negatively impacts the time required to preempt |
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| 187 | * the IDLE task from an interrupt because the floating point context |
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| 188 | * must be saved as part of the preemption. |
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| 189 | */ |
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| 190 | |
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| 191 | #define CPU_IDLE_TASK_IS_FP FALSE |
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| 192 | |
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| 193 | /* |
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| 194 | * Should the saving of the floating point registers be deferred |
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| 195 | * until a context switch is made to another different floating point |
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| 196 | * task? |
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| 197 | * |
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| 198 | * If TRUE, then the floating point context will not be stored until |
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| 199 | * necessary. It will remain in the floating point registers and not |
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| 200 | * disturned until another floating point task is switched to. |
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| 201 | * |
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| 202 | * If FALSE, then the floating point context is saved when a floating |
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| 203 | * point task is switched out and restored when the next floating point |
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| 204 | * task is restored. The state of the floating point registers between |
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| 205 | * those two operations is not specified. |
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| 206 | * |
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| 207 | * If the floating point context does NOT have to be saved as part of |
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| 208 | * interrupt dispatching, then it should be safe to set this to TRUE. |
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| 209 | * |
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| 210 | * Setting this flag to TRUE results in using a different algorithm |
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| 211 | * for deciding when to save and restore the floating point context. |
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| 212 | * The deferred FP switch algorithm minimizes the number of times |
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| 213 | * the FP context is saved and restored. The FP context is not saved |
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| 214 | * until a context switch is made to another, different FP task. |
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| 215 | * Thus in a system with only one FP task, the FP context will never |
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| 216 | * be saved or restored. |
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| 217 | */ |
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| 218 | |
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| 219 | #define CPU_USE_DEFERRED_FP_SWITCH TRUE |
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| 220 | |
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| 221 | /* |
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| 222 | * Does this port provide a CPU dependent IDLE task implementation? |
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| 223 | * |
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[75f09e5] | 224 | * If TRUE, then the routine _CPU_Thread_Idle_body |
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[ac7d5ef0] | 225 | * must be provided and is the default IDLE thread body instead of |
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[75f09e5] | 226 | * _CPU_Thread_Idle_body. |
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[ac7d5ef0] | 227 | * |
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| 228 | * If FALSE, then use the generic IDLE thread body if the BSP does |
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| 229 | * not provide one. |
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| 230 | * |
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| 231 | * This is intended to allow for supporting processors which have |
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| 232 | * a low power or idle mode. When the IDLE thread is executed, then |
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| 233 | * the CPU can be powered down. |
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| 234 | * |
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| 235 | * The order of precedence for selecting the IDLE thread body is: |
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| 236 | * |
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| 237 | * 1. BSP provided |
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| 238 | * 2. CPU dependent (if provided) |
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| 239 | * 3. generic (if no BSP and no CPU dependent) |
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| 240 | */ |
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| 241 | |
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| 242 | #define CPU_PROVIDES_IDLE_THREAD_BODY TRUE |
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| 243 | |
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| 244 | /* |
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| 245 | * Does the stack grow up (toward higher addresses) or down |
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| 246 | * (toward lower addresses)? |
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| 247 | * |
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| 248 | * If TRUE, then the grows upward. |
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| 249 | * If FALSE, then the grows toward smaller addresses. |
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| 250 | */ |
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| 251 | |
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| 252 | #if defined(hppa1_1) |
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| 253 | #define CPU_STACK_GROWS_UP TRUE |
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[8044533] | 254 | #elif defined(sparc) || defined(i386) |
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[ac7d5ef0] | 255 | #define CPU_STACK_GROWS_UP FALSE |
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| 256 | #else |
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| 257 | #error "unknown CPU!!" |
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| 258 | #endif |
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| 259 | |
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| 260 | |
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| 261 | /* |
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| 262 | * The following is the variable attribute used to force alignment |
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| 263 | * of critical RTEMS structures. On some processors it may make |
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| 264 | * sense to have these aligned on tighter boundaries than |
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| 265 | * the minimum requirements of the compiler in order to have as |
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| 266 | * much of the critical data area as possible in a cache line. |
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| 267 | * |
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| 268 | * The placement of this macro in the declaration of the variables |
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| 269 | * is based on the syntactically requirements of the GNU C |
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| 270 | * "__attribute__" extension. For example with GNU C, use |
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| 271 | * the following to force a structures to a 32 byte boundary. |
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| 272 | * |
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| 273 | * __attribute__ ((aligned (32))) |
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| 274 | * |
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| 275 | * NOTE: Currently only the Priority Bit Map table uses this feature. |
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| 276 | * To benefit from using this, the data must be heavily |
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| 277 | * used so it will stay in the cache and used frequently enough |
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| 278 | * in the executive to justify turning this on. |
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| 279 | */ |
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| 280 | |
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[c64e4ed4] | 281 | #ifdef __GNUC__ |
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[ac7d5ef0] | 282 | #define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned (32))) |
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[c64e4ed4] | 283 | #else |
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| 284 | #define CPU_STRUCTURE_ALIGNMENT |
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| 285 | #endif |
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[ac7d5ef0] | 286 | |
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| 287 | /* |
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| 288 | * The following defines the number of bits actually used in the |
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| 289 | * interrupt field of the task mode. How those bits map to the |
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| 290 | * CPU interrupt levels is defined by the routine _CPU_ISR_Set_level(). |
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| 291 | */ |
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| 292 | |
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| 293 | #define CPU_MODES_INTERRUPT_MASK 0x00000001 |
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| 294 | |
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| 295 | #define CPU_NAME "UNIX" |
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| 296 | |
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| 297 | /* |
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| 298 | * Processor defined structures |
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| 299 | * |
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| 300 | * Examples structures include the descriptor tables from the i386 |
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| 301 | * and the processor control structure on the i960ca. |
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| 302 | */ |
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| 303 | |
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| 304 | /* may need to put some structures here. */ |
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| 305 | |
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| 306 | #if defined(hppa1_1) |
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| 307 | /* |
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| 308 | * Word indices within a jmp_buf structure |
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| 309 | */ |
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| 310 | |
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[e7e016f] | 311 | #ifdef RTEMS_NEWLIB_SETJMP |
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[ac7d5ef0] | 312 | #define RP_OFF 6 |
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| 313 | #define SP_OFF 2 |
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| 314 | #define R3_OFF 10 |
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| 315 | #define R4_OFF 11 |
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| 316 | #define R5_OFF 12 |
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| 317 | #define R6_OFF 13 |
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| 318 | #define R7_OFF 14 |
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| 319 | #define R8_OFF 15 |
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| 320 | #define R9_OFF 16 |
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| 321 | #define R10_OFF 17 |
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| 322 | #define R11_OFF 18 |
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| 323 | #define R12_OFF 19 |
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| 324 | #define R13_OFF 20 |
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| 325 | #define R14_OFF 21 |
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| 326 | #define R15_OFF 22 |
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| 327 | #define R16_OFF 23 |
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| 328 | #define R17_OFF 24 |
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| 329 | #define R18_OFF 25 |
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| 330 | #define DP_OFF 26 |
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| 331 | #endif |
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| 332 | |
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[e7e016f] | 333 | #ifdef RTEMS_UNIXLIB_SETJMP |
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[ac7d5ef0] | 334 | #define RP_OFF 0 |
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| 335 | #define SP_OFF 1 |
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| 336 | #define R3_OFF 4 |
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| 337 | #define R4_OFF 5 |
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| 338 | #define R5_OFF 6 |
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| 339 | #define R6_OFF 7 |
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| 340 | #define R7_OFF 8 |
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| 341 | #define R8_OFF 9 |
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| 342 | #define R9_OFF 10 |
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| 343 | #define R10_OFF 11 |
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| 344 | #define R11_OFF 12 |
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| 345 | #define R12_OFF 13 |
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| 346 | #define R13_OFF 14 |
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| 347 | #define R14_OFF 15 |
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| 348 | #define R15_OFF 16 |
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| 349 | #define R16_OFF 17 |
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| 350 | #define R17_OFF 18 |
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| 351 | #define R18_OFF 19 |
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| 352 | #define DP_OFF 20 |
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| 353 | #endif |
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| 354 | #endif |
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| 355 | |
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[8044533] | 356 | #if defined(i386) |
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| 357 | |
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| 358 | #ifdef RTEMS_NEWLIB |
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| 359 | #error "Newlib not installed" |
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| 360 | #endif |
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| 361 | |
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| 362 | /* |
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| 363 | * For Linux 1.1 |
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| 364 | */ |
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| 365 | |
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| 366 | #ifdef RTEMS_UNIXLIB |
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| 367 | #define EBX_OFF 0 |
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| 368 | #define ESI_OFF 1 |
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| 369 | #define EDI_OFF 2 |
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| 370 | #define EBP_OFF 3 |
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| 371 | #define ESP_OFF 4 |
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| 372 | #define RET_OFF 5 |
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| 373 | #endif |
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| 374 | |
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| 375 | #endif |
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| 376 | |
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[ac7d5ef0] | 377 | #if defined(sparc) |
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| 378 | |
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| 379 | /* |
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| 380 | * Word indices within a jmp_buf structure |
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| 381 | */ |
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| 382 | |
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| 383 | #ifdef RTEMS_NEWLIB |
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| 384 | #define ADDR_ADJ_OFFSET -8 |
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| 385 | #define SP_OFF 0 |
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| 386 | #define RP_OFF 1 |
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| 387 | #define FP_OFF 2 |
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| 388 | #endif |
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| 389 | |
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| 390 | #ifdef RTEMS_UNIXLIB |
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| 391 | #define ADDR_ADJ_OFFSET 0 |
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| 392 | #define G0_OFF 0 |
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| 393 | #define SP_OFF 1 |
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| 394 | #define RP_OFF 2 |
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| 395 | #define FP_OFF 3 |
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| 396 | #define I7_OFF 4 |
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| 397 | #endif |
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| 398 | |
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| 399 | #endif |
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| 400 | |
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| 401 | /* |
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| 402 | * Contexts |
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| 403 | * |
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| 404 | * Generally there are 2 types of context to save. |
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| 405 | * 1. Interrupt registers to save |
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| 406 | * 2. Task level registers to save |
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| 407 | * |
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| 408 | * This means we have the following 3 context items: |
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| 409 | * 1. task level context stuff:: Context_Control |
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| 410 | * 2. floating point task stuff:: Context_Control_fp |
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| 411 | * 3. special interrupt level context :: Context_Control_interrupt |
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| 412 | * |
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| 413 | * On some processors, it is cost-effective to save only the callee |
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| 414 | * preserved registers during a task context switch. This means |
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| 415 | * that the ISR code needs to save those registers which do not |
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| 416 | * persist across function calls. It is not mandatory to make this |
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| 417 | * distinctions between the caller/callee saves registers for the |
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| 418 | * purpose of minimizing context saved during task switch and on interrupts. |
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| 419 | * If the cost of saving extra registers is minimal, simplicity is the |
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| 420 | * choice. Save the same context on interrupt entry as for tasks in |
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| 421 | * this case. |
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| 422 | * |
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| 423 | * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then |
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| 424 | * care should be used in designing the context area. |
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| 425 | * |
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| 426 | * On some CPUs with hardware floating point support, the Context_Control_fp |
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| 427 | * structure will not be used or it simply consist of an array of a |
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| 428 | * fixed number of bytes. This is done when the floating point context |
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| 429 | * is dumped by a "FP save context" type instruction and the format |
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| 430 | * is not really defined by the CPU. In this case, there is no need |
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| 431 | * to figure out the exact format -- only the size. Of course, although |
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| 432 | * this is enough information for RTEMS, it is probably not enough for |
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| 433 | * a debugger such as gdb. But that is another problem. |
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| 434 | */ |
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| 435 | |
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[37f4c2d] | 436 | /* |
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| 437 | * This is really just the area for the following fields. |
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| 438 | * |
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[d196e48] | 439 | * jmp_buf regs; |
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| 440 | * unsigned32 isr_level; |
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[37f4c2d] | 441 | * |
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| 442 | * Doing it this way avoids conflicts between the native stuff and the |
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| 443 | * RTEMS stuff. |
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[cc4c1fe4] | 444 | * |
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| 445 | * NOTE: |
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| 446 | * hpux9 setjmp is optimized for the case where the setjmp buffer |
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| 447 | * is 8 byte aligned. In a RISC world, this seems likely to enable |
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| 448 | * 8 byte copies, especially for the float registers. |
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| 449 | * So we always align them on 8 byte boundaries. |
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[37f4c2d] | 450 | */ |
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[cc4c1fe4] | 451 | |
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| 452 | #ifdef __GNUC__ |
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| 453 | #define CONTEXT_STRUCTURE_ALIGNMENT __attribute__ ((aligned (8))) |
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| 454 | #else |
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| 455 | #define CONTEXT_STRUCTURE_ALIGNMENT |
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| 456 | #endif |
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| 457 | |
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[ac7d5ef0] | 458 | typedef struct { |
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[cc4c1fe4] | 459 | char Area[ CPU_CONTEXT_SIZE_IN_BYTES ] CONTEXT_STRUCTURE_ALIGNMENT; |
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[ac7d5ef0] | 460 | } Context_Control; |
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| 461 | |
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| 462 | typedef struct { |
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| 463 | } Context_Control_fp; |
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| 464 | |
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| 465 | typedef struct { |
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| 466 | } CPU_Interrupt_frame; |
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| 467 | |
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| 468 | |
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| 469 | /* |
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| 470 | * The following table contains the information required to configure |
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[cc4c1fe4] | 471 | * the UNIX Simulator specific parameters. |
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[ac7d5ef0] | 472 | */ |
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| 473 | |
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| 474 | typedef struct { |
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| 475 | void (*pretasking_hook)( void ); |
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| 476 | void (*predriver_hook)( void ); |
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| 477 | void (*postdriver_hook)( void ); |
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| 478 | void (*idle_task)( void ); |
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| 479 | boolean do_zero_of_workspace; |
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| 480 | unsigned32 interrupt_stack_size; |
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[75f09e5] | 481 | unsigned32 extra_mpci_receive_server_stack; |
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[cc4c1fe4] | 482 | void * (*stack_allocate_hook)( unsigned32 ); |
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| 483 | void (*stack_free_hook)( void* ); |
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| 484 | /* end of required fields */ |
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[ac7d5ef0] | 485 | } rtems_cpu_table; |
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| 486 | |
---|
| 487 | /* |
---|
| 488 | * This variable is optional. It is used on CPUs on which it is difficult |
---|
| 489 | * to generate an "uninitialized" FP context. It is filled in by |
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| 490 | * _CPU_Initialize and copied into the task's FP context area during |
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| 491 | * _CPU_Context_Initialize. |
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| 492 | */ |
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| 493 | |
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[c627b2a3] | 494 | SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context; |
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[ac7d5ef0] | 495 | |
---|
| 496 | /* |
---|
| 497 | * On some CPUs, RTEMS supports a software managed interrupt stack. |
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| 498 | * This stack is allocated by the Interrupt Manager and the switch |
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| 499 | * is performed in _ISR_Handler. These variables contain pointers |
---|
| 500 | * to the lowest and highest addresses in the chunk of memory allocated |
---|
| 501 | * for the interrupt stack. Since it is unknown whether the stack |
---|
| 502 | * grows up or down (in general), this give the CPU dependent |
---|
| 503 | * code the option of picking the version it wants to use. |
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| 504 | * |
---|
| 505 | * NOTE: These two variables are required if the macro |
---|
| 506 | * CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE. |
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| 507 | */ |
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| 508 | |
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[c627b2a3] | 509 | SCORE_EXTERN void *_CPU_Interrupt_stack_low; |
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| 510 | SCORE_EXTERN void *_CPU_Interrupt_stack_high; |
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[ac7d5ef0] | 511 | |
---|
| 512 | /* |
---|
| 513 | * With some compilation systems, it is difficult if not impossible to |
---|
| 514 | * call a high-level language routine from assembly language. This |
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| 515 | * is especially true of commercial Ada compilers and name mangling |
---|
| 516 | * C++ ones. This variable can be optionally defined by the CPU porter |
---|
| 517 | * and contains the address of the routine _Thread_Dispatch. This |
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| 518 | * can make it easier to invoke that routine at the end of the interrupt |
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| 519 | * sequence (if a dispatch is necessary). |
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| 520 | */ |
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| 521 | |
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[c627b2a3] | 522 | SCORE_EXTERN void (*_CPU_Thread_dispatch_pointer)(); |
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[ac7d5ef0] | 523 | |
---|
| 524 | /* |
---|
| 525 | * Nothing prevents the porter from declaring more CPU specific variables. |
---|
| 526 | */ |
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| 527 | |
---|
| 528 | /* XXX: if needed, put more variables here */ |
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| 529 | |
---|
| 530 | /* |
---|
| 531 | * The size of the floating point context area. On some CPUs this |
---|
| 532 | * will not be a "sizeof" because the format of the floating point |
---|
| 533 | * area is not defined -- only the size is. This is usually on |
---|
| 534 | * CPUs with a "floating point save context" instruction. |
---|
| 535 | */ |
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| 536 | |
---|
| 537 | #define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) |
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| 538 | |
---|
| 539 | /* |
---|
| 540 | * The size of a frame on the stack |
---|
| 541 | */ |
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| 542 | |
---|
| 543 | #if defined(hppa1_1) |
---|
| 544 | #define CPU_FRAME_SIZE (32 * 4) |
---|
| 545 | #elif defined(sparc) |
---|
| 546 | #define CPU_FRAME_SIZE (112) /* based on disassembled test code */ |
---|
[8044533] | 547 | #elif defined(i386) |
---|
| 548 | #define CPU_FRAME_SIZE (24) /* return address, sp, and bp pushed plus fudge */ |
---|
[ac7d5ef0] | 549 | #else |
---|
| 550 | #error "Unknown CPU!!!" |
---|
| 551 | #endif |
---|
| 552 | |
---|
| 553 | /* |
---|
| 554 | * Amount of extra stack (above minimum stack size) required by |
---|
[75f09e5] | 555 | * MPCI receive server thread. Remember that in a multiprocessor |
---|
| 556 | * system this thread must exist and be able to process all directives. |
---|
[ac7d5ef0] | 557 | */ |
---|
| 558 | |
---|
[75f09e5] | 559 | #define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 |
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[ac7d5ef0] | 560 | |
---|
| 561 | /* |
---|
| 562 | * This defines the number of entries in the ISR_Vector_table managed |
---|
| 563 | * by RTEMS. |
---|
| 564 | */ |
---|
| 565 | |
---|
[9700578] | 566 | #define CPU_INTERRUPT_NUMBER_OF_VECTORS 64 |
---|
| 567 | #define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1) |
---|
[ac7d5ef0] | 568 | |
---|
| 569 | /* |
---|
| 570 | * Should be large enough to run all RTEMS tests. This insures |
---|
| 571 | * that a "reasonable" small application should not have any problems. |
---|
| 572 | */ |
---|
| 573 | |
---|
| 574 | #define CPU_STACK_MINIMUM_SIZE (16 * 1024) |
---|
| 575 | |
---|
| 576 | /* |
---|
| 577 | * CPU's worst alignment requirement for data types on a byte boundary. This |
---|
| 578 | * alignment does not take into account the requirements for the stack. |
---|
| 579 | */ |
---|
| 580 | |
---|
| 581 | #define CPU_ALIGNMENT 8 |
---|
| 582 | |
---|
| 583 | /* |
---|
| 584 | * This number corresponds to the byte alignment requirement for the |
---|
| 585 | * heap handler. This alignment requirement may be stricter than that |
---|
| 586 | * for the data types alignment specified by CPU_ALIGNMENT. It is |
---|
| 587 | * common for the heap to follow the same alignment requirement as |
---|
| 588 | * CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict enough for the heap, |
---|
| 589 | * then this should be set to CPU_ALIGNMENT. |
---|
| 590 | * |
---|
| 591 | * NOTE: This does not have to be a power of 2. It does have to |
---|
| 592 | * be greater or equal to than CPU_ALIGNMENT. |
---|
| 593 | */ |
---|
| 594 | |
---|
| 595 | #define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT |
---|
| 596 | |
---|
| 597 | /* |
---|
| 598 | * This number corresponds to the byte alignment requirement for memory |
---|
| 599 | * buffers allocated by the partition manager. This alignment requirement |
---|
| 600 | * may be stricter than that for the data types alignment specified by |
---|
| 601 | * CPU_ALIGNMENT. It is common for the partition to follow the same |
---|
| 602 | * alignment requirement as CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict |
---|
| 603 | * enough for the partition, then this should be set to CPU_ALIGNMENT. |
---|
| 604 | * |
---|
| 605 | * NOTE: This does not have to be a power of 2. It does have to |
---|
| 606 | * be greater or equal to than CPU_ALIGNMENT. |
---|
| 607 | */ |
---|
| 608 | |
---|
| 609 | #define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT |
---|
| 610 | |
---|
| 611 | /* |
---|
| 612 | * This number corresponds to the byte alignment requirement for the |
---|
| 613 | * stack. This alignment requirement may be stricter than that for the |
---|
| 614 | * data types alignment specified by CPU_ALIGNMENT. If the CPU_ALIGNMENT |
---|
| 615 | * is strict enough for the stack, then this should be set to 0. |
---|
| 616 | * |
---|
| 617 | * NOTE: This must be a power of 2 either 0 or greater than CPU_ALIGNMENT. |
---|
| 618 | */ |
---|
| 619 | |
---|
| 620 | #define CPU_STACK_ALIGNMENT 64 |
---|
| 621 | |
---|
| 622 | /* ISR handler macros */ |
---|
| 623 | |
---|
| 624 | /* |
---|
| 625 | * Disable all interrupts for an RTEMS critical section. The previous |
---|
| 626 | * level is returned in _level. |
---|
| 627 | */ |
---|
| 628 | |
---|
[637df35] | 629 | extern unsigned32 _CPU_ISR_Disable_support(void); |
---|
| 630 | |
---|
[ac7d5ef0] | 631 | #define _CPU_ISR_Disable( _level ) \ |
---|
| 632 | do { \ |
---|
[637df35] | 633 | (_level) = _CPU_ISR_Disable_support(); \ |
---|
[ac7d5ef0] | 634 | } while ( 0 ) |
---|
| 635 | |
---|
| 636 | /* |
---|
| 637 | * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). |
---|
| 638 | * This indicates the end of an RTEMS critical section. The parameter |
---|
| 639 | * _level is not modified. |
---|
| 640 | */ |
---|
| 641 | |
---|
[637df35] | 642 | void _CPU_ISR_Enable(unsigned32 level); |
---|
[ac7d5ef0] | 643 | |
---|
| 644 | /* |
---|
| 645 | * This temporarily restores the interrupt to _level before immediately |
---|
| 646 | * disabling them again. This is used to divide long RTEMS critical |
---|
| 647 | * sections into two or more parts. The parameter _level is not |
---|
| 648 | * modified. |
---|
| 649 | */ |
---|
| 650 | |
---|
| 651 | #define _CPU_ISR_Flash( _level ) \ |
---|
| 652 | do { \ |
---|
| 653 | register _ignored = 0; \ |
---|
| 654 | _CPU_ISR_Enable( (_level) ); \ |
---|
| 655 | _CPU_ISR_Disable( _ignored ); \ |
---|
| 656 | } while ( 0 ) |
---|
| 657 | |
---|
| 658 | /* |
---|
| 659 | * Map interrupt level in task mode onto the hardware that the CPU |
---|
| 660 | * actually provides. Currently, interrupt levels which do not |
---|
| 661 | * map onto the CPU in a generic fashion are undefined. Someday, |
---|
| 662 | * it would be nice if these were "mapped" by the application |
---|
| 663 | * via a callout. For example, m68k has 8 levels 0 - 7, levels |
---|
| 664 | * 8 - 255 would be available for bsp/application specific meaning. |
---|
| 665 | * This could be used to manage a programmable interrupt controller |
---|
| 666 | * via the rtems_task_mode directive. |
---|
| 667 | */ |
---|
| 668 | |
---|
| 669 | #define _CPU_ISR_Set_level( new_level ) \ |
---|
| 670 | { \ |
---|
[637df35] | 671 | if ( new_level == 0 ) _CPU_ISR_Enable( 0 ); \ |
---|
| 672 | else _CPU_ISR_Enable( 1 ); \ |
---|
[ac7d5ef0] | 673 | } |
---|
| 674 | |
---|
[3a4ae6c] | 675 | unsigned32 _CPU_ISR_Get_level( void ); |
---|
| 676 | |
---|
[ac7d5ef0] | 677 | /* end of ISR handler macros */ |
---|
| 678 | |
---|
| 679 | /* Context handler macros */ |
---|
| 680 | |
---|
| 681 | /* |
---|
| 682 | * This routine is responsible for somehow restarting the currently |
---|
| 683 | * executing task. If you are lucky, then all that is necessary |
---|
| 684 | * is restoring the context. Otherwise, there will need to be |
---|
| 685 | * a special assembly routine which does something special in this |
---|
| 686 | * case. Context_Restore should work most of the time. It will |
---|
| 687 | * not work if restarting self conflicts with the stack frame |
---|
| 688 | * assumptions of restoring a context. |
---|
| 689 | */ |
---|
| 690 | |
---|
| 691 | #define _CPU_Context_Restart_self( _the_context ) \ |
---|
| 692 | _CPU_Context_restore( (_the_context) ); |
---|
| 693 | |
---|
| 694 | /* |
---|
| 695 | * The purpose of this macro is to allow the initial pointer into |
---|
| 696 | * a floating point context area (used to save the floating point |
---|
| 697 | * context) to be at an arbitrary place in the floating point |
---|
| 698 | * context area. |
---|
| 699 | * |
---|
| 700 | * This is necessary because some FP units are designed to have |
---|
| 701 | * their context saved as a stack which grows into lower addresses. |
---|
| 702 | * Other FP units can be saved by simply moving registers into offsets |
---|
| 703 | * from the base of the context area. Finally some FP units provide |
---|
| 704 | * a "dump context" instruction which could fill in from high to low |
---|
| 705 | * or low to high based on the whim of the CPU designers. |
---|
| 706 | */ |
---|
| 707 | |
---|
| 708 | #define _CPU_Context_Fp_start( _base, _offset ) \ |
---|
[2069773] | 709 | ( (void *) _Addresses_Add_offset( (_base), (_offset) ) ) |
---|
[ac7d5ef0] | 710 | |
---|
| 711 | /* |
---|
| 712 | * This routine initializes the FP context area passed to it to. |
---|
| 713 | * There are a few standard ways in which to initialize the |
---|
| 714 | * floating point context. The code included for this macro assumes |
---|
| 715 | * that this is a CPU in which a "initial" FP context was saved into |
---|
| 716 | * _CPU_Null_fp_context and it simply copies it to the destination |
---|
| 717 | * context passed to it. |
---|
| 718 | * |
---|
| 719 | * Other models include (1) not doing anything, and (2) putting |
---|
| 720 | * a "null FP status word" in the correct place in the FP context. |
---|
| 721 | */ |
---|
| 722 | |
---|
| 723 | #define _CPU_Context_Initialize_fp( _destination ) \ |
---|
| 724 | { \ |
---|
| 725 | *((Context_Control_fp *) *((void **) _destination)) = _CPU_Null_fp_context; \ |
---|
| 726 | } |
---|
| 727 | |
---|
| 728 | #define _CPU_Context_save_fp( _fp_context ) \ |
---|
| 729 | _CPU_Save_float_context( *(Context_Control_fp **)(_fp_context)) |
---|
| 730 | |
---|
| 731 | #define _CPU_Context_restore_fp( _fp_context ) \ |
---|
| 732 | _CPU_Restore_float_context( *(Context_Control_fp **)(_fp_context)) |
---|
| 733 | |
---|
| 734 | extern void _CPU_Context_Initialize( |
---|
| 735 | Context_Control *_the_context, |
---|
| 736 | unsigned32 *_stack_base, |
---|
| 737 | unsigned32 _size, |
---|
| 738 | unsigned32 _new_level, |
---|
[9700578] | 739 | void *_entry_point, |
---|
| 740 | boolean _is_fp |
---|
[ac7d5ef0] | 741 | ); |
---|
| 742 | |
---|
| 743 | /* end of Context handler macros */ |
---|
| 744 | |
---|
| 745 | /* Fatal Error manager macros */ |
---|
| 746 | |
---|
| 747 | /* |
---|
| 748 | * This routine copies _error into a known place -- typically a stack |
---|
| 749 | * location or a register, optionally disables interrupts, and |
---|
| 750 | * halts/stops the CPU. |
---|
| 751 | */ |
---|
| 752 | |
---|
| 753 | #define _CPU_Fatal_halt( _error ) \ |
---|
| 754 | _CPU_Fatal_error( _error ) |
---|
| 755 | |
---|
| 756 | /* end of Fatal Error manager macros */ |
---|
| 757 | |
---|
| 758 | /* Bitfield handler macros */ |
---|
| 759 | |
---|
| 760 | /* |
---|
| 761 | * This routine sets _output to the bit number of the first bit |
---|
| 762 | * set in _value. _value is of CPU dependent type Priority_Bit_map_control. |
---|
| 763 | * This type may be either 16 or 32 bits wide although only the 16 |
---|
| 764 | * least significant bits will be used. |
---|
| 765 | * |
---|
| 766 | * There are a number of variables in using a "find first bit" type |
---|
| 767 | * instruction. |
---|
| 768 | * |
---|
| 769 | * (1) What happens when run on a value of zero? |
---|
| 770 | * (2) Bits may be numbered from MSB to LSB or vice-versa. |
---|
| 771 | * (3) The numbering may be zero or one based. |
---|
| 772 | * (4) The "find first bit" instruction may search from MSB or LSB. |
---|
| 773 | * |
---|
| 774 | * RTEMS guarantees that (1) will never happen so it is not a concern. |
---|
| 775 | * (2),(3), (4) are handled by the macros _CPU_Priority_mask() and |
---|
[9700578] | 776 | * _CPU_Priority_bits_index(). These three form a set of routines |
---|
[ac7d5ef0] | 777 | * which must logically operate together. Bits in the _value are |
---|
| 778 | * set and cleared based on masks built by _CPU_Priority_mask(). |
---|
| 779 | * The basic major and minor values calculated by _Priority_Major() |
---|
[9700578] | 780 | * and _Priority_Minor() are "massaged" by _CPU_Priority_bits_index() |
---|
[ac7d5ef0] | 781 | * to properly range between the values returned by the "find first bit" |
---|
| 782 | * instruction. This makes it possible for _Priority_Get_highest() to |
---|
| 783 | * calculate the major and directly index into the minor table. |
---|
| 784 | * This mapping is necessary to ensure that 0 (a high priority major/minor) |
---|
| 785 | * is the first bit found. |
---|
| 786 | * |
---|
| 787 | * This entire "find first bit" and mapping process depends heavily |
---|
| 788 | * on the manner in which a priority is broken into a major and minor |
---|
| 789 | * components with the major being the 4 MSB of a priority and minor |
---|
| 790 | * the 4 LSB. Thus (0 << 4) + 0 corresponds to priority 0 -- the highest |
---|
| 791 | * priority. And (15 << 4) + 14 corresponds to priority 254 -- the next |
---|
| 792 | * to the lowest priority. |
---|
| 793 | * |
---|
| 794 | * If your CPU does not have a "find first bit" instruction, then |
---|
| 795 | * there are ways to make do without it. Here are a handful of ways |
---|
| 796 | * to implement this in software: |
---|
| 797 | * |
---|
| 798 | * - a series of 16 bit test instructions |
---|
| 799 | * - a "binary search using if's" |
---|
| 800 | * - _number = 0 |
---|
| 801 | * if _value > 0x00ff |
---|
| 802 | * _value >>=8 |
---|
| 803 | * _number = 8; |
---|
| 804 | * |
---|
| 805 | * if _value > 0x0000f |
---|
| 806 | * _value >=8 |
---|
| 807 | * _number += 4 |
---|
| 808 | * |
---|
| 809 | * _number += bit_set_table[ _value ] |
---|
| 810 | * |
---|
| 811 | * where bit_set_table[ 16 ] has values which indicate the first |
---|
| 812 | * bit set |
---|
| 813 | */ |
---|
| 814 | |
---|
| 815 | /* |
---|
[9700578] | 816 | * The UNIX port uses the generic C algorithm for bitfield scan to avoid |
---|
| 817 | * dependencies on either a native bitscan instruction or an ffs() in the |
---|
| 818 | * C library. |
---|
[ac7d5ef0] | 819 | */ |
---|
[9700578] | 820 | |
---|
| 821 | #define CPU_USE_GENERIC_BITFIELD_CODE TRUE |
---|
| 822 | #define CPU_USE_GENERIC_BITFIELD_DATA TRUE |
---|
| 823 | |
---|
| 824 | /* end of Bitfield handler macros */ |
---|
| 825 | |
---|
| 826 | /* Priority handler handler macros */ |
---|
| 827 | |
---|
[ac7d5ef0] | 828 | /* |
---|
[9700578] | 829 | * The UNIX port uses the generic C algorithm for bitfield scan to avoid |
---|
| 830 | * dependencies on either a native bitscan instruction or an ffs() in the |
---|
| 831 | * C library. |
---|
[ac7d5ef0] | 832 | */ |
---|
[9700578] | 833 | |
---|
[ac7d5ef0] | 834 | /* end of Priority handler macros */ |
---|
| 835 | |
---|
| 836 | /* functions */ |
---|
| 837 | |
---|
| 838 | /* |
---|
| 839 | * _CPU_Initialize |
---|
| 840 | * |
---|
| 841 | * This routine performs CPU dependent initialization. |
---|
| 842 | */ |
---|
| 843 | |
---|
| 844 | void _CPU_Initialize( |
---|
| 845 | rtems_cpu_table *cpu_table, |
---|
| 846 | void (*thread_dispatch) |
---|
| 847 | ); |
---|
| 848 | |
---|
[637df35] | 849 | /* |
---|
| 850 | * _CPU_ISR_install_raw_handler |
---|
| 851 | * |
---|
| 852 | * This routine installs a "raw" interrupt handler directly into the |
---|
| 853 | * processor's vector table. |
---|
| 854 | */ |
---|
| 855 | |
---|
| 856 | void _CPU_ISR_install_raw_handler( |
---|
| 857 | unsigned32 vector, |
---|
| 858 | proc_ptr new_handler, |
---|
| 859 | proc_ptr *old_handler |
---|
| 860 | ); |
---|
| 861 | |
---|
[ac7d5ef0] | 862 | /* |
---|
| 863 | * _CPU_ISR_install_vector |
---|
| 864 | * |
---|
| 865 | * This routine installs an interrupt vector. |
---|
| 866 | */ |
---|
| 867 | |
---|
| 868 | void _CPU_ISR_install_vector( |
---|
| 869 | unsigned32 vector, |
---|
| 870 | proc_ptr new_handler, |
---|
| 871 | proc_ptr *old_handler |
---|
| 872 | ); |
---|
| 873 | |
---|
| 874 | /* |
---|
| 875 | * _CPU_Install_interrupt_stack |
---|
| 876 | * |
---|
| 877 | * This routine installs the hardware interrupt stack pointer. |
---|
| 878 | * |
---|
| 879 | * NOTE: It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK |
---|
| 880 | * is TRUE. |
---|
| 881 | */ |
---|
| 882 | |
---|
| 883 | void _CPU_Install_interrupt_stack( void ); |
---|
| 884 | |
---|
| 885 | /* |
---|
[75f09e5] | 886 | * _CPU_Thread_Idle_body |
---|
[ac7d5ef0] | 887 | * |
---|
| 888 | * This routine is the CPU dependent IDLE thread body. |
---|
| 889 | * |
---|
| 890 | * NOTE: It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY |
---|
| 891 | * is TRUE. |
---|
| 892 | */ |
---|
| 893 | |
---|
[75f09e5] | 894 | void _CPU_Thread_Idle_body( void ); |
---|
[ac7d5ef0] | 895 | |
---|
| 896 | /* |
---|
| 897 | * _CPU_Context_switch |
---|
| 898 | * |
---|
| 899 | * This routine switches from the run context to the heir context. |
---|
| 900 | */ |
---|
| 901 | |
---|
| 902 | void _CPU_Context_switch( |
---|
| 903 | Context_Control *run, |
---|
| 904 | Context_Control *heir |
---|
| 905 | ); |
---|
| 906 | |
---|
| 907 | /* |
---|
| 908 | * _CPU_Context_restore |
---|
| 909 | * |
---|
| 910 | * This routine is generallu used only to restart self in an |
---|
| 911 | * efficient manner. It may simply be a label in _CPU_Context_switch. |
---|
| 912 | * |
---|
| 913 | * NOTE: May be unnecessary to reload some registers. |
---|
| 914 | */ |
---|
| 915 | |
---|
| 916 | void _CPU_Context_restore( |
---|
| 917 | Context_Control *new_context |
---|
| 918 | ); |
---|
| 919 | |
---|
| 920 | /* |
---|
| 921 | * _CPU_Save_float_context |
---|
| 922 | * |
---|
| 923 | * This routine saves the floating point context passed to it. |
---|
| 924 | */ |
---|
| 925 | |
---|
| 926 | void _CPU_Save_float_context( |
---|
| 927 | Context_Control_fp *fp_context_ptr |
---|
| 928 | ); |
---|
| 929 | |
---|
| 930 | /* |
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| 931 | * _CPU_Restore_float_context |
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| 932 | * |
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| 933 | * This routine restores the floating point context passed to it. |
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| 934 | */ |
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| 935 | |
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| 936 | void _CPU_Restore_float_context( |
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| 937 | Context_Control_fp *fp_context_ptr |
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| 938 | ); |
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| 939 | |
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| 940 | |
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| 941 | void _CPU_ISR_Set_signal_level( |
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| 942 | unsigned32 level |
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| 943 | ); |
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| 944 | |
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| 945 | void _CPU_Fatal_error( |
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| 946 | unsigned32 _error |
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| 947 | ); |
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| 948 | |
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| 949 | /* The following routine swaps the endian format of an unsigned int. |
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| 950 | * It must be static because it is referenced indirectly. |
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| 951 | * |
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| 952 | * This version will work on any processor, but if there is a better |
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| 953 | * way for your CPU PLEASE use it. The most common way to do this is to: |
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| 954 | * |
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| 955 | * swap least significant two bytes with 16-bit rotate |
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| 956 | * swap upper and lower 16-bits |
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| 957 | * swap most significant two bytes with 16-bit rotate |
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| 958 | * |
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| 959 | * Some CPUs have special instructions which swap a 32-bit quantity in |
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| 960 | * a single instruction (e.g. i486). It is probably best to avoid |
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| 961 | * an "endian swapping control bit" in the CPU. One good reason is |
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| 962 | * that interrupts would probably have to be disabled to insure that |
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| 963 | * an interrupt does not try to access the same "chunk" with the wrong |
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| 964 | * endian. Another good reason is that on some CPUs, the endian bit |
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| 965 | * endianness for ALL fetches -- both code and data -- so the code |
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| 966 | * will be fetched incorrectly. |
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| 967 | */ |
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| 968 | |
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| 969 | static inline unsigned int CPU_swap_u32( |
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| 970 | unsigned int value |
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| 971 | ) |
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| 972 | { |
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| 973 | unsigned32 byte1, byte2, byte3, byte4, swapped; |
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| 974 | |
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| 975 | byte4 = (value >> 24) & 0xff; |
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| 976 | byte3 = (value >> 16) & 0xff; |
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| 977 | byte2 = (value >> 8) & 0xff; |
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| 978 | byte1 = value & 0xff; |
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| 979 | |
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| 980 | swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; |
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| 981 | return( swapped ); |
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| 982 | } |
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| 983 | |
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[37f4c2d] | 984 | /* |
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| 985 | * Special Purpose Routines to hide the use of UNIX system calls. |
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| 986 | */ |
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| 987 | |
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| 988 | int _CPU_Get_clock_vector( void ); |
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| 989 | |
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| 990 | void _CPU_Start_clock( |
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| 991 | int microseconds |
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| 992 | ); |
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| 993 | |
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| 994 | void _CPU_Stop_clock( void ); |
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| 995 | |
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| 996 | void _CPU_SHM_Init( |
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| 997 | unsigned32 maximum_nodes, |
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| 998 | boolean is_master_node, |
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| 999 | void **shm_address, |
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| 1000 | unsigned32 *shm_length |
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| 1001 | ); |
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| 1002 | |
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| 1003 | int _CPU_Get_pid( void ); |
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| 1004 | |
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| 1005 | int _CPU_SHM_Get_vector( void ); |
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| 1006 | |
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| 1007 | void _CPU_SHM_Send_interrupt( |
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| 1008 | int pid, |
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| 1009 | int vector |
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| 1010 | ); |
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| 1011 | |
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| 1012 | void _CPU_SHM_Lock( |
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| 1013 | int semaphore |
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| 1014 | ); |
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| 1015 | |
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| 1016 | void _CPU_SHM_Unlock( |
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| 1017 | int semaphore |
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| 1018 | ); |
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| 1019 | |
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[ac7d5ef0] | 1020 | #ifdef __cplusplus |
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| 1021 | } |
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| 1022 | #endif |
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| 1023 | |
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| 1024 | #endif |
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