source: rtems/c/src/exec/score/cpu/unix/cpu.c @ 10aed1e3

4.104.114.84.95
Last change on this file since 10aed1e3 was 10aed1e3, checked in by Joel Sherrill <joel.sherrill@…>, on Jul 18, 1995 at 7:58:45 PM

fixed for Linux

  • Property mode set to 100644
File size: 13.3 KB
Line 
1/*
2 *  HP PA-RISC CPU Dependent Source
3 *
4 *
5 *  To anyone who acknowledges that this file is provided "AS IS"
6 *  without any express or implied warranty:
7 *      permission to use, copy, modify, and distribute this file
8 *      for any purpose is hereby granted without fee, provided that
9 *      the above copyright notice and this notice appears in all
10 *      copies, and that the name of Division Incorporated not be
11 *      used in advertising or publicity pertaining to distribution
12 *      of the software without specific, written prior permission.
13 *      Division Incorporated makes no representations about the
14 *      suitability of this software for any purpose.
15 *
16 *  $Id$
17 */
18
19#include <rtems/system.h>
20#include <rtems/isr.h>
21
22#include <stdio.h>
23#include <stdlib.h>
24#include <unistd.h>
25#include <signal.h>
26#include <time.h>
27#include <sys/time.h>
28
29#ifndef SA_RESTART
30#define SA_RESTART 0
31#endif
32
33void  _CPU_Signal_initialize(void);
34void  _CPU_Stray_signal(int);
35void  _CPU_ISR_Handler(int);
36
37sigset_t         _CPU_Signal_mask;
38Context_Control  _CPU_Context_Default_with_ISRs_enabled;
39Context_Control  _CPU_Context_Default_with_ISRs_disabled;
40
41/*
42 * Which cpu are we? Used by libcpu and libbsp.
43 */
44
45int cpu_number;
46
47/*PAGE
48 *
49 *  _CPU_ISR_From_CPU_Init
50 */
51
52void _CPU_ISR_From_CPU_Init()
53{
54  unsigned32        i;
55  proc_ptr          old_handler;
56
57
58  /*
59   * Block all the signals except SIGTRAP for the debugger
60   * and SIGABRT for fatal errors.
61   */
62
63  _CPU_ISR_Enable(1);
64
65  (void) sigfillset(&_CPU_Signal_mask);
66  (void) sigdelset(&_CPU_Signal_mask, SIGTRAP);
67  (void) sigdelset(&_CPU_Signal_mask, SIGABRT);
68  (void) sigdelset(&_CPU_Signal_mask, SIGIOT);
69  (void) sigdelset(&_CPU_Signal_mask, SIGCONT);
70
71  sigprocmask(SIG_BLOCK, &_CPU_Signal_mask, 0);
72
73  /*
74   * Set the handler for all signals to be signal_handler
75   * which will then vector out to the correct handler
76   * for whichever signal actually happened. Initially
77   * set the vectors to the stray signal handler.
78   */
79
80  for (i = 0; i < CPU_INTERRUPT_NUMBER_OF_VECTORS; i++)
81      (void)_CPU_ISR_install_vector(i, _CPU_Stray_signal, &old_handler);
82
83  _CPU_Signal_initialize();
84}
85
86void _CPU_Signal_initialize( void )
87{
88  struct sigaction  act;
89  sigset_t          mask;
90
91  /* mark them all active except for TraceTrap  and Abort */
92
93  sigfillset(&mask);
94  sigdelset(&mask, SIGTRAP);
95  sigdelset(&mask, SIGABRT);
96  sigdelset(&mask, SIGIOT);
97  sigdelset(&mask, SIGCONT);
98  sigprocmask(SIG_UNBLOCK, &mask, 0);
99
100  act.sa_handler = _CPU_ISR_Handler;
101  act.sa_mask = mask;
102  act.sa_flags = SA_RESTART;
103
104  sigaction(SIGHUP, &act, 0);
105  sigaction(SIGINT, &act, 0);
106  sigaction(SIGQUIT, &act, 0);
107  sigaction(SIGILL, &act, 0);
108#ifdef SIGEMT
109  sigaction(SIGEMT, &act, 0);
110#endif
111  sigaction(SIGFPE, &act, 0);
112  sigaction(SIGKILL, &act, 0);
113  sigaction(SIGBUS, &act, 0);
114  sigaction(SIGSEGV, &act, 0);
115#ifdef SIGSYS
116  sigaction(SIGSYS, &act, 0);
117#endif
118  sigaction(SIGPIPE, &act, 0);
119  sigaction(SIGALRM, &act, 0);
120  sigaction(SIGTERM, &act, 0);
121  sigaction(SIGUSR1, &act, 0);
122  sigaction(SIGUSR2, &act, 0);
123  sigaction(SIGCHLD, &act, 0);
124  sigaction(SIGCLD, &act, 0);
125  sigaction(SIGPWR, &act, 0);
126  sigaction(SIGVTALRM, &act, 0);
127  sigaction(SIGPROF, &act, 0);
128  sigaction(SIGIO, &act, 0);
129  sigaction(SIGWINCH, &act, 0);
130  sigaction(SIGSTOP, &act, 0);
131  sigaction(SIGTTIN, &act, 0);
132  sigaction(SIGTTOU, &act, 0);
133  sigaction(SIGURG, &act, 0);
134/*
135 *  XXX: Really should be on HPUX.
136 */
137
138#if defined(hppa1_1)
139    sigaction(SIGLOST, &act, 0);
140#endif
141
142}
143
144/*PAGE
145 *
146 *  _CPU_Context_From_CPU_Init
147 */
148
149void _CPU_Context_From_CPU_Init()
150{
151
152#if defined(hppa1_1) && defined(RTEMS_UNIXLIB)
153    /*
154     * HACK - set the _SYSTEM_ID to 0x20c so that setjmp/longjmp
155     * will handle the full 32 floating point registers.
156     *
157     *  NOTE:  Is this a bug in HPUX9?
158     */
159
160    {
161      extern unsigned32 _SYSTEM_ID;
162
163      _SYSTEM_ID = 0x20c;
164    }
165#endif
166
167  /*
168   *  get default values to use in _CPU_Context_Initialize()
169   */
170
171  _CPU_ISR_Set_level( 0 );
172  setjmp( _CPU_Context_Default_with_ISRs_enabled.regs );
173  sigprocmask(
174    SIG_SETMASK,    /* ignored when second arg is NULL */
175    0,
176    &_CPU_Context_Default_with_ISRs_enabled.isr_level
177  );
178
179  _CPU_ISR_Set_level( 1 );
180  setjmp( _CPU_Context_Default_with_ISRs_disabled.regs );
181  sigprocmask(
182    SIG_SETMASK,    /* ignored when second arg is NULL */
183    0,
184    &_CPU_Context_Default_with_ISRs_disabled.isr_level
185  );
186
187}
188
189/*  _CPU_Initialize
190 *
191 *  This routine performs processor dependent initialization.
192 *
193 *  INPUT PARAMETERS:
194 *    cpu_table       - CPU table to initialize
195 *    thread_dispatch - address of disptaching routine
196 */
197
198
199void _CPU_Initialize(
200  rtems_cpu_table  *cpu_table,
201  void      (*thread_dispatch)      /* ignored on this CPU */
202)
203{
204  if ( cpu_table == NULL )
205    _CPU_Fatal_halt( RTEMS_NOT_CONFIGURED );
206
207  /*
208   *  The thread_dispatch argument is the address of the entry point
209   *  for the routine called at the end of an ISR once it has been
210   *  decided a context switch is necessary.  On some compilation
211   *  systems it is difficult to call a high-level language routine
212   *  from assembly.  This allows us to trick these systems.
213   *
214   *  If you encounter this problem save the entry point in a CPU
215   *  dependent variable.
216   */
217
218  _CPU_Thread_dispatch_pointer = thread_dispatch;
219
220  /*
221   * XXX; If there is not an easy way to initialize the FP context
222   *      during Context_Initialize, then it is usually easier to
223   *      save an "uninitialized" FP context here and copy it to
224   *      the task's during Context_Initialize.
225   */
226
227  /* XXX: FP context initialization support */
228
229  _CPU_Table = *cpu_table;
230
231  _CPU_ISR_From_CPU_Init();
232
233  _CPU_Context_From_CPU_Init();
234
235}
236
237/*PAGE
238 *
239 *  _CPU_ISR_install_raw_handler
240 */
241
242void _CPU_ISR_install_raw_handler(
243  unsigned32  vector,
244  proc_ptr    new_handler,
245  proc_ptr   *old_handler
246)
247{
248  _CPU_Fatal_halt( 0xdeaddead );
249}
250
251/*PAGE
252 *
253 *  _CPU_ISR_install_vector
254 *
255 *  This kernel routine installs the RTEMS handler for the
256 *  specified vector.
257 *
258 *  Input parameters:
259 *    vector      - interrupt vector number
260 *    old_handler - former ISR for this vector number
261 *    new_handler - replacement ISR for this vector number
262 *
263 *  Output parameters:  NONE
264 *
265 */
266
267
268void _CPU_ISR_install_vector(
269  unsigned32  vector,
270  proc_ptr    new_handler,
271  proc_ptr   *old_handler
272)
273{
274   *old_handler = _ISR_Vector_table[ vector ];
275
276   /*
277    *  If the interrupt vector table is a table of pointer to isr entry
278    *  points, then we need to install the appropriate RTEMS interrupt
279    *  handler for this vector number.
280    */
281
282   /*
283    *  We put the actual user ISR address in '_ISR_vector_table'.  This will
284    *  be used by the _CPU_ISR_Handler so the user gets control.
285    */
286
287    _ISR_Vector_table[ vector ] = new_handler;
288}
289
290/*PAGE
291 *
292 *  _CPU_Install_interrupt_stack
293 */
294
295void _CPU_Install_interrupt_stack( void )
296{
297}
298
299/*PAGE
300 *
301 *  _CPU_Internal_threads_Idle_thread_body
302 *
303 *  NOTES:
304 *
305 *  1. This is the same as the regular CPU independent algorithm.
306 *
307 *  2. If you implement this using a "halt", "idle", or "shutdown"
308 *     instruction, then don't forget to put it in an infinite loop.
309 *
310 *  3. Be warned. Some processors with onboard DMA have been known
311 *     to stop the DMA if the CPU were put in IDLE mode.  This might
312 *     also be a problem with other on-chip peripherals.  So use this
313 *     hook with caution.
314 */
315
316void _CPU_Internal_threads_Idle_thread_body( void )
317{
318  while (1)
319    pause();
320}
321
322/*PAGE
323 *
324 *  _CPU_Context_Initialize
325 */
326
327void _CPU_Context_Initialize(
328  Context_Control  *_the_context,
329  unsigned32       *_stack_base,
330  unsigned32        _size,
331  unsigned32        _new_level,
332  void             *_entry_point
333)
334{
335  void        *source;
336  unsigned32  *addr;
337  unsigned32   jmp_addr;
338  unsigned32   _stack_low;   /* lowest "stack aligned" address */
339  unsigned32   _stack_high;  /* highest "stack aligned" address */
340  unsigned32   _the_size;
341
342  jmp_addr = (unsigned32) _entry_point;
343
344  /*
345   *  On CPUs with stacks which grow down, we build the stack
346   *  based on the _stack_high address.  On CPUs with stacks which
347   *  grow up, we build the stack based on the _stack_low address. 
348   */
349
350  _stack_low = ((unsigned32)(_stack_base) + CPU_STACK_ALIGNMENT);
351  _stack_low &= ~(CPU_STACK_ALIGNMENT - 1);
352
353  _stack_high = ((unsigned32)(_stack_base) + _size);
354  _stack_high &= ~(CPU_STACK_ALIGNMENT - 1);
355
356  _the_size = _size & ~(CPU_STACK_ALIGNMENT - 1);
357
358  /*
359   * Slam our jmp_buf template into the context we are creating
360   */
361
362  if ( _new_level == 0 )
363    source = _CPU_Context_Default_with_ISRs_enabled.regs;
364  else
365    source = _CPU_Context_Default_with_ISRs_disabled.regs;
366     
367  memcpy(_the_context, source, sizeof(jmp_buf));
368
369  addr = (unsigned32 *)_the_context;
370
371#if defined(hppa1_1)
372  *(addr + RP_OFF) = jmp_addr;
373  *(addr + SP_OFF) = (unsigned32)(_stack_low + CPU_FRAME_SIZE);
374
375  /*
376   * See if we are using shared libraries by checking
377   * bit 30 in 24 off of newp. If bit 30 is set then
378   * we are using shared libraries and the jump address
379   * is at what 24 off of newp points to so shove that
380   * into 24 off of newp instead.
381   */
382
383  if (jmp_addr & 0x40000000) {
384    jmp_addr &= 0xfffffffc;
385     *(addr + RP_OFF) = (unsigned32)*(unsigned32 *)jmp_addr;
386  }
387#elif defined(sparc)
388
389  /*
390   *  See /usr/include/sys/stack.h in Solaris 2.3 for a nice
391   *  diagram of the stack.
392   */
393
394  asm ("ta  0x03");            /* flush registers */
395
396  *(addr + RP_OFF) = jmp_addr + ADDR_ADJ_OFFSET;
397  *(addr + SP_OFF) = (unsigned32)(_stack_high - CPU_FRAME_SIZE);
398  *(addr + FP_OFF) = (unsigned32)(_stack_high);
399
400#elif defined(i386)
401 
402    /*
403     *  This information was gathered by disassembling setjmp().
404     */
405
406    {
407      unsigned32 stack_ptr;
408
409      stack_ptr = _stack_high - CPU_FRAME_SIZE;
410
411      *(addr + EBX_OFF) = 0xFEEDFEED;
412      *(addr + ESI_OFF) = 0xDEADDEAD;
413      *(addr + EDI_OFF) = 0xDEAFDEAF;
414      *(addr + EBP_OFF) = stack_ptr;
415      *(addr + ESP_OFF) = stack_ptr;
416      *(addr + RET_OFF) = jmp_addr;
417 
418      addr = (unsigned32 *) stack_ptr;
419 
420      addr[ 0 ] = jmp_addr;
421      addr[ 1 ] = (unsigned32) stack_ptr;
422      addr[ 2 ] = (unsigned32) stack_ptr;
423    }
424
425#else
426#error "UNKNOWN CPU!!!"
427#endif
428
429}
430
431/*PAGE
432 *
433 *  _CPU_Context_restore
434 */
435
436void _CPU_Context_restore(
437  Context_Control  *next
438)
439{
440  sigprocmask( SIG_SETMASK, &next->isr_level, 0 );
441  longjmp( next->regs, 0 );
442}
443
444/*PAGE
445 *
446 *  _CPU_Context_switch
447 */
448
449void _CPU_Context_switch(
450  Context_Control  *current,
451  Context_Control  *next
452)
453{
454  /*
455   *  Switch levels in one operation
456   */
457
458  sigprocmask( SIG_SETMASK, &next->isr_level, &current->isr_level );
459
460  if (setjmp(current->regs) == 0) {    /* Save the current context */
461     longjmp(next->regs, 0);           /* Switch to the new context */
462  }
463}
464 
465/*PAGE
466 *
467 *  _CPU_Save_float_context
468 */
469
470void _CPU_Save_float_context(
471  Context_Control_fp *fp_context
472)
473{
474}
475
476/*PAGE
477 *
478 *  _CPU_Restore_float_context
479 */
480
481void _CPU_Restore_float_context(
482  Context_Control_fp *fp_context
483)
484{
485}
486
487/*PAGE
488 *
489 *  _CPU_ISR_Disable_support
490 */
491
492unsigned32 _CPU_ISR_Disable_support(void)
493{
494  sigset_t  old_mask;
495  sigset_t  empty_mask;
496
497  sigemptyset(&empty_mask);
498  sigemptyset(&old_mask);
499  sigprocmask(SIG_BLOCK, &_CPU_Signal_mask, &old_mask);
500
501  if (memcmp((char *)&empty_mask, (char *)&old_mask, sizeof(sigset_t)) != 0)
502    return 1;
503
504  return 0;
505}
506
507/*PAGE
508 *
509 *  _CPU_ISR_Enable
510 */
511
512void _CPU_ISR_Enable(
513  unsigned32 level
514)
515{
516  if (level == 0)
517    sigprocmask(SIG_UNBLOCK, &_CPU_Signal_mask, 0);
518  else
519    sigprocmask(SIG_BLOCK, &_CPU_Signal_mask, 0);
520}
521
522/*PAGE
523 *
524 *  _CPU_ISR_Handler
525 *
526 *  External interrupt handler.
527 *  This is installed as a UNIX signal handler.
528 *  It vectors out to specific user interrupt handlers.
529 */
530
531void _CPU_ISR_Handler(int vector)
532{
533  extern void        _Thread_Dispatch(void);
534  extern unsigned32  _Thread_Dispatch_disable_level;
535  extern boolean     _Context_Switch_necessary;
536
537
538  if (_ISR_Nest_level++ == 0) {
539      /* switch to interrupt stack */
540  }
541
542  _Thread_Dispatch_disable_level++;
543
544  if (_ISR_Vector_table[vector]) {
545     _ISR_Vector_table[vector](vector);
546  } else {
547     _CPU_Stray_signal(vector);
548  }
549
550  if (_ISR_Nest_level-- == 0) {
551      /* switch back to original stack */
552  }
553
554  _Thread_Dispatch_disable_level--;
555
556  if (_Thread_Dispatch_disable_level == 0 &&
557      (_Context_Switch_necessary || _ISR_Signals_to_thread_executing)) {
558      _CPU_ISR_Enable(0);
559      _Thread_Dispatch();
560  }
561}
562
563/*PAGE
564 *
565 *  _CPU_Stray_signal
566 */
567
568void _CPU_Stray_signal(int sig_num)
569{
570  char buffer[ 80 ];   
571
572  /*
573   *  We avoid using the stdio section of the library.
574   *  The following is generally safe.
575   */
576
577  write( 
578    2,
579    buffer, 
580    sprintf( buffer, "Stray signal %d\n", sig_num )
581  );
582 
583  /*
584   * If it was a "fatal" signal, then exit here
585   * If app code has installed a hander for one of these, then
586   * we won't call _CPU_Stray_signal, so this is ok.
587   */
588 
589  switch (sig_num) {
590      case SIGINT:
591      case SIGHUP:
592      case SIGQUIT:
593      case SIGILL:
594#ifdef SIGEMT
595      case SIGEMT:
596#endif
597      case SIGKILL:
598      case SIGBUS:
599      case SIGSEGV:
600      case SIGTERM:
601          _CPU_Fatal_error(0x100 + sig_num);
602  }
603}
604
605/*PAGE
606 *
607 *  _CPU_Fatal_error
608 */
609
610void _CPU_Fatal_error(unsigned32 error)
611{
612  setitimer(ITIMER_REAL, 0, 0);
613
614  _exit(error);
615}
616
617/*PAGE
618 *
619 *  _CPU_ffs
620 */
621
622int _CPU_ffs(unsigned32 value)
623{
624  int output;
625  extern int ffs( int );
626
627  output = ffs(value);
628  output = output - 1;
629
630  return output;
631}
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