[ac7d5ef0] | 1 | /* |
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| 2 | * HP PA-RISC CPU Dependent Source |
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| 3 | * |
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| 4 | * |
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| 5 | * To anyone who acknowledges that this file is provided "AS IS" |
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| 6 | * without any express or implied warranty: |
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| 7 | * permission to use, copy, modify, and distribute this file |
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| 8 | * for any purpose is hereby granted without fee, provided that |
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| 9 | * the above copyright notice and this notice appears in all |
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| 10 | * copies, and that the name of Division Incorporated not be |
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| 11 | * used in advertising or publicity pertaining to distribution |
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| 12 | * of the software without specific, written prior permission. |
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| 13 | * Division Incorporated makes no representations about the |
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| 14 | * suitability of this software for any purpose. |
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| 15 | * |
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| 16 | * $Id$ |
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| 17 | */ |
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| 18 | |
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| 19 | #include <rtems/system.h> |
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| 20 | #include <rtems/isr.h> |
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| 21 | |
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| 22 | #include <stdio.h> |
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| 23 | #include <stdlib.h> |
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| 24 | #include <unistd.h> |
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| 25 | #include <signal.h> |
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| 26 | #include <time.h> |
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| 27 | |
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[637df35] | 28 | #ifndef SA_RESTART |
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| 29 | #define SA_RESTART 0 |
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| 30 | #endif |
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[ac7d5ef0] | 31 | |
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[637df35] | 32 | void _CPU_Signal_initialize(void); |
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| 33 | void _CPU_Stray_signal(int); |
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| 34 | void _CPU_ISR_Handler(int); |
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[ac7d5ef0] | 35 | |
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[637df35] | 36 | sigset_t _CPU_Signal_mask; |
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| 37 | Context_Control _CPU_Context_Default_with_ISRs_enabled; |
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| 38 | Context_Control _CPU_Context_Default_with_ISRs_disabled; |
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[ac7d5ef0] | 39 | |
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| 40 | /* |
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| 41 | * Which cpu are we? Used by libcpu and libbsp. |
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| 42 | */ |
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| 43 | |
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| 44 | int cpu_number; |
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| 45 | |
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[637df35] | 46 | /*PAGE |
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| 47 | * |
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| 48 | * _CPU_ISR_From_CPU_Init |
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| 49 | */ |
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| 50 | |
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| 51 | void _CPU_ISR_From_CPU_Init() |
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| 52 | { |
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| 53 | unsigned32 i; |
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| 54 | proc_ptr old_handler; |
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| 55 | |
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| 56 | |
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| 57 | /* |
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| 58 | * Block all the signals except SIGTRAP for the debugger |
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| 59 | * and SIGABRT for fatal errors. |
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| 60 | */ |
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| 61 | |
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| 62 | _CPU_ISR_Enable(1); |
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| 63 | |
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| 64 | (void) sigfillset(&_CPU_Signal_mask); |
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| 65 | (void) sigdelset(&_CPU_Signal_mask, SIGTRAP); |
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| 66 | (void) sigdelset(&_CPU_Signal_mask, SIGABRT); |
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| 67 | (void) sigdelset(&_CPU_Signal_mask, SIGIOT); |
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| 68 | (void) sigdelset(&_CPU_Signal_mask, SIGCONT); |
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| 69 | |
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| 70 | sigprocmask(SIG_BLOCK, &_CPU_Signal_mask, 0); |
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| 71 | |
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| 72 | /* |
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| 73 | * Set the handler for all signals to be signal_handler |
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| 74 | * which will then vector out to the correct handler |
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| 75 | * for whichever signal actually happened. Initially |
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| 76 | * set the vectors to the stray signal handler. |
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| 77 | */ |
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| 78 | |
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| 79 | for (i = 0; i < CPU_INTERRUPT_NUMBER_OF_VECTORS; i++) |
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| 80 | (void)_CPU_ISR_install_vector(i, _CPU_Stray_signal, &old_handler); |
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| 81 | |
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| 82 | _CPU_Signal_initialize(); |
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| 83 | } |
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| 84 | |
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| 85 | void _CPU_Signal_initialize( void ) |
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| 86 | { |
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| 87 | struct sigaction act; |
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| 88 | sigset_t mask; |
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| 89 | |
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| 90 | /* mark them all active except for TraceTrap and Abort */ |
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| 91 | |
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| 92 | sigfillset(&mask); |
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| 93 | sigdelset(&mask, SIGTRAP); |
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| 94 | sigdelset(&mask, SIGABRT); |
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| 95 | sigdelset(&mask, SIGIOT); |
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| 96 | sigdelset(&mask, SIGCONT); |
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| 97 | sigprocmask(SIG_UNBLOCK, &mask, 0); |
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| 98 | |
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| 99 | act.sa_handler = _CPU_ISR_Handler; |
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| 100 | act.sa_mask = mask; |
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| 101 | act.sa_flags = SA_RESTART; |
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| 102 | |
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| 103 | sigaction(SIGHUP, &act, 0); |
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| 104 | sigaction(SIGINT, &act, 0); |
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| 105 | sigaction(SIGQUIT, &act, 0); |
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| 106 | sigaction(SIGILL, &act, 0); |
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| 107 | sigaction(SIGEMT, &act, 0); |
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| 108 | sigaction(SIGFPE, &act, 0); |
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| 109 | sigaction(SIGKILL, &act, 0); |
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| 110 | sigaction(SIGBUS, &act, 0); |
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| 111 | sigaction(SIGSEGV, &act, 0); |
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| 112 | sigaction(SIGSYS, &act, 0); |
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| 113 | sigaction(SIGPIPE, &act, 0); |
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| 114 | sigaction(SIGALRM, &act, 0); |
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| 115 | sigaction(SIGTERM, &act, 0); |
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| 116 | sigaction(SIGUSR1, &act, 0); |
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| 117 | sigaction(SIGUSR2, &act, 0); |
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| 118 | sigaction(SIGCHLD, &act, 0); |
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| 119 | sigaction(SIGCLD, &act, 0); |
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| 120 | sigaction(SIGPWR, &act, 0); |
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| 121 | sigaction(SIGVTALRM, &act, 0); |
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| 122 | sigaction(SIGPROF, &act, 0); |
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| 123 | sigaction(SIGIO, &act, 0); |
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| 124 | sigaction(SIGWINCH, &act, 0); |
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| 125 | sigaction(SIGSTOP, &act, 0); |
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| 126 | sigaction(SIGTTIN, &act, 0); |
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| 127 | sigaction(SIGTTOU, &act, 0); |
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| 128 | sigaction(SIGURG, &act, 0); |
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| 129 | /* |
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| 130 | * XXX: Really should be on HPUX. |
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| 131 | */ |
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| 132 | |
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| 133 | #if defined(hppa1_1) |
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| 134 | sigaction(SIGLOST, &act, 0); |
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| 135 | #endif |
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| 136 | |
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| 137 | } |
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| 138 | |
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| 139 | /*PAGE |
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| 140 | * |
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| 141 | * _CPU_Context_From_CPU_Init |
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| 142 | */ |
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| 143 | |
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| 144 | void _CPU_Context_From_CPU_Init() |
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| 145 | { |
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| 146 | |
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| 147 | #if defined(hppa1_1) && defined(RTEMS_UNIXLIB) |
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| 148 | /* |
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| 149 | * HACK - set the _SYSTEM_ID to 0x20c so that setjmp/longjmp |
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| 150 | * will handle the full 32 floating point registers. |
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| 151 | * |
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| 152 | * NOTE: Is this a bug in HPUX9? |
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| 153 | */ |
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| 154 | |
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| 155 | { |
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| 156 | extern unsigned32 _SYSTEM_ID; |
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| 157 | |
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| 158 | _SYSTEM_ID = 0x20c; |
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| 159 | } |
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| 160 | #endif |
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| 161 | |
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| 162 | /* |
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| 163 | * get default values to use in _CPU_Context_Initialize() |
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| 164 | */ |
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| 165 | |
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| 166 | _CPU_ISR_Set_level( 0 ); |
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| 167 | setjmp( _CPU_Context_Default_with_ISRs_enabled.regs ); |
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| 168 | sigprocmask( |
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| 169 | SIG_SETMASK, /* ignored when second arg is NULL */ |
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| 170 | 0, |
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| 171 | &_CPU_Context_Default_with_ISRs_enabled.isr_level |
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| 172 | ); |
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| 173 | |
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| 174 | _CPU_ISR_Set_level( 1 ); |
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| 175 | setjmp( _CPU_Context_Default_with_ISRs_disabled.regs ); |
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| 176 | sigprocmask( |
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| 177 | SIG_SETMASK, /* ignored when second arg is NULL */ |
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| 178 | 0, |
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| 179 | &_CPU_Context_Default_with_ISRs_disabled.isr_level |
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| 180 | ); |
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| 181 | |
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| 182 | } |
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| 183 | |
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[ac7d5ef0] | 184 | /* _CPU_Initialize |
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| 185 | * |
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| 186 | * This routine performs processor dependent initialization. |
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| 187 | * |
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| 188 | * INPUT PARAMETERS: |
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| 189 | * cpu_table - CPU table to initialize |
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| 190 | * thread_dispatch - address of disptaching routine |
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| 191 | */ |
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| 192 | |
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| 193 | |
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| 194 | void _CPU_Initialize( |
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| 195 | rtems_cpu_table *cpu_table, |
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| 196 | void (*thread_dispatch) /* ignored on this CPU */ |
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| 197 | ) |
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| 198 | { |
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| 199 | if ( cpu_table == NULL ) |
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[637df35] | 200 | _CPU_Fatal_halt( RTEMS_NOT_CONFIGURED ); |
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[ac7d5ef0] | 201 | |
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| 202 | /* |
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| 203 | * The thread_dispatch argument is the address of the entry point |
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| 204 | * for the routine called at the end of an ISR once it has been |
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| 205 | * decided a context switch is necessary. On some compilation |
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| 206 | * systems it is difficult to call a high-level language routine |
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| 207 | * from assembly. This allows us to trick these systems. |
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| 208 | * |
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| 209 | * If you encounter this problem save the entry point in a CPU |
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| 210 | * dependent variable. |
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| 211 | */ |
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| 212 | |
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| 213 | _CPU_Thread_dispatch_pointer = thread_dispatch; |
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| 214 | |
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| 215 | /* |
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| 216 | * XXX; If there is not an easy way to initialize the FP context |
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| 217 | * during Context_Initialize, then it is usually easier to |
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| 218 | * save an "uninitialized" FP context here and copy it to |
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| 219 | * the task's during Context_Initialize. |
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| 220 | */ |
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| 221 | |
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| 222 | /* XXX: FP context initialization support */ |
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| 223 | |
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| 224 | _CPU_Table = *cpu_table; |
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| 225 | |
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[637df35] | 226 | _CPU_ISR_From_CPU_Init(); |
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[ac7d5ef0] | 227 | |
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[637df35] | 228 | _CPU_Context_From_CPU_Init(); |
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[ac7d5ef0] | 229 | |
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[637df35] | 230 | } |
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[ac7d5ef0] | 231 | |
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[637df35] | 232 | /*PAGE |
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| 233 | * |
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| 234 | * _CPU_ISR_install_raw_handler |
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| 235 | */ |
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[ac7d5ef0] | 236 | |
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[637df35] | 237 | void _CPU_ISR_install_raw_handler( |
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| 238 | unsigned32 vector, |
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| 239 | proc_ptr new_handler, |
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| 240 | proc_ptr *old_handler |
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| 241 | ) |
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| 242 | { |
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| 243 | _CPU_Fatal_halt( 0xdeaddead ); |
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[ac7d5ef0] | 244 | } |
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| 245 | |
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[637df35] | 246 | /*PAGE |
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| 247 | * |
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| 248 | * _CPU_ISR_install_vector |
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[ac7d5ef0] | 249 | * |
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| 250 | * This kernel routine installs the RTEMS handler for the |
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| 251 | * specified vector. |
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| 252 | * |
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| 253 | * Input parameters: |
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| 254 | * vector - interrupt vector number |
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| 255 | * old_handler - former ISR for this vector number |
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| 256 | * new_handler - replacement ISR for this vector number |
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| 257 | * |
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| 258 | * Output parameters: NONE |
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| 259 | * |
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| 260 | */ |
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| 261 | |
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| 262 | |
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| 263 | void _CPU_ISR_install_vector( |
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| 264 | unsigned32 vector, |
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| 265 | proc_ptr new_handler, |
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| 266 | proc_ptr *old_handler |
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| 267 | ) |
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| 268 | { |
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| 269 | *old_handler = _ISR_Vector_table[ vector ]; |
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| 270 | |
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| 271 | /* |
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| 272 | * If the interrupt vector table is a table of pointer to isr entry |
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| 273 | * points, then we need to install the appropriate RTEMS interrupt |
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| 274 | * handler for this vector number. |
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| 275 | */ |
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| 276 | |
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| 277 | /* |
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| 278 | * We put the actual user ISR address in '_ISR_vector_table'. This will |
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[637df35] | 279 | * be used by the _CPU_ISR_Handler so the user gets control. |
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[ac7d5ef0] | 280 | */ |
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| 281 | |
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| 282 | _ISR_Vector_table[ vector ] = new_handler; |
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| 283 | } |
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| 284 | |
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| 285 | /*PAGE |
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| 286 | * |
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| 287 | * _CPU_Install_interrupt_stack |
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| 288 | */ |
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| 289 | |
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| 290 | void _CPU_Install_interrupt_stack( void ) |
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| 291 | { |
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| 292 | } |
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| 293 | |
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| 294 | /*PAGE |
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| 295 | * |
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| 296 | * _CPU_Internal_threads_Idle_thread_body |
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| 297 | * |
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| 298 | * NOTES: |
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| 299 | * |
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| 300 | * 1. This is the same as the regular CPU independent algorithm. |
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| 301 | * |
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| 302 | * 2. If you implement this using a "halt", "idle", or "shutdown" |
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| 303 | * instruction, then don't forget to put it in an infinite loop. |
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| 304 | * |
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| 305 | * 3. Be warned. Some processors with onboard DMA have been known |
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| 306 | * to stop the DMA if the CPU were put in IDLE mode. This might |
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| 307 | * also be a problem with other on-chip peripherals. So use this |
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| 308 | * hook with caution. |
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| 309 | */ |
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| 310 | |
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| 311 | void _CPU_Internal_threads_Idle_thread_body( void ) |
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| 312 | { |
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[637df35] | 313 | while (1) |
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| 314 | pause(); |
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[ac7d5ef0] | 315 | } |
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| 316 | |
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[637df35] | 317 | /*PAGE |
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| 318 | * |
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| 319 | * _CPU_Context_Initialize |
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| 320 | */ |
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| 321 | |
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[ac7d5ef0] | 322 | void _CPU_Context_Initialize( |
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| 323 | Context_Control *_the_context, |
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| 324 | unsigned32 *_stack_base, |
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| 325 | unsigned32 _size, |
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| 326 | unsigned32 _new_level, |
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[88d594a] | 327 | void *_entry_point |
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[ac7d5ef0] | 328 | ) |
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| 329 | { |
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[637df35] | 330 | void *source; |
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| 331 | unsigned32 *addr; |
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| 332 | unsigned32 jmp_addr; |
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| 333 | unsigned32 _stack_low; /* lowest "stack aligned" address */ |
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| 334 | unsigned32 _stack_high; /* highest "stack aligned" address */ |
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| 335 | unsigned32 _the_size; |
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[ac7d5ef0] | 336 | |
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[637df35] | 337 | jmp_addr = (unsigned32) _entry_point; |
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[ac7d5ef0] | 338 | |
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[637df35] | 339 | /* |
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| 340 | * On CPUs with stacks which grow down, we build the stack |
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| 341 | * based on the _stack_high address. On CPUs with stacks which |
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| 342 | * grow up, we build the stack based on the _stack_low address. |
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| 343 | */ |
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[88d594a] | 344 | |
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[637df35] | 345 | _stack_low = ((unsigned32)(_stack_base) + CPU_STACK_ALIGNMENT); |
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| 346 | _stack_low &= ~(CPU_STACK_ALIGNMENT - 1); |
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[88d594a] | 347 | |
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[637df35] | 348 | _stack_high = ((unsigned32)(_stack_base) + _size); |
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| 349 | _stack_high &= ~(CPU_STACK_ALIGNMENT - 1); |
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[ac7d5ef0] | 350 | |
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[637df35] | 351 | _the_size = _size & ~(CPU_STACK_ALIGNMENT - 1); |
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[ac7d5ef0] | 352 | |
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[637df35] | 353 | /* |
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| 354 | * Slam our jmp_buf template into the context we are creating |
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| 355 | */ |
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[ac7d5ef0] | 356 | |
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[637df35] | 357 | if ( _new_level == 0 ) |
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| 358 | source = _CPU_Context_Default_with_ISRs_enabled.regs; |
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| 359 | else |
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| 360 | source = _CPU_Context_Default_with_ISRs_disabled.regs; |
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| 361 | |
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| 362 | memcpy(_the_context, source, sizeof(jmp_buf)); |
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[ac7d5ef0] | 363 | |
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[637df35] | 364 | addr = (unsigned32 *)_the_context; |
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[ac7d5ef0] | 365 | |
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| 366 | #if defined(hppa1_1) |
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[637df35] | 367 | *(addr + RP_OFF) = jmp_addr; |
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| 368 | *(addr + SP_OFF) = (unsigned32)(_stack_low + CPU_FRAME_SIZE); |
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[ac7d5ef0] | 369 | |
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[637df35] | 370 | /* |
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| 371 | * See if we are using shared libraries by checking |
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| 372 | * bit 30 in 24 off of newp. If bit 30 is set then |
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| 373 | * we are using shared libraries and the jump address |
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| 374 | * is at what 24 off of newp points to so shove that |
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| 375 | * into 24 off of newp instead. |
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| 376 | */ |
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[ac7d5ef0] | 377 | |
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[637df35] | 378 | if (jmp_addr & 0x40000000) { |
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| 379 | jmp_addr &= 0xfffffffc; |
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| 380 | *(addr + RP_OFF) = (unsigned32)*(unsigned32 *)jmp_addr; |
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| 381 | } |
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[ac7d5ef0] | 382 | #elif defined(sparc) |
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| 383 | |
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[637df35] | 384 | /* |
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| 385 | * See /usr/include/sys/stack.h in Solaris 2.3 for a nice |
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| 386 | * diagram of the stack. |
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| 387 | */ |
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[ac7d5ef0] | 388 | |
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[637df35] | 389 | asm ("ta 0x03"); /* flush registers */ |
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[ac7d5ef0] | 390 | |
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[637df35] | 391 | *(addr + RP_OFF) = jmp_addr + ADDR_ADJ_OFFSET; |
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| 392 | *(addr + SP_OFF) = (unsigned32)(_stack_high - CPU_FRAME_SIZE); |
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| 393 | *(addr + FP_OFF) = (unsigned32)(_stack_high); |
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[ac7d5ef0] | 394 | #else |
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| 395 | #error "UNKNOWN CPU!!!" |
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| 396 | #endif |
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| 397 | |
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| 398 | } |
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| 399 | |
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[637df35] | 400 | /*PAGE |
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| 401 | * |
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| 402 | * _CPU_Context_restore |
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| 403 | */ |
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| 404 | |
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[ac7d5ef0] | 405 | void _CPU_Context_restore( |
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| 406 | Context_Control *next |
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| 407 | ) |
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| 408 | { |
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[637df35] | 409 | sigprocmask( SIG_SETMASK, &next->isr_level, 0 ); |
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| 410 | longjmp( next->regs, 0 ); |
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[ac7d5ef0] | 411 | } |
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| 412 | |
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[637df35] | 413 | /*PAGE |
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| 414 | * |
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| 415 | * _CPU_Context_switch |
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| 416 | */ |
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| 417 | |
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[ac7d5ef0] | 418 | void _CPU_Context_switch( |
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| 419 | Context_Control *current, |
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| 420 | Context_Control *next |
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| 421 | ) |
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| 422 | { |
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[637df35] | 423 | /* |
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| 424 | * Switch levels in one operation |
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| 425 | */ |
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[ac7d5ef0] | 426 | |
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[637df35] | 427 | sigprocmask( SIG_SETMASK, &next->isr_level, ¤t->isr_level ); |
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[ac7d5ef0] | 428 | |
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[637df35] | 429 | if (setjmp(current->regs) == 0) { /* Save the current context */ |
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| 430 | longjmp(next->regs, 0); /* Switch to the new context */ |
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| 431 | } |
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[ac7d5ef0] | 432 | } |
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[637df35] | 433 | |
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| 434 | /*PAGE |
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| 435 | * |
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| 436 | * _CPU_Save_float_context |
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| 437 | */ |
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[ac7d5ef0] | 438 | |
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| 439 | void _CPU_Save_float_context( |
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| 440 | Context_Control_fp *fp_context |
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| 441 | ) |
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| 442 | { |
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| 443 | } |
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| 444 | |
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[637df35] | 445 | /*PAGE |
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| 446 | * |
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| 447 | * _CPU_Restore_float_context |
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| 448 | */ |
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| 449 | |
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[ac7d5ef0] | 450 | void _CPU_Restore_float_context( |
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| 451 | Context_Control_fp *fp_context |
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| 452 | ) |
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| 453 | { |
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| 454 | } |
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| 455 | |
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[637df35] | 456 | /*PAGE |
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| 457 | * |
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| 458 | * _CPU_ISR_Disable_support |
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| 459 | */ |
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[ac7d5ef0] | 460 | |
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[637df35] | 461 | unsigned32 _CPU_ISR_Disable_support(void) |
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[ac7d5ef0] | 462 | { |
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[637df35] | 463 | sigset_t old_mask; |
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| 464 | sigset_t empty_mask; |
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[ac7d5ef0] | 465 | |
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[637df35] | 466 | sigemptyset(&empty_mask); |
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| 467 | sigemptyset(&old_mask); |
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| 468 | sigprocmask(SIG_BLOCK, &_CPU_Signal_mask, &old_mask); |
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[ac7d5ef0] | 469 | |
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[637df35] | 470 | if (memcmp((char *)&empty_mask, (char *)&old_mask, sizeof(sigset_t)) != 0) |
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| 471 | return 1; |
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[ac7d5ef0] | 472 | |
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[637df35] | 473 | return 0; |
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[ac7d5ef0] | 474 | } |
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| 475 | |
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[637df35] | 476 | /*PAGE |
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| 477 | * |
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| 478 | * _CPU_ISR_Enable |
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| 479 | */ |
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[ac7d5ef0] | 480 | |
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[637df35] | 481 | void _CPU_ISR_Enable( |
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| 482 | unsigned32 level |
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| 483 | ) |
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[ac7d5ef0] | 484 | { |
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[637df35] | 485 | if (level == 0) |
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| 486 | sigprocmask(SIG_UNBLOCK, &_CPU_Signal_mask, 0); |
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| 487 | else |
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| 488 | sigprocmask(SIG_BLOCK, &_CPU_Signal_mask, 0); |
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[ac7d5ef0] | 489 | } |
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| 490 | |
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[637df35] | 491 | /*PAGE |
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[ac7d5ef0] | 492 | * |
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[637df35] | 493 | * _CPU_ISR_Handler |
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| 494 | * |
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| 495 | * External interrupt handler. |
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| 496 | * This is installed as a UNIX signal handler. |
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| 497 | * It vectors out to specific user interrupt handlers. |
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[ac7d5ef0] | 498 | */ |
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| 499 | |
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[637df35] | 500 | void _CPU_ISR_Handler(int vector) |
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[ac7d5ef0] | 501 | { |
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[637df35] | 502 | extern void _Thread_Dispatch(void); |
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| 503 | extern unsigned32 _Thread_Dispatch_disable_level; |
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| 504 | extern boolean _Context_Switch_necessary; |
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[ac7d5ef0] | 505 | |
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| 506 | |
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[637df35] | 507 | if (_ISR_Nest_level++ == 0) { |
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| 508 | /* switch to interrupt stack */ |
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| 509 | } |
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[ac7d5ef0] | 510 | |
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[637df35] | 511 | _Thread_Dispatch_disable_level++; |
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[ac7d5ef0] | 512 | |
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[637df35] | 513 | if (_ISR_Vector_table[vector]) { |
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| 514 | _ISR_Vector_table[vector](vector); |
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| 515 | } else { |
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| 516 | _CPU_Stray_signal(vector); |
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| 517 | } |
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[ac7d5ef0] | 518 | |
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[637df35] | 519 | if (_ISR_Nest_level-- == 0) { |
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| 520 | /* switch back to original stack */ |
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| 521 | } |
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[ac7d5ef0] | 522 | |
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[637df35] | 523 | _Thread_Dispatch_disable_level--; |
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[ac7d5ef0] | 524 | |
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[637df35] | 525 | if (_Thread_Dispatch_disable_level == 0 && |
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| 526 | (_Context_Switch_necessary || _ISR_Signals_to_thread_executing)) { |
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| 527 | _CPU_ISR_Enable(0); |
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| 528 | _Thread_Dispatch(); |
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| 529 | } |
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[ac7d5ef0] | 530 | } |
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| 531 | |
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[637df35] | 532 | /*PAGE |
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| 533 | * |
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| 534 | * _CPU_Stray_signal |
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| 535 | */ |
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[ac7d5ef0] | 536 | |
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[637df35] | 537 | void _CPU_Stray_signal(int sig_num) |
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[ac7d5ef0] | 538 | { |
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[637df35] | 539 | char buffer[ 80 ]; |
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[ac7d5ef0] | 540 | |
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[637df35] | 541 | /* |
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| 542 | * We avoid using the stdio section of the library. |
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| 543 | * The following is generally safe. |
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| 544 | */ |
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[ac7d5ef0] | 545 | |
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[637df35] | 546 | write( |
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| 547 | 2, |
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| 548 | buffer, |
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| 549 | sprintf( buffer, "Stray signal %d\n", sig_num ) |
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| 550 | ); |
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[ac7d5ef0] | 551 | |
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[637df35] | 552 | /* |
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| 553 | * If it was a "fatal" signal, then exit here |
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| 554 | * If app code has installed a hander for one of these, then |
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| 555 | * we won't call _CPU_Stray_signal, so this is ok. |
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| 556 | */ |
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[ac7d5ef0] | 557 | |
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[637df35] | 558 | switch (sig_num) { |
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| 559 | case SIGINT: |
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| 560 | case SIGHUP: |
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| 561 | case SIGQUIT: |
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| 562 | case SIGILL: |
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| 563 | case SIGEMT: |
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| 564 | case SIGKILL: |
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| 565 | case SIGBUS: |
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| 566 | case SIGSEGV: |
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| 567 | case SIGTERM: |
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| 568 | _CPU_Fatal_error(0x100 + sig_num); |
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| 569 | } |
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[ac7d5ef0] | 570 | } |
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| 571 | |
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[637df35] | 572 | /*PAGE |
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| 573 | * |
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| 574 | * _CPU_Fatal_error |
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| 575 | */ |
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[ac7d5ef0] | 576 | |
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[637df35] | 577 | void _CPU_Fatal_error(unsigned32 error) |
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[ac7d5ef0] | 578 | { |
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[637df35] | 579 | setitimer(ITIMER_REAL, 0, 0); |
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[ac7d5ef0] | 580 | |
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[637df35] | 581 | _exit(error); |
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[ac7d5ef0] | 582 | } |
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| 583 | |
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[637df35] | 584 | /*PAGE |
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| 585 | * |
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| 586 | * _CPU_ffs |
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| 587 | */ |
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| 588 | |
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| 589 | int _CPU_ffs(unsigned32 value) |
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[ac7d5ef0] | 590 | { |
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[637df35] | 591 | int output; |
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| 592 | extern int ffs( int ); |
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[ac7d5ef0] | 593 | |
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[637df35] | 594 | output = ffs(value); |
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| 595 | output = output - 1; |
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[ac7d5ef0] | 596 | |
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[637df35] | 597 | return output; |
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[ac7d5ef0] | 598 | } |
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