[ac7d5ef0] | 1 | /* |
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[3652ad35] | 2 | * UNIX Simulator Dependent Source |
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[ac7d5ef0] | 3 | * |
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| 4 | * |
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| 5 | * To anyone who acknowledges that this file is provided "AS IS" |
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| 6 | * without any express or implied warranty: |
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| 7 | * permission to use, copy, modify, and distribute this file |
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| 8 | * for any purpose is hereby granted without fee, provided that |
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| 9 | * the above copyright notice and this notice appears in all |
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| 10 | * copies, and that the name of Division Incorporated not be |
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| 11 | * used in advertising or publicity pertaining to distribution |
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| 12 | * of the software without specific, written prior permission. |
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| 13 | * Division Incorporated makes no representations about the |
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| 14 | * suitability of this software for any purpose. |
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| 15 | * |
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| 16 | * $Id$ |
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| 17 | */ |
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| 18 | |
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| 19 | #include <rtems/system.h> |
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[5e9b32b] | 20 | #include <rtems/score/isr.h> |
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| 21 | #include <rtems/score/interr.h> |
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[ac7d5ef0] | 22 | |
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| 23 | #include <stdio.h> |
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| 24 | #include <stdlib.h> |
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| 25 | #include <signal.h> |
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| 26 | #include <time.h> |
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[10aed1e3] | 27 | #include <sys/time.h> |
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[ac7d5ef0] | 28 | |
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[637df35] | 29 | #ifndef SA_RESTART |
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| 30 | #define SA_RESTART 0 |
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| 31 | #endif |
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[ac7d5ef0] | 32 | |
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[637df35] | 33 | void _CPU_Signal_initialize(void); |
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| 34 | void _CPU_Stray_signal(int); |
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| 35 | void _CPU_ISR_Handler(int); |
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[ac7d5ef0] | 36 | |
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[637df35] | 37 | sigset_t _CPU_Signal_mask; |
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| 38 | Context_Control _CPU_Context_Default_with_ISRs_enabled; |
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| 39 | Context_Control _CPU_Context_Default_with_ISRs_disabled; |
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[ac7d5ef0] | 40 | |
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| 41 | /* |
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| 42 | * Which cpu are we? Used by libcpu and libbsp. |
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| 43 | */ |
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| 44 | |
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| 45 | int cpu_number; |
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| 46 | |
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[637df35] | 47 | /*PAGE |
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| 48 | * |
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| 49 | * _CPU_ISR_From_CPU_Init |
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| 50 | */ |
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| 51 | |
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[e7e016f] | 52 | sigset_t posix_empty_mask; |
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| 53 | |
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[637df35] | 54 | void _CPU_ISR_From_CPU_Init() |
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| 55 | { |
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| 56 | unsigned32 i; |
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| 57 | proc_ptr old_handler; |
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| 58 | |
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[e7e016f] | 59 | /* |
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| 60 | * Generate an empty mask to be used by disable_support |
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| 61 | */ |
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[637df35] | 62 | |
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[e7e016f] | 63 | sigemptyset(&posix_empty_mask); |
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| 64 | |
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[637df35] | 65 | /* |
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| 66 | * Block all the signals except SIGTRAP for the debugger |
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| 67 | * and SIGABRT for fatal errors. |
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| 68 | */ |
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| 69 | |
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| 70 | (void) sigfillset(&_CPU_Signal_mask); |
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| 71 | (void) sigdelset(&_CPU_Signal_mask, SIGTRAP); |
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| 72 | (void) sigdelset(&_CPU_Signal_mask, SIGABRT); |
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| 73 | (void) sigdelset(&_CPU_Signal_mask, SIGIOT); |
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| 74 | (void) sigdelset(&_CPU_Signal_mask, SIGCONT); |
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| 75 | |
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[e7e016f] | 76 | _CPU_ISR_Enable(1); |
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[637df35] | 77 | |
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| 78 | /* |
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| 79 | * Set the handler for all signals to be signal_handler |
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| 80 | * which will then vector out to the correct handler |
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| 81 | * for whichever signal actually happened. Initially |
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| 82 | * set the vectors to the stray signal handler. |
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| 83 | */ |
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| 84 | |
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| 85 | for (i = 0; i < CPU_INTERRUPT_NUMBER_OF_VECTORS; i++) |
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| 86 | (void)_CPU_ISR_install_vector(i, _CPU_Stray_signal, &old_handler); |
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| 87 | |
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| 88 | _CPU_Signal_initialize(); |
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| 89 | } |
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| 90 | |
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| 91 | void _CPU_Signal_initialize( void ) |
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| 92 | { |
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| 93 | struct sigaction act; |
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| 94 | sigset_t mask; |
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| 95 | |
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| 96 | /* mark them all active except for TraceTrap and Abort */ |
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| 97 | |
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| 98 | sigfillset(&mask); |
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| 99 | sigdelset(&mask, SIGTRAP); |
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| 100 | sigdelset(&mask, SIGABRT); |
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| 101 | sigdelset(&mask, SIGIOT); |
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| 102 | sigdelset(&mask, SIGCONT); |
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| 103 | sigprocmask(SIG_UNBLOCK, &mask, 0); |
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| 104 | |
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| 105 | act.sa_handler = _CPU_ISR_Handler; |
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| 106 | act.sa_mask = mask; |
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| 107 | act.sa_flags = SA_RESTART; |
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| 108 | |
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| 109 | sigaction(SIGHUP, &act, 0); |
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| 110 | sigaction(SIGINT, &act, 0); |
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| 111 | sigaction(SIGQUIT, &act, 0); |
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| 112 | sigaction(SIGILL, &act, 0); |
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[10aed1e3] | 113 | #ifdef SIGEMT |
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[637df35] | 114 | sigaction(SIGEMT, &act, 0); |
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[10aed1e3] | 115 | #endif |
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[637df35] | 116 | sigaction(SIGFPE, &act, 0); |
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| 117 | sigaction(SIGKILL, &act, 0); |
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| 118 | sigaction(SIGBUS, &act, 0); |
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| 119 | sigaction(SIGSEGV, &act, 0); |
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[10aed1e3] | 120 | #ifdef SIGSYS |
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[637df35] | 121 | sigaction(SIGSYS, &act, 0); |
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[10aed1e3] | 122 | #endif |
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[637df35] | 123 | sigaction(SIGPIPE, &act, 0); |
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| 124 | sigaction(SIGALRM, &act, 0); |
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| 125 | sigaction(SIGTERM, &act, 0); |
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| 126 | sigaction(SIGUSR1, &act, 0); |
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| 127 | sigaction(SIGUSR2, &act, 0); |
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| 128 | sigaction(SIGCHLD, &act, 0); |
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| 129 | sigaction(SIGCLD, &act, 0); |
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| 130 | sigaction(SIGPWR, &act, 0); |
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| 131 | sigaction(SIGVTALRM, &act, 0); |
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| 132 | sigaction(SIGPROF, &act, 0); |
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| 133 | sigaction(SIGIO, &act, 0); |
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| 134 | sigaction(SIGWINCH, &act, 0); |
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| 135 | sigaction(SIGSTOP, &act, 0); |
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| 136 | sigaction(SIGTTIN, &act, 0); |
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| 137 | sigaction(SIGTTOU, &act, 0); |
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| 138 | sigaction(SIGURG, &act, 0); |
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[e7e016f] | 139 | #ifdef SIGLOST |
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[637df35] | 140 | sigaction(SIGLOST, &act, 0); |
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| 141 | #endif |
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| 142 | |
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| 143 | } |
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| 144 | |
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| 145 | /*PAGE |
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| 146 | * |
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| 147 | * _CPU_Context_From_CPU_Init |
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| 148 | */ |
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| 149 | |
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| 150 | void _CPU_Context_From_CPU_Init() |
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| 151 | { |
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| 152 | |
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| 153 | #if defined(hppa1_1) && defined(RTEMS_UNIXLIB) |
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| 154 | /* |
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| 155 | * HACK - set the _SYSTEM_ID to 0x20c so that setjmp/longjmp |
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| 156 | * will handle the full 32 floating point registers. |
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| 157 | * |
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| 158 | * NOTE: Is this a bug in HPUX9? |
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| 159 | */ |
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| 160 | |
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| 161 | { |
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| 162 | extern unsigned32 _SYSTEM_ID; |
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| 163 | |
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| 164 | _SYSTEM_ID = 0x20c; |
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| 165 | } |
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| 166 | #endif |
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| 167 | |
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| 168 | /* |
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| 169 | * get default values to use in _CPU_Context_Initialize() |
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| 170 | */ |
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| 171 | |
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| 172 | _CPU_ISR_Set_level( 0 ); |
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[3652ad35] | 173 | _CPU_Context_switch( |
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| 174 | &_CPU_Context_Default_with_ISRs_enabled, |
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| 175 | &_CPU_Context_Default_with_ISRs_enabled |
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[637df35] | 176 | ); |
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| 177 | |
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| 178 | _CPU_ISR_Set_level( 1 ); |
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[3652ad35] | 179 | _CPU_Context_switch( |
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| 180 | &_CPU_Context_Default_with_ISRs_disabled, |
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| 181 | &_CPU_Context_Default_with_ISRs_disabled |
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[637df35] | 182 | ); |
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| 183 | } |
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| 184 | |
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[3a4ae6c] | 185 | /*PAGE |
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| 186 | * |
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| 187 | * _CPU_ISR_Get_level |
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| 188 | */ |
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| 189 | |
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[3652ad35] | 190 | sigset_t GET_old_mask; |
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| 191 | |
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[3a4ae6c] | 192 | unsigned32 _CPU_ISR_Get_level( void ) |
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| 193 | { |
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[3652ad35] | 194 | /* sigset_t old_mask; */ |
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| 195 | unsigned32 old_level; |
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[3a4ae6c] | 196 | |
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[3652ad35] | 197 | sigprocmask(0, 0, &GET_old_mask); |
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| 198 | |
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| 199 | if (memcmp((void *)&posix_empty_mask, (void *)&GET_old_mask, sizeof(sigset_t))) |
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| 200 | old_level = 1; |
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| 201 | else |
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| 202 | old_level = 0; |
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[3a4ae6c] | 203 | |
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[3652ad35] | 204 | return old_level; |
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[3a4ae6c] | 205 | } |
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| 206 | |
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[ac7d5ef0] | 207 | /* _CPU_Initialize |
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| 208 | * |
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| 209 | * This routine performs processor dependent initialization. |
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| 210 | * |
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| 211 | * INPUT PARAMETERS: |
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| 212 | * cpu_table - CPU table to initialize |
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| 213 | * thread_dispatch - address of disptaching routine |
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| 214 | */ |
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| 215 | |
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| 216 | |
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| 217 | void _CPU_Initialize( |
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| 218 | rtems_cpu_table *cpu_table, |
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[3a4ae6c] | 219 | void (*thread_dispatch) /* ignored on this CPU */ |
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[ac7d5ef0] | 220 | ) |
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| 221 | { |
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| 222 | /* |
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| 223 | * The thread_dispatch argument is the address of the entry point |
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| 224 | * for the routine called at the end of an ISR once it has been |
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| 225 | * decided a context switch is necessary. On some compilation |
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| 226 | * systems it is difficult to call a high-level language routine |
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| 227 | * from assembly. This allows us to trick these systems. |
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| 228 | * |
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| 229 | * If you encounter this problem save the entry point in a CPU |
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| 230 | * dependent variable. |
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| 231 | */ |
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| 232 | |
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| 233 | _CPU_Thread_dispatch_pointer = thread_dispatch; |
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| 234 | |
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| 235 | /* |
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| 236 | * XXX; If there is not an easy way to initialize the FP context |
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| 237 | * during Context_Initialize, then it is usually easier to |
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| 238 | * save an "uninitialized" FP context here and copy it to |
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| 239 | * the task's during Context_Initialize. |
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| 240 | */ |
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| 241 | |
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| 242 | /* XXX: FP context initialization support */ |
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| 243 | |
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| 244 | _CPU_Table = *cpu_table; |
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| 245 | |
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[637df35] | 246 | _CPU_ISR_From_CPU_Init(); |
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[ac7d5ef0] | 247 | |
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[637df35] | 248 | _CPU_Context_From_CPU_Init(); |
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[ac7d5ef0] | 249 | |
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[637df35] | 250 | } |
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[ac7d5ef0] | 251 | |
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[637df35] | 252 | /*PAGE |
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| 253 | * |
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| 254 | * _CPU_ISR_install_raw_handler |
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| 255 | */ |
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[ac7d5ef0] | 256 | |
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[637df35] | 257 | void _CPU_ISR_install_raw_handler( |
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| 258 | unsigned32 vector, |
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| 259 | proc_ptr new_handler, |
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| 260 | proc_ptr *old_handler |
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| 261 | ) |
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| 262 | { |
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| 263 | _CPU_Fatal_halt( 0xdeaddead ); |
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[ac7d5ef0] | 264 | } |
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| 265 | |
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[637df35] | 266 | /*PAGE |
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| 267 | * |
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| 268 | * _CPU_ISR_install_vector |
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[ac7d5ef0] | 269 | * |
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| 270 | * This kernel routine installs the RTEMS handler for the |
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| 271 | * specified vector. |
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| 272 | * |
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| 273 | * Input parameters: |
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| 274 | * vector - interrupt vector number |
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| 275 | * old_handler - former ISR for this vector number |
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| 276 | * new_handler - replacement ISR for this vector number |
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| 277 | * |
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| 278 | * Output parameters: NONE |
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| 279 | * |
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| 280 | */ |
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| 281 | |
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| 282 | |
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| 283 | void _CPU_ISR_install_vector( |
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| 284 | unsigned32 vector, |
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| 285 | proc_ptr new_handler, |
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| 286 | proc_ptr *old_handler |
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| 287 | ) |
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| 288 | { |
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| 289 | *old_handler = _ISR_Vector_table[ vector ]; |
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| 290 | |
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| 291 | /* |
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| 292 | * If the interrupt vector table is a table of pointer to isr entry |
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| 293 | * points, then we need to install the appropriate RTEMS interrupt |
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| 294 | * handler for this vector number. |
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| 295 | */ |
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| 296 | |
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| 297 | /* |
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| 298 | * We put the actual user ISR address in '_ISR_vector_table'. This will |
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[637df35] | 299 | * be used by the _CPU_ISR_Handler so the user gets control. |
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[ac7d5ef0] | 300 | */ |
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| 301 | |
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| 302 | _ISR_Vector_table[ vector ] = new_handler; |
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| 303 | } |
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| 304 | |
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| 305 | /*PAGE |
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| 306 | * |
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| 307 | * _CPU_Install_interrupt_stack |
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| 308 | */ |
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| 309 | |
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| 310 | void _CPU_Install_interrupt_stack( void ) |
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| 311 | { |
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| 312 | } |
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| 313 | |
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| 314 | /*PAGE |
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| 315 | * |
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| 316 | * _CPU_Internal_threads_Idle_thread_body |
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| 317 | * |
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| 318 | * NOTES: |
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| 319 | * |
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| 320 | * 1. This is the same as the regular CPU independent algorithm. |
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| 321 | * |
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| 322 | * 2. If you implement this using a "halt", "idle", or "shutdown" |
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| 323 | * instruction, then don't forget to put it in an infinite loop. |
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| 324 | * |
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| 325 | * 3. Be warned. Some processors with onboard DMA have been known |
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| 326 | * to stop the DMA if the CPU were put in IDLE mode. This might |
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| 327 | * also be a problem with other on-chip peripherals. So use this |
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| 328 | * hook with caution. |
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| 329 | */ |
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| 330 | |
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| 331 | void _CPU_Internal_threads_Idle_thread_body( void ) |
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| 332 | { |
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[637df35] | 333 | while (1) |
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| 334 | pause(); |
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[ac7d5ef0] | 335 | } |
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| 336 | |
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[637df35] | 337 | /*PAGE |
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| 338 | * |
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| 339 | * _CPU_Context_Initialize |
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| 340 | */ |
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| 341 | |
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[ac7d5ef0] | 342 | void _CPU_Context_Initialize( |
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| 343 | Context_Control *_the_context, |
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| 344 | unsigned32 *_stack_base, |
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| 345 | unsigned32 _size, |
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| 346 | unsigned32 _new_level, |
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[88d594a] | 347 | void *_entry_point |
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[ac7d5ef0] | 348 | ) |
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| 349 | { |
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[637df35] | 350 | void *source; |
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| 351 | unsigned32 *addr; |
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| 352 | unsigned32 jmp_addr; |
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| 353 | unsigned32 _stack_low; /* lowest "stack aligned" address */ |
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| 354 | unsigned32 _stack_high; /* highest "stack aligned" address */ |
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| 355 | unsigned32 _the_size; |
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[ac7d5ef0] | 356 | |
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[637df35] | 357 | jmp_addr = (unsigned32) _entry_point; |
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[ac7d5ef0] | 358 | |
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[637df35] | 359 | /* |
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| 360 | * On CPUs with stacks which grow down, we build the stack |
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| 361 | * based on the _stack_high address. On CPUs with stacks which |
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| 362 | * grow up, we build the stack based on the _stack_low address. |
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| 363 | */ |
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[88d594a] | 364 | |
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[637df35] | 365 | _stack_low = ((unsigned32)(_stack_base) + CPU_STACK_ALIGNMENT); |
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| 366 | _stack_low &= ~(CPU_STACK_ALIGNMENT - 1); |
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[88d594a] | 367 | |
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[637df35] | 368 | _stack_high = ((unsigned32)(_stack_base) + _size); |
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| 369 | _stack_high &= ~(CPU_STACK_ALIGNMENT - 1); |
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[ac7d5ef0] | 370 | |
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[637df35] | 371 | _the_size = _size & ~(CPU_STACK_ALIGNMENT - 1); |
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[ac7d5ef0] | 372 | |
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[637df35] | 373 | /* |
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| 374 | * Slam our jmp_buf template into the context we are creating |
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| 375 | */ |
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[ac7d5ef0] | 376 | |
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[637df35] | 377 | if ( _new_level == 0 ) |
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| 378 | source = _CPU_Context_Default_with_ISRs_enabled.regs; |
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| 379 | else |
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| 380 | source = _CPU_Context_Default_with_ISRs_disabled.regs; |
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| 381 | |
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[3652ad35] | 382 | memcpy(_the_context, source, sizeof(Context_Control) ); /* sizeof(jmp_buf)); */ |
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[ac7d5ef0] | 383 | |
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[637df35] | 384 | addr = (unsigned32 *)_the_context; |
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[ac7d5ef0] | 385 | |
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| 386 | #if defined(hppa1_1) |
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[637df35] | 387 | *(addr + RP_OFF) = jmp_addr; |
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| 388 | *(addr + SP_OFF) = (unsigned32)(_stack_low + CPU_FRAME_SIZE); |
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[ac7d5ef0] | 389 | |
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[637df35] | 390 | /* |
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| 391 | * See if we are using shared libraries by checking |
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| 392 | * bit 30 in 24 off of newp. If bit 30 is set then |
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| 393 | * we are using shared libraries and the jump address |
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| 394 | * is at what 24 off of newp points to so shove that |
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| 395 | * into 24 off of newp instead. |
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| 396 | */ |
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[ac7d5ef0] | 397 | |
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[637df35] | 398 | if (jmp_addr & 0x40000000) { |
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| 399 | jmp_addr &= 0xfffffffc; |
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| 400 | *(addr + RP_OFF) = (unsigned32)*(unsigned32 *)jmp_addr; |
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| 401 | } |
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[ac7d5ef0] | 402 | #elif defined(sparc) |
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| 403 | |
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[637df35] | 404 | /* |
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| 405 | * See /usr/include/sys/stack.h in Solaris 2.3 for a nice |
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| 406 | * diagram of the stack. |
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| 407 | */ |
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[ac7d5ef0] | 408 | |
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[637df35] | 409 | asm ("ta 0x03"); /* flush registers */ |
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[ac7d5ef0] | 410 | |
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[637df35] | 411 | *(addr + RP_OFF) = jmp_addr + ADDR_ADJ_OFFSET; |
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| 412 | *(addr + SP_OFF) = (unsigned32)(_stack_high - CPU_FRAME_SIZE); |
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| 413 | *(addr + FP_OFF) = (unsigned32)(_stack_high); |
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[8044533] | 414 | |
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| 415 | #elif defined(i386) |
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| 416 | |
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| 417 | /* |
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| 418 | * This information was gathered by disassembling setjmp(). |
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| 419 | */ |
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[10aed1e3] | 420 | |
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| 421 | { |
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| 422 | unsigned32 stack_ptr; |
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| 423 | |
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| 424 | stack_ptr = _stack_high - CPU_FRAME_SIZE; |
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| 425 | |
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| 426 | *(addr + EBX_OFF) = 0xFEEDFEED; |
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| 427 | *(addr + ESI_OFF) = 0xDEADDEAD; |
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| 428 | *(addr + EDI_OFF) = 0xDEAFDEAF; |
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| 429 | *(addr + EBP_OFF) = stack_ptr; |
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| 430 | *(addr + ESP_OFF) = stack_ptr; |
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| 431 | *(addr + RET_OFF) = jmp_addr; |
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[8044533] | 432 | |
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[10aed1e3] | 433 | addr = (unsigned32 *) stack_ptr; |
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[8044533] | 434 | |
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[10aed1e3] | 435 | addr[ 0 ] = jmp_addr; |
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| 436 | addr[ 1 ] = (unsigned32) stack_ptr; |
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| 437 | addr[ 2 ] = (unsigned32) stack_ptr; |
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| 438 | } |
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[8044533] | 439 | |
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[ac7d5ef0] | 440 | #else |
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| 441 | #error "UNKNOWN CPU!!!" |
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| 442 | #endif |
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| 443 | |
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| 444 | } |
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| 445 | |
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[637df35] | 446 | /*PAGE |
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| 447 | * |
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| 448 | * _CPU_Context_restore |
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| 449 | */ |
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| 450 | |
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[ac7d5ef0] | 451 | void _CPU_Context_restore( |
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| 452 | Context_Control *next |
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| 453 | ) |
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| 454 | { |
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[637df35] | 455 | sigprocmask( SIG_SETMASK, &next->isr_level, 0 ); |
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| 456 | longjmp( next->regs, 0 ); |
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[ac7d5ef0] | 457 | } |
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| 458 | |
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[637df35] | 459 | /*PAGE |
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| 460 | * |
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| 461 | * _CPU_Context_switch |
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| 462 | */ |
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| 463 | |
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[ac7d5ef0] | 464 | void _CPU_Context_switch( |
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| 465 | Context_Control *current, |
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| 466 | Context_Control *next |
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| 467 | ) |
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| 468 | { |
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[3652ad35] | 469 | int status; |
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| 470 | |
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[637df35] | 471 | /* |
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| 472 | * Switch levels in one operation |
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| 473 | */ |
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[ac7d5ef0] | 474 | |
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[3652ad35] | 475 | status = sigprocmask( SIG_SETMASK, &next->isr_level, ¤t->isr_level ); |
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| 476 | if ( status ) |
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| 477 | _Internal_error_Occurred( |
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| 478 | INTERNAL_ERROR_CORE, |
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| 479 | TRUE, |
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| 480 | status |
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| 481 | ); |
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[ac7d5ef0] | 482 | |
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[637df35] | 483 | if (setjmp(current->regs) == 0) { /* Save the current context */ |
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| 484 | longjmp(next->regs, 0); /* Switch to the new context */ |
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[3652ad35] | 485 | if ( status ) |
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| 486 | _Internal_error_Occurred( |
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| 487 | INTERNAL_ERROR_CORE, |
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| 488 | TRUE, |
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| 489 | status |
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| 490 | ); |
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[637df35] | 491 | } |
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[3652ad35] | 492 | |
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[ac7d5ef0] | 493 | } |
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[637df35] | 494 | |
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| 495 | /*PAGE |
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| 496 | * |
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| 497 | * _CPU_Save_float_context |
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| 498 | */ |
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[ac7d5ef0] | 499 | |
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| 500 | void _CPU_Save_float_context( |
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| 501 | Context_Control_fp *fp_context |
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| 502 | ) |
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| 503 | { |
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| 504 | } |
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| 505 | |
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[637df35] | 506 | /*PAGE |
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| 507 | * |
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| 508 | * _CPU_Restore_float_context |
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| 509 | */ |
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| 510 | |
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[ac7d5ef0] | 511 | void _CPU_Restore_float_context( |
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| 512 | Context_Control_fp *fp_context |
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| 513 | ) |
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| 514 | { |
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| 515 | } |
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| 516 | |
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[637df35] | 517 | /*PAGE |
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| 518 | * |
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| 519 | * _CPU_ISR_Disable_support |
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| 520 | */ |
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[ac7d5ef0] | 521 | |
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[637df35] | 522 | unsigned32 _CPU_ISR_Disable_support(void) |
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[ac7d5ef0] | 523 | { |
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[3652ad35] | 524 | int status; |
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[637df35] | 525 | sigset_t old_mask; |
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[ac7d5ef0] | 526 | |
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[3652ad35] | 527 | status = sigprocmask(SIG_BLOCK, &_CPU_Signal_mask, &old_mask); |
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| 528 | if ( status ) |
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| 529 | _Internal_error_Occurred( |
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| 530 | INTERNAL_ERROR_CORE, |
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| 531 | TRUE, |
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| 532 | status |
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| 533 | ); |
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[ac7d5ef0] | 534 | |
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[3652ad35] | 535 | if (memcmp((void *)&posix_empty_mask, (void *)&old_mask, sizeof(sigset_t))) |
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[637df35] | 536 | return 1; |
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[ac7d5ef0] | 537 | |
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[637df35] | 538 | return 0; |
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[ac7d5ef0] | 539 | } |
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| 540 | |
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[637df35] | 541 | /*PAGE |
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| 542 | * |
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| 543 | * _CPU_ISR_Enable |
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| 544 | */ |
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[ac7d5ef0] | 545 | |
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[637df35] | 546 | void _CPU_ISR_Enable( |
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| 547 | unsigned32 level |
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| 548 | ) |
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[ac7d5ef0] | 549 | { |
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[3652ad35] | 550 | int status; |
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| 551 | |
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[637df35] | 552 | if (level == 0) |
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[3652ad35] | 553 | status = sigprocmask(SIG_UNBLOCK, &_CPU_Signal_mask, 0); |
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[637df35] | 554 | else |
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[3652ad35] | 555 | status = sigprocmask(SIG_BLOCK, &_CPU_Signal_mask, 0); |
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| 556 | |
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| 557 | if ( status ) |
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| 558 | _Internal_error_Occurred( |
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| 559 | INTERNAL_ERROR_CORE, |
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| 560 | TRUE, |
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| 561 | status |
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| 562 | ); |
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[ac7d5ef0] | 563 | } |
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| 564 | |
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[637df35] | 565 | /*PAGE |
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[ac7d5ef0] | 566 | * |
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[637df35] | 567 | * _CPU_ISR_Handler |
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| 568 | * |
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| 569 | * External interrupt handler. |
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| 570 | * This is installed as a UNIX signal handler. |
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| 571 | * It vectors out to specific user interrupt handlers. |
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[ac7d5ef0] | 572 | */ |
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| 573 | |
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[637df35] | 574 | void _CPU_ISR_Handler(int vector) |
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[ac7d5ef0] | 575 | { |
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[637df35] | 576 | extern void _Thread_Dispatch(void); |
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| 577 | extern unsigned32 _Thread_Dispatch_disable_level; |
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| 578 | extern boolean _Context_Switch_necessary; |
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[ac7d5ef0] | 579 | |
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| 580 | |
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[637df35] | 581 | if (_ISR_Nest_level++ == 0) { |
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| 582 | /* switch to interrupt stack */ |
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| 583 | } |
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[ac7d5ef0] | 584 | |
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[637df35] | 585 | _Thread_Dispatch_disable_level++; |
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[ac7d5ef0] | 586 | |
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[637df35] | 587 | if (_ISR_Vector_table[vector]) { |
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| 588 | _ISR_Vector_table[vector](vector); |
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| 589 | } else { |
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| 590 | _CPU_Stray_signal(vector); |
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| 591 | } |
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[ac7d5ef0] | 592 | |
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[637df35] | 593 | if (_ISR_Nest_level-- == 0) { |
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| 594 | /* switch back to original stack */ |
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| 595 | } |
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[ac7d5ef0] | 596 | |
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[637df35] | 597 | _Thread_Dispatch_disable_level--; |
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[ac7d5ef0] | 598 | |
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[637df35] | 599 | if (_Thread_Dispatch_disable_level == 0 && |
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| 600 | (_Context_Switch_necessary || _ISR_Signals_to_thread_executing)) { |
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| 601 | _CPU_ISR_Enable(0); |
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| 602 | _Thread_Dispatch(); |
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| 603 | } |
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[ac7d5ef0] | 604 | } |
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| 605 | |
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[637df35] | 606 | /*PAGE |
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| 607 | * |
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| 608 | * _CPU_Stray_signal |
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| 609 | */ |
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[ac7d5ef0] | 610 | |
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[637df35] | 611 | void _CPU_Stray_signal(int sig_num) |
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[ac7d5ef0] | 612 | { |
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[637df35] | 613 | char buffer[ 80 ]; |
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[ac7d5ef0] | 614 | |
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[637df35] | 615 | /* |
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| 616 | * We avoid using the stdio section of the library. |
---|
| 617 | * The following is generally safe. |
---|
| 618 | */ |
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[ac7d5ef0] | 619 | |
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[637df35] | 620 | write( |
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| 621 | 2, |
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| 622 | buffer, |
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| 623 | sprintf( buffer, "Stray signal %d\n", sig_num ) |
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| 624 | ); |
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[ac7d5ef0] | 625 | |
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[637df35] | 626 | /* |
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| 627 | * If it was a "fatal" signal, then exit here |
---|
| 628 | * If app code has installed a hander for one of these, then |
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| 629 | * we won't call _CPU_Stray_signal, so this is ok. |
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| 630 | */ |
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[ac7d5ef0] | 631 | |
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[637df35] | 632 | switch (sig_num) { |
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| 633 | case SIGINT: |
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| 634 | case SIGHUP: |
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| 635 | case SIGQUIT: |
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| 636 | case SIGILL: |
---|
[10aed1e3] | 637 | #ifdef SIGEMT |
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[637df35] | 638 | case SIGEMT: |
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[10aed1e3] | 639 | #endif |
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[637df35] | 640 | case SIGKILL: |
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| 641 | case SIGBUS: |
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| 642 | case SIGSEGV: |
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| 643 | case SIGTERM: |
---|
| 644 | _CPU_Fatal_error(0x100 + sig_num); |
---|
| 645 | } |
---|
[ac7d5ef0] | 646 | } |
---|
| 647 | |
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[637df35] | 648 | /*PAGE |
---|
| 649 | * |
---|
| 650 | * _CPU_Fatal_error |
---|
| 651 | */ |
---|
[ac7d5ef0] | 652 | |
---|
[637df35] | 653 | void _CPU_Fatal_error(unsigned32 error) |
---|
[ac7d5ef0] | 654 | { |
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[637df35] | 655 | setitimer(ITIMER_REAL, 0, 0); |
---|
[ac7d5ef0] | 656 | |
---|
[e7e016f] | 657 | if ( error ) { |
---|
| 658 | #ifdef RTEMS_DEBUG |
---|
| 659 | abort(); |
---|
| 660 | #endif |
---|
| 661 | if (getenv("RTEMS_DEBUG")) |
---|
| 662 | abort(); |
---|
| 663 | } |
---|
| 664 | |
---|
[637df35] | 665 | _exit(error); |
---|
[ac7d5ef0] | 666 | } |
---|
| 667 | |
---|
[637df35] | 668 | /*PAGE |
---|
| 669 | * |
---|
| 670 | * _CPU_ffs |
---|
| 671 | */ |
---|
| 672 | |
---|
| 673 | int _CPU_ffs(unsigned32 value) |
---|
[ac7d5ef0] | 674 | { |
---|
[637df35] | 675 | int output; |
---|
| 676 | extern int ffs( int ); |
---|
[ac7d5ef0] | 677 | |
---|
[637df35] | 678 | output = ffs(value); |
---|
| 679 | output = output - 1; |
---|
[ac7d5ef0] | 680 | |
---|
[637df35] | 681 | return output; |
---|
[ac7d5ef0] | 682 | } |
---|