source: rtems/c/src/exec/score/cpu/sparc/sparc.h @ c4808ca

4.104.114.84.95
Last change on this file since c4808ca was c4808ca, checked in by Joel Sherrill <joel.sherrill@…>, on Oct 31, 1995 at 9:28:16 PM

typos fixed

  • Property mode set to 100644
File size: 6.9 KB
Line 
1/*  sparc.h
2 *
3 *  This include file contains information pertaining to the SPARC
4 *  processor family.
5 *
6 *  COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994.
7 *  On-Line Applications Research Corporation (OAR).
8 *  All rights assigned to U.S. Government, 1994.
9 *
10 *  This material may be reproduced by or for the U.S. Government pursuant
11 *  to the copyright license under the clause at DFARS 252.227-7013.  This
12 *  notice must appear in all copies of this file and its derivatives.
13 *
14 *  Ported to ERC32 implementation of the SPARC by On-Line Applications
15 *  Research Corporation (OAR) under contract to the European Space
16 *  Agency (ESA).
17 *
18 *  ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995.
19 *  European Space Agency.
20 *
21 *  $Id$
22 */
23
24#ifndef _INCLUDE_SPARC_h
25#define _INCLUDE_SPARC_h
26
27#ifdef __cplusplus
28extern "C" {
29#endif
30
31/*
32 *  The following define the CPU Family and Model within the family
33 *
34 *  NOTE: The string "REPLACE_THIS_WITH_THE_CPU_MODEL" is replaced
35 *        with the name of the appropriate macro for this target CPU.
36 */
37 
38#ifdef sparc
39#undef sparc
40#endif
41#define sparc
42
43#ifdef REPLACE_THIS_WITH_THE_CPU_MODEL
44#undef REPLACE_THIS_WITH_THE_CPU_MODEL
45#endif
46#define REPLACE_THIS_WITH_THE_CPU_MODEL
47 
48#ifdef REPLACE_THIS_WITH_THE_BSP
49#undef REPLACE_THIS_WITH_THE_BSP
50#endif
51#define REPLACE_THIS_WITH_THE_BSP
52
53/*
54 *  This file contains the information required to build
55 *  RTEMS for a particular member of the "sparc" family.  It does
56 *  this by setting variables to indicate which implementation
57 *  dependent features are present in a particular member
58 *  of the family.
59 *
60 *  Currently recognized feature flags:
61 *
62 *    + SPARC_HAS_FPU
63 *        0 - no HW FPU
64 *        1 - has HW FPU (assumed to be compatible w/90C602)
65 *
66 *    + SPARC_HAS_BITSCAN
67 *        0 - does not have scan instructions
68 *        1 - has scan instruction  (not currently implemented)
69 *
70 *    + SPARC_NUMBER_OF_REGISTER_WINDOWS
71 *        8 is the most common number supported by SPARC implementations.
72 *        SPARC_PSR_CWP_MASK is derived from this value.
73 *
74 *    + SPARC_HAS_LOW_POWER_MODE
75 *        0 - does not have low power mode support (or not supported)
76 *        1 - has low power mode and thus a CPU model dependent idle task.
77 *
78 */
79 
80#if defined(erc32)
81 
82#define CPU_MODEL_NAME                   "erc32"
83#define SPARC_HAS_FPU                    1
84#define SPARC_HAS_BITSCAN                0
85#define SPARC_NUMBER_OF_REGISTER_WINDOWS 8
86#define SPARC_HAS_LOW_POWER_MODE         1
87 
88#else
89 
90#error "Unsupported CPU Model"
91 
92#endif
93
94/*
95 *  Define the name of the CPU family.
96 */
97
98#define CPU_NAME "SPARC"
99
100/*
101 *  Miscellaneous constants
102 */
103
104/*
105 *  PSR masks and starting bit positions
106 *
107 *  NOTE: Reserved bits are ignored.
108 */
109
110#if (SPARC_NUMBER_OF_REGISTER_WINDOWS == 8)
111#define SPARC_PSR_CWP_MASK               0x07   /* bits  0 -  4 */
112#elif (SPARC_NUMBER_OF_REGISTER_WINDOWS == 16)
113#define SPARC_PSR_CWP_MASK               0x0F   /* bits  0 -  4 */
114#elif (SPARC_NUMBER_OF_REGISTER_WINDOWS == 32)
115#define SPARC_PSR_CWP_MASK               0x1F   /* bits  0 -  4 */
116#else
117#error "Unsupported number of register windows for this cpu"
118#endif
119
120#define SPARC_PSR_ET_MASK   0x00000020   /* bit   5 */
121#define SPARC_PSR_PS_MASK   0x00000040   /* bit   6 */
122#define SPARC_PSR_S_MASK    0x00000080   /* bit   7 */
123#define SPARC_PSR_PIL_MASK  0x00000F00   /* bits  8 - 11 */
124#define SPARC_PSR_EF_MASK   0x00001000   /* bit  12 */
125#define SPARC_PSR_EC_MASK   0x00002000   /* bit  13 */
126#define SPARC_PSR_ICC_MASK  0x00F00000   /* bits 20 - 23 */
127#define SPARC_PSR_VER_MASK  0x0F000000   /* bits 24 - 27 */
128#define SPARC_PSR_IMPL_MASK 0xF0000000   /* bits 28 - 31 */
129
130#define SPARC_PSR_CWP_BIT_POSITION   0   /* bits  0 -  4 */
131#define SPARC_PSR_ET_BIT_POSITION    5   /* bit   5 */
132#define SPARC_PSR_PS_BIT_POSITION    6   /* bit   6 */
133#define SPARC_PSR_S_BIT_POSITION     7   /* bit   7 */
134#define SPARC_PSR_PIL_BIT_POSITION   8   /* bits  8 - 11 */
135#define SPARC_PSR_EF_BIT_POSITION   12   /* bit  12 */
136#define SPARC_PSR_EC_BIT_POSITION   13   /* bit  13 */
137#define SPARC_PSR_ICC_BIT_POSITION  20   /* bits 20 - 23 */
138#define SPARC_PSR_VER_BIT_POSITION  24   /* bits 24 - 27 */
139#define SPARC_PSR_IMPL_BIT_POSITION 28   /* bits 28 - 31 */
140
141#ifndef ASM
142
143/*
144 *  Standard nop
145 */
146
147#define nop() \
148  do { \
149    asm volatile ( "nop" ); \
150  } while ( 0 )
151
152/*
153 *  Get and set the PSR
154 */
155
156#define sparc_get_psr( _psr ) \
157  do { \
158     (_psr) = 0; \
159     asm volatile( "rd %%psr, %0" :  "=r" (_psr) : "0" (_psr) ); \
160  } while ( 0 )
161
162#define sparc_set_psr( _psr ) \
163  do { \
164    asm volatile ( "mov  %0, %%psr " : "=r" ((_psr)) : "0" ((_psr)) ); \
165    nop(); \
166    nop(); \
167    nop(); \
168  } while ( 0 )
169
170/*
171 *  Get and set the TBR
172 */
173
174#define sparc_get_tbr( _tbr ) \
175  do { \
176     (_tbr) = 0; /* to avoid unitialized warnings */ \
177     asm volatile( "rd %%tbr, %0" :  "=r" (_tbr) : "0" (_tbr) ); \
178  } while ( 0 )
179
180#define sparc_set_tbr( _tbr ) \
181  do { \
182     asm volatile( "wr %0, 0, %%tbr" :  "=r" (_tbr) : "0" (_tbr) ); \
183  } while ( 0 )
184
185/*
186 *  Get and set the WIM
187 */
188
189#define sparc_get_wim( _wim ) \
190  do { \
191    asm volatile( "rd %%wim, %0" :  "=r" (_wim) : "0" (_wim) ); \
192  } while ( 0 )
193
194#define sparc_set_wim( _wim ) \
195  do { \
196    asm volatile( "wr %0, %%wim" :  "=r" (_wim) : "0" (_wim) ); \
197    nop(); \
198    nop(); \
199    nop(); \
200  } while ( 0 )
201
202/*
203 *  Get and set the Y
204 */
205 
206#define sparc_get_y( _y ) \
207  do { \
208    asm volatile( "rd %%y, %0" :  "=r" (_y) : "0" (_y) ); \
209  } while ( 0 )
210 
211#define sparc_set_y( _y ) \
212  do { \
213    asm volatile( "wr %0, %%y" :  "=r" (_y) : "0" (_y) ); \
214  } while ( 0 )
215
216/*
217 *  Manipulate the interrupt level in the psr
218 *
219 */
220
221#define sparc_disable_interrupts( _level ) \
222  do { \
223    register unsigned int _newlevel; \
224    \
225    sparc_get_psr( _level ); \
226    (_newlevel) = (_level) | SPARC_PSR_PIL_MASK; \
227    sparc_set_psr( _newlevel ); \
228  } while ( 0 )
229 
230#define sparc_enable_interrupts( _level ) \
231  do { \
232    unsigned int _tmp; \
233    \
234    sparc_get_psr( _tmp ); \
235    _tmp &= ~SPARC_PSR_PIL_MASK; \
236    _tmp |= (_level) & SPARC_PSR_PIL_MASK; \
237    sparc_set_psr( _tmp ); \
238  } while ( 0 )
239 
240#define sparc_flash_interrupts( _level ) \
241  do { \
242    register unsigned32 _ignored = 0; \
243    \
244    sparc_enable_interrupts( (_level) ); \
245    sparc_disable_interrupts( _ignored ); \
246  } while ( 0 )
247
248#define sparc_set_interrupt_level( _new_level ) \
249  do { \
250    register unsigned32 _new_psr_level = 0; \
251    \
252    sparc_get_psr( _new_psr_level ); \
253    _new_psr_level &= ~SPARC_PSR_PIL_MASK; \
254    _new_psr_level |= \
255      (((_new_level) << SPARC_PSR_PIL_BIT_POSITION) & SPARC_PSR_PIL_MASK); \
256    sparc_set_psr( _new_psr_level ); \
257  } while ( 0 )
258
259#define sparc_get_interrupt_level( _level ) \
260  do { \
261    register unsigned32 _psr_level = 0; \
262    \
263    sparc_get_psr( _psr_level ); \
264    (_level) = \
265      (_psr_level & SPARC_PSR_PIL_MASK) >> SPARC_PSR_PIL_BIT_POSITION; \
266  } while ( 0 )
267
268#endif
269
270#ifdef __cplusplus
271}
272#endif
273
274#endif /* ! _INCLUDE_SPARC_h */
275/* end of include file */
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