source: rtems/c/src/exec/score/cpu/sparc/rtems/score/sparc.h @ 4159370

4.104.114.84.95
Last change on this file since 4159370 was 4159370, checked in by Joel Sherrill <joel.sherrill@…>, on Jul 11, 2000 at 9:16:53 PM

Reworked score/cpu/sparc so it can be safely compiled multilib. All
routines and structures that require CPU model specific information
are now in libcpu. This primarily required moving erc32 specific
information from score/cpu files to libcpu/sparc and the erc32 BSP.

  • Property mode set to 100644
File size: 6.5 KB
Line 
1/*  sparc.h
2 *
3 *  This include file contains information pertaining to the SPARC
4 *  processor family.
5 *
6 *  COPYRIGHT (c) 1989-1999.
7 *  On-Line Applications Research Corporation (OAR).
8 *
9 *  The license and distribution terms for this file may be
10 *  found in the file LICENSE in this distribution or at
11 *  http://www.OARcorp.com/rtems/license.html.
12 *
13 *  $Id$
14 */
15
16#ifndef _INCLUDE_SPARC_h
17#define _INCLUDE_SPARC_h
18
19#ifdef __cplusplus
20extern "C" {
21#endif
22
23/*
24 *  This file contains the information required to build
25 *  RTEMS for a particular member of the "sparc" family.  It does
26 *  this by setting variables to indicate which implementation
27 *  dependent features are present in a particular member
28 *  of the family.
29 *
30 *  Currently recognized feature flags:
31 *
32 *    + SPARC_HAS_FPU
33 *        0 - no HW FPU
34 *        1 - has HW FPU (assumed to be compatible w/90C602)
35 *
36 *    + SPARC_HAS_BITSCAN
37 *        0 - does not have scan instructions
38 *        1 - has scan instruction  (not currently implemented)
39 *
40 *    + SPARC_NUMBER_OF_REGISTER_WINDOWS
41 *        8 is the most common number supported by SPARC implementations.
42 *        SPARC_PSR_CWP_MASK is derived from this value.
43 */
44 
45/*
46 *  Some higher end SPARCs have a bitscan instructions. It would
47 *  be nice to take advantage of them.  Right now, there is no
48 *  port to a CPU model with this feature and no (untested) code
49 *  that is based on this feature flag.
50 */
51
52#define SPARC_HAS_BITSCAN                0
53
54/*
55 *  This should be OK until a port to a higher end SPARC processor
56 *  is made that has more than 8 register windows.  If this cannot
57 *  be determined based on multilib settings (v7/v8/v9), then the
58 *  cpu_asm.S code that depends on this will have to move to libcpu.
59 */
60
61#define SPARC_NUMBER_OF_REGISTER_WINDOWS 8
62 
63/*
64 *  This should be determined based on some soft float derived
65 *  cpp predefine but gcc does not currently give us that information.
66 */
67
68#define SPARC_HAS_FPU                    1
69
70#if SPARC_HAS_FPU
71#define CPU_MODEL_NAME "w/FPU"
72#else
73#define CPU_MODEL_NAME "w/soft-float"
74#endif
75
76/*
77 *  Define the name of the CPU family.
78 */
79
80#define CPU_NAME "SPARC"
81
82/*
83 *  Miscellaneous constants
84 */
85
86/*
87 *  PSR masks and starting bit positions
88 *
89 *  NOTE: Reserved bits are ignored.
90 */
91
92#if (SPARC_NUMBER_OF_REGISTER_WINDOWS == 8)
93#define SPARC_PSR_CWP_MASK               0x07   /* bits  0 -  4 */
94#elif (SPARC_NUMBER_OF_REGISTER_WINDOWS == 16)
95#define SPARC_PSR_CWP_MASK               0x0F   /* bits  0 -  4 */
96#elif (SPARC_NUMBER_OF_REGISTER_WINDOWS == 32)
97#define SPARC_PSR_CWP_MASK               0x1F   /* bits  0 -  4 */
98#else
99#error "Unsupported number of register windows for this cpu"
100#endif
101
102#define SPARC_PSR_ET_MASK   0x00000020   /* bit   5 */
103#define SPARC_PSR_PS_MASK   0x00000040   /* bit   6 */
104#define SPARC_PSR_S_MASK    0x00000080   /* bit   7 */
105#define SPARC_PSR_PIL_MASK  0x00000F00   /* bits  8 - 11 */
106#define SPARC_PSR_EF_MASK   0x00001000   /* bit  12 */
107#define SPARC_PSR_EC_MASK   0x00002000   /* bit  13 */
108#define SPARC_PSR_ICC_MASK  0x00F00000   /* bits 20 - 23 */
109#define SPARC_PSR_VER_MASK  0x0F000000   /* bits 24 - 27 */
110#define SPARC_PSR_IMPL_MASK 0xF0000000   /* bits 28 - 31 */
111
112#define SPARC_PSR_CWP_BIT_POSITION   0   /* bits  0 -  4 */
113#define SPARC_PSR_ET_BIT_POSITION    5   /* bit   5 */
114#define SPARC_PSR_PS_BIT_POSITION    6   /* bit   6 */
115#define SPARC_PSR_S_BIT_POSITION     7   /* bit   7 */
116#define SPARC_PSR_PIL_BIT_POSITION   8   /* bits  8 - 11 */
117#define SPARC_PSR_EF_BIT_POSITION   12   /* bit  12 */
118#define SPARC_PSR_EC_BIT_POSITION   13   /* bit  13 */
119#define SPARC_PSR_ICC_BIT_POSITION  20   /* bits 20 - 23 */
120#define SPARC_PSR_VER_BIT_POSITION  24   /* bits 24 - 27 */
121#define SPARC_PSR_IMPL_BIT_POSITION 28   /* bits 28 - 31 */
122
123#ifndef ASM
124
125/*
126 *  Standard nop
127 */
128
129#define nop() \
130  do { \
131    asm volatile ( "nop" ); \
132  } while ( 0 )
133
134/*
135 *  Get and set the PSR
136 */
137
138#define sparc_get_psr( _psr ) \
139  do { \
140     (_psr) = 0; \
141     asm volatile( "rd %%psr, %0" :  "=r" (_psr) : "0" (_psr) ); \
142  } while ( 0 )
143
144#define sparc_set_psr( _psr ) \
145  do { \
146    asm volatile ( "mov  %0, %%psr " : "=r" ((_psr)) : "0" ((_psr)) ); \
147    nop(); \
148    nop(); \
149    nop(); \
150  } while ( 0 )
151
152/*
153 *  Get and set the TBR
154 */
155
156#define sparc_get_tbr( _tbr ) \
157  do { \
158     (_tbr) = 0; /* to avoid unitialized warnings */ \
159     asm volatile( "rd %%tbr, %0" :  "=r" (_tbr) : "0" (_tbr) ); \
160  } while ( 0 )
161
162#define sparc_set_tbr( _tbr ) \
163  do { \
164     asm volatile( "wr %0, 0, %%tbr" :  "=r" (_tbr) : "0" (_tbr) ); \
165  } while ( 0 )
166
167/*
168 *  Get and set the WIM
169 */
170
171#define sparc_get_wim( _wim ) \
172  do { \
173    asm volatile( "rd %%wim, %0" :  "=r" (_wim) : "0" (_wim) ); \
174  } while ( 0 )
175
176#define sparc_set_wim( _wim ) \
177  do { \
178    asm volatile( "wr %0, %%wim" :  "=r" (_wim) : "0" (_wim) ); \
179    nop(); \
180    nop(); \
181    nop(); \
182  } while ( 0 )
183
184/*
185 *  Get and set the Y
186 */
187 
188#define sparc_get_y( _y ) \
189  do { \
190    asm volatile( "rd %%y, %0" :  "=r" (_y) : "0" (_y) ); \
191  } while ( 0 )
192 
193#define sparc_set_y( _y ) \
194  do { \
195    asm volatile( "wr %0, %%y" :  "=r" (_y) : "0" (_y) ); \
196  } while ( 0 )
197
198/*
199 *  Manipulate the interrupt level in the psr
200 *
201 */
202
203/*
204#define sparc_disable_interrupts( _level ) \
205  do { \
206    register unsigned int _newlevel; \
207    \
208    sparc_get_psr( _level ); \
209    (_newlevel) = (_level) | SPARC_PSR_PIL_MASK; \
210    sparc_set_psr( _newlevel ); \
211  } while ( 0 )
212
213#define sparc_enable_interrupts( _level ) \
214  do { \
215    unsigned int _tmp; \
216    \
217    sparc_get_psr( _tmp ); \
218    _tmp &= ~SPARC_PSR_PIL_MASK; \
219    _tmp |= (_level) & SPARC_PSR_PIL_MASK; \
220    sparc_set_psr( _tmp ); \
221  } while ( 0 )
222*/
223 
224#define sparc_flash_interrupts( _level ) \
225  do { \
226    register unsigned32 _ignored = 0; \
227    \
228    sparc_enable_interrupts( (_level) ); \
229    sparc_disable_interrupts( _ignored ); \
230  } while ( 0 )
231
232/*
233#define sparc_set_interrupt_level( _new_level ) \
234  do { \
235    register unsigned32 _new_psr_level = 0; \
236    \
237    sparc_get_psr( _new_psr_level ); \
238    _new_psr_level &= ~SPARC_PSR_PIL_MASK; \
239    _new_psr_level |= \
240      (((_new_level) << SPARC_PSR_PIL_BIT_POSITION) & SPARC_PSR_PIL_MASK); \
241    sparc_set_psr( _new_psr_level ); \
242  } while ( 0 )
243*/
244
245#define sparc_get_interrupt_level( _level ) \
246  do { \
247    register unsigned32 _psr_level = 0; \
248    \
249    sparc_get_psr( _psr_level ); \
250    (_level) = \
251      (_psr_level & SPARC_PSR_PIL_MASK) >> SPARC_PSR_PIL_BIT_POSITION; \
252  } while ( 0 )
253
254#endif
255
256#ifdef __cplusplus
257}
258#endif
259
260#endif /* ! _INCLUDE_SPARC_h */
261/* end of include file */
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