[7908ba5b] | 1 | /* cpu.h |
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| 2 | * |
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| 3 | * This include file contains information pertaining to the port of |
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| 4 | * the executive to the SPARC processor. |
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| 5 | * |
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[08311cc3] | 6 | * COPYRIGHT (c) 1989-1999. |
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[7908ba5b] | 7 | * On-Line Applications Research Corporation (OAR). |
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| 8 | * |
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| 9 | * The license and distribution terms for this file may be |
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| 10 | * found in the file LICENSE in this distribution or at |
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| 11 | * http://www.OARcorp.com/rtems/license.html. |
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| 12 | * |
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| 13 | * $Id$ |
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| 14 | */ |
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| 15 | |
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| 16 | #ifndef __CPU_h |
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| 17 | #define __CPU_h |
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| 18 | |
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| 19 | #ifdef __cplusplus |
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| 20 | extern "C" { |
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| 21 | #endif |
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| 22 | |
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| 23 | #include <rtems/score/sparc.h> /* pick up machine definitions */ |
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| 24 | #ifndef ASM |
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[22ed9d0f] | 25 | #include <rtems/score/types.h> |
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[7908ba5b] | 26 | #endif |
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| 27 | |
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| 28 | /* conditional compilation parameters */ |
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| 29 | |
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| 30 | /* |
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| 31 | * Should the calls to _Thread_Enable_dispatch be inlined? |
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| 32 | * |
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| 33 | * If TRUE, then they are inlined. |
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| 34 | * If FALSE, then a subroutine call is made. |
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| 35 | */ |
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| 36 | |
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| 37 | #define CPU_INLINE_ENABLE_DISPATCH TRUE |
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| 38 | |
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| 39 | /* |
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| 40 | * Should the body of the search loops in _Thread_queue_Enqueue_priority |
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| 41 | * be unrolled one time? In unrolled each iteration of the loop examines |
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| 42 | * two "nodes" on the chain being searched. Otherwise, only one node |
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| 43 | * is examined per iteration. |
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| 44 | * |
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| 45 | * If TRUE, then the loops are unrolled. |
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| 46 | * If FALSE, then the loops are not unrolled. |
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| 47 | * |
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| 48 | * This parameter could go either way on the SPARC. The interrupt flash |
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| 49 | * code is relatively lengthy given the requirements for nops following |
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| 50 | * writes to the psr. But if the clock speed were high enough, this would |
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| 51 | * not represent a great deal of time. |
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| 52 | */ |
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| 53 | |
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| 54 | #define CPU_UNROLL_ENQUEUE_PRIORITY TRUE |
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| 55 | |
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| 56 | /* |
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| 57 | * Does the executive manage a dedicated interrupt stack in software? |
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| 58 | * |
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[8bc62aeb] | 59 | * If TRUE, then a stack is allocated in _ISR_Handler_initialization. |
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[7908ba5b] | 60 | * If FALSE, nothing is done. |
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| 61 | * |
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| 62 | * The SPARC does not have a dedicated HW interrupt stack and one has |
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| 63 | * been implemented in SW. |
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| 64 | */ |
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| 65 | |
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| 66 | #define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE |
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| 67 | |
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| 68 | /* |
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| 69 | * Does this CPU have hardware support for a dedicated interrupt stack? |
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| 70 | * |
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| 71 | * If TRUE, then it must be installed during initialization. |
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| 72 | * If FALSE, then no installation is performed. |
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| 73 | * |
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| 74 | * The SPARC does not have a dedicated HW interrupt stack. |
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| 75 | */ |
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| 76 | |
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| 77 | #define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE |
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| 78 | |
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| 79 | /* |
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| 80 | * Do we allocate a dedicated interrupt stack in the Interrupt Manager? |
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| 81 | * |
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| 82 | * If TRUE, then the memory is allocated during initialization. |
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| 83 | * If FALSE, then the memory is allocated during initialization. |
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| 84 | */ |
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| 85 | |
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| 86 | #define CPU_ALLOCATE_INTERRUPT_STACK TRUE |
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| 87 | |
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| 88 | /* |
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| 89 | * Does the RTEMS invoke the user's ISR with the vector number and |
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| 90 | * a pointer to the saved interrupt frame (1) or just the vector |
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| 91 | * number (0)? |
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| 92 | */ |
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| 93 | |
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| 94 | #define CPU_ISR_PASSES_FRAME_POINTER 0 |
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| 95 | |
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| 96 | /* |
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| 97 | * Does the CPU have hardware floating point? |
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| 98 | * |
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| 99 | * If TRUE, then the FLOATING_POINT task attribute is supported. |
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| 100 | * If FALSE, then the FLOATING_POINT task attribute is ignored. |
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| 101 | */ |
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| 102 | |
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| 103 | #if ( SPARC_HAS_FPU == 1 ) |
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| 104 | #define CPU_HARDWARE_FP TRUE |
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| 105 | #else |
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| 106 | #define CPU_HARDWARE_FP FALSE |
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| 107 | #endif |
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[17508d02] | 108 | #define CPU_SOFTWARE_FP FALSE |
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[7908ba5b] | 109 | |
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| 110 | /* |
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| 111 | * Are all tasks FLOATING_POINT tasks implicitly? |
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| 112 | * |
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| 113 | * If TRUE, then the FLOATING_POINT task attribute is assumed. |
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| 114 | * If FALSE, then the FLOATING_POINT task attribute is followed. |
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| 115 | */ |
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| 116 | |
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| 117 | #define CPU_ALL_TASKS_ARE_FP FALSE |
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| 118 | |
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| 119 | /* |
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| 120 | * Should the IDLE task have a floating point context? |
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| 121 | * |
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| 122 | * If TRUE, then the IDLE task is created as a FLOATING_POINT task |
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| 123 | * and it has a floating point context which is switched in and out. |
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| 124 | * If FALSE, then the IDLE task does not have a floating point context. |
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| 125 | */ |
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| 126 | |
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| 127 | #define CPU_IDLE_TASK_IS_FP FALSE |
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| 128 | |
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| 129 | /* |
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| 130 | * Should the saving of the floating point registers be deferred |
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| 131 | * until a context switch is made to another different floating point |
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| 132 | * task? |
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| 133 | * |
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| 134 | * If TRUE, then the floating point context will not be stored until |
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| 135 | * necessary. It will remain in the floating point registers and not |
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| 136 | * disturned until another floating point task is switched to. |
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| 137 | * |
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| 138 | * If FALSE, then the floating point context is saved when a floating |
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| 139 | * point task is switched out and restored when the next floating point |
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| 140 | * task is restored. The state of the floating point registers between |
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| 141 | * those two operations is not specified. |
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| 142 | */ |
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| 143 | |
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| 144 | #define CPU_USE_DEFERRED_FP_SWITCH TRUE |
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| 145 | |
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| 146 | /* |
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| 147 | * Does this port provide a CPU dependent IDLE task implementation? |
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| 148 | * |
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| 149 | * If TRUE, then the routine _CPU_Thread_Idle_body |
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| 150 | * must be provided and is the default IDLE thread body instead of |
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| 151 | * _CPU_Thread_Idle_body. |
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| 152 | * |
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| 153 | * If FALSE, then use the generic IDLE thread body if the BSP does |
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| 154 | * not provide one. |
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| 155 | */ |
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| 156 | |
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| 157 | #define CPU_PROVIDES_IDLE_THREAD_BODY FALSE |
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| 158 | |
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| 159 | /* |
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| 160 | * Does the stack grow up (toward higher addresses) or down |
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| 161 | * (toward lower addresses)? |
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| 162 | * |
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| 163 | * If TRUE, then the grows upward. |
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| 164 | * If FALSE, then the grows toward smaller addresses. |
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| 165 | * |
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| 166 | * The stack grows to lower addresses on the SPARC. |
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| 167 | */ |
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| 168 | |
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| 169 | #define CPU_STACK_GROWS_UP FALSE |
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| 170 | |
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| 171 | /* |
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| 172 | * The following is the variable attribute used to force alignment |
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| 173 | * of critical data structures. On some processors it may make |
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| 174 | * sense to have these aligned on tighter boundaries than |
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| 175 | * the minimum requirements of the compiler in order to have as |
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| 176 | * much of the critical data area as possible in a cache line. |
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| 177 | * |
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| 178 | * The SPARC does not appear to have particularly strict alignment |
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| 179 | * requirements. This value was chosen to take advantages of caches. |
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| 180 | */ |
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| 181 | |
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| 182 | #define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned (16))) |
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| 183 | |
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| 184 | /* |
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| 185 | * Define what is required to specify how the network to host conversion |
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| 186 | * routines are handled. |
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| 187 | */ |
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| 188 | |
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[6805640e] | 189 | #define CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES FALSE |
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[7908ba5b] | 190 | #define CPU_BIG_ENDIAN TRUE |
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| 191 | #define CPU_LITTLE_ENDIAN FALSE |
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| 192 | |
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| 193 | /* |
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| 194 | * The following defines the number of bits actually used in the |
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| 195 | * interrupt field of the task mode. How those bits map to the |
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| 196 | * CPU interrupt levels is defined by the routine _CPU_ISR_Set_level(). |
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| 197 | * |
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| 198 | * The SPARC has 16 interrupt levels in the PIL field of the PSR. |
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| 199 | */ |
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| 200 | |
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| 201 | #define CPU_MODES_INTERRUPT_MASK 0x0000000F |
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| 202 | |
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| 203 | /* |
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| 204 | * This structure represents the organization of the minimum stack frame |
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| 205 | * for the SPARC. More framing information is required in certain situaions |
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| 206 | * such as when there are a large number of out parameters or when the callee |
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| 207 | * must save floating point registers. |
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| 208 | */ |
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| 209 | |
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| 210 | #ifndef ASM |
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| 211 | |
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| 212 | typedef struct { |
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| 213 | unsigned32 l0; |
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| 214 | unsigned32 l1; |
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| 215 | unsigned32 l2; |
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| 216 | unsigned32 l3; |
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| 217 | unsigned32 l4; |
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| 218 | unsigned32 l5; |
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| 219 | unsigned32 l6; |
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| 220 | unsigned32 l7; |
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| 221 | unsigned32 i0; |
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| 222 | unsigned32 i1; |
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| 223 | unsigned32 i2; |
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| 224 | unsigned32 i3; |
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| 225 | unsigned32 i4; |
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| 226 | unsigned32 i5; |
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| 227 | unsigned32 i6_fp; |
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| 228 | unsigned32 i7; |
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| 229 | void *structure_return_address; |
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| 230 | /* |
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| 231 | * The following are for the callee to save the register arguments in |
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| 232 | * should this be necessary. |
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| 233 | */ |
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| 234 | unsigned32 saved_arg0; |
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| 235 | unsigned32 saved_arg1; |
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| 236 | unsigned32 saved_arg2; |
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| 237 | unsigned32 saved_arg3; |
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| 238 | unsigned32 saved_arg4; |
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| 239 | unsigned32 saved_arg5; |
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| 240 | unsigned32 pad0; |
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| 241 | } CPU_Minimum_stack_frame; |
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| 242 | |
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| 243 | #endif /* ASM */ |
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| 244 | |
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| 245 | #define CPU_STACK_FRAME_L0_OFFSET 0x00 |
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| 246 | #define CPU_STACK_FRAME_L1_OFFSET 0x04 |
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| 247 | #define CPU_STACK_FRAME_L2_OFFSET 0x08 |
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| 248 | #define CPU_STACK_FRAME_L3_OFFSET 0x0c |
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| 249 | #define CPU_STACK_FRAME_L4_OFFSET 0x10 |
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| 250 | #define CPU_STACK_FRAME_L5_OFFSET 0x14 |
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| 251 | #define CPU_STACK_FRAME_L6_OFFSET 0x18 |
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| 252 | #define CPU_STACK_FRAME_L7_OFFSET 0x1c |
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| 253 | #define CPU_STACK_FRAME_I0_OFFSET 0x20 |
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| 254 | #define CPU_STACK_FRAME_I1_OFFSET 0x24 |
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| 255 | #define CPU_STACK_FRAME_I2_OFFSET 0x28 |
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| 256 | #define CPU_STACK_FRAME_I3_OFFSET 0x2c |
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| 257 | #define CPU_STACK_FRAME_I4_OFFSET 0x30 |
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| 258 | #define CPU_STACK_FRAME_I5_OFFSET 0x34 |
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| 259 | #define CPU_STACK_FRAME_I6_FP_OFFSET 0x38 |
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| 260 | #define CPU_STACK_FRAME_I7_OFFSET 0x3c |
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| 261 | #define CPU_STRUCTURE_RETURN_ADDRESS_OFFSET 0x40 |
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| 262 | #define CPU_STACK_FRAME_SAVED_ARG0_OFFSET 0x44 |
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| 263 | #define CPU_STACK_FRAME_SAVED_ARG1_OFFSET 0x48 |
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| 264 | #define CPU_STACK_FRAME_SAVED_ARG2_OFFSET 0x4c |
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| 265 | #define CPU_STACK_FRAME_SAVED_ARG3_OFFSET 0x50 |
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| 266 | #define CPU_STACK_FRAME_SAVED_ARG4_OFFSET 0x54 |
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| 267 | #define CPU_STACK_FRAME_SAVED_ARG5_OFFSET 0x58 |
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| 268 | #define CPU_STACK_FRAME_PAD0_OFFSET 0x5c |
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| 269 | |
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| 270 | #define CPU_MINIMUM_STACK_FRAME_SIZE 0x60 |
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| 271 | |
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| 272 | /* |
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| 273 | * Contexts |
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| 274 | * |
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| 275 | * Generally there are 2 types of context to save. |
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| 276 | * 1. Interrupt registers to save |
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| 277 | * 2. Task level registers to save |
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| 278 | * |
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| 279 | * This means we have the following 3 context items: |
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| 280 | * 1. task level context stuff:: Context_Control |
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| 281 | * 2. floating point task stuff:: Context_Control_fp |
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| 282 | * 3. special interrupt level context :: Context_Control_interrupt |
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| 283 | * |
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| 284 | * On the SPARC, we are relatively conservative in that we save most |
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| 285 | * of the CPU state in the context area. The ET (enable trap) bit and |
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| 286 | * the CWP (current window pointer) fields of the PSR are considered |
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| 287 | * system wide resources and are not maintained on a per-thread basis. |
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| 288 | */ |
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| 289 | |
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| 290 | #ifndef ASM |
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| 291 | |
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| 292 | typedef struct { |
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| 293 | /* |
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| 294 | * Using a double g0_g1 will put everything in this structure on a |
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| 295 | * double word boundary which allows us to use double word loads |
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| 296 | * and stores safely in the context switch. |
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| 297 | */ |
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| 298 | double g0_g1; |
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| 299 | unsigned32 g2; |
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| 300 | unsigned32 g3; |
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| 301 | unsigned32 g4; |
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| 302 | unsigned32 g5; |
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| 303 | unsigned32 g6; |
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| 304 | unsigned32 g7; |
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| 305 | |
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| 306 | unsigned32 l0; |
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| 307 | unsigned32 l1; |
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| 308 | unsigned32 l2; |
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| 309 | unsigned32 l3; |
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| 310 | unsigned32 l4; |
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| 311 | unsigned32 l5; |
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| 312 | unsigned32 l6; |
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| 313 | unsigned32 l7; |
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| 314 | |
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| 315 | unsigned32 i0; |
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| 316 | unsigned32 i1; |
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| 317 | unsigned32 i2; |
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| 318 | unsigned32 i3; |
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| 319 | unsigned32 i4; |
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| 320 | unsigned32 i5; |
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| 321 | unsigned32 i6_fp; |
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| 322 | unsigned32 i7; |
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| 323 | |
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| 324 | unsigned32 o0; |
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| 325 | unsigned32 o1; |
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| 326 | unsigned32 o2; |
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| 327 | unsigned32 o3; |
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| 328 | unsigned32 o4; |
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| 329 | unsigned32 o5; |
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| 330 | unsigned32 o6_sp; |
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| 331 | unsigned32 o7; |
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| 332 | |
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| 333 | unsigned32 psr; |
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| 334 | } Context_Control; |
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| 335 | |
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| 336 | #endif /* ASM */ |
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| 337 | |
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| 338 | /* |
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| 339 | * Offsets of fields with Context_Control for assembly routines. |
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| 340 | */ |
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| 341 | |
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| 342 | #define G0_OFFSET 0x00 |
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| 343 | #define G1_OFFSET 0x04 |
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| 344 | #define G2_OFFSET 0x08 |
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| 345 | #define G3_OFFSET 0x0C |
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| 346 | #define G4_OFFSET 0x10 |
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| 347 | #define G5_OFFSET 0x14 |
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| 348 | #define G6_OFFSET 0x18 |
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| 349 | #define G7_OFFSET 0x1C |
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| 350 | |
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| 351 | #define L0_OFFSET 0x20 |
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| 352 | #define L1_OFFSET 0x24 |
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| 353 | #define L2_OFFSET 0x28 |
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| 354 | #define L3_OFFSET 0x2C |
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| 355 | #define L4_OFFSET 0x30 |
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| 356 | #define L5_OFFSET 0x34 |
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| 357 | #define L6_OFFSET 0x38 |
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| 358 | #define L7_OFFSET 0x3C |
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| 359 | |
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| 360 | #define I0_OFFSET 0x40 |
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| 361 | #define I1_OFFSET 0x44 |
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| 362 | #define I2_OFFSET 0x48 |
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| 363 | #define I3_OFFSET 0x4C |
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| 364 | #define I4_OFFSET 0x50 |
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| 365 | #define I5_OFFSET 0x54 |
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| 366 | #define I6_FP_OFFSET 0x58 |
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| 367 | #define I7_OFFSET 0x5C |
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| 368 | |
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| 369 | #define O0_OFFSET 0x60 |
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| 370 | #define O1_OFFSET 0x64 |
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| 371 | #define O2_OFFSET 0x68 |
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| 372 | #define O3_OFFSET 0x6C |
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| 373 | #define O4_OFFSET 0x70 |
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| 374 | #define O5_OFFSET 0x74 |
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| 375 | #define O6_SP_OFFSET 0x78 |
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| 376 | #define O7_OFFSET 0x7C |
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| 377 | |
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| 378 | #define PSR_OFFSET 0x80 |
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| 379 | |
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| 380 | #define CONTEXT_CONTROL_SIZE 0x84 |
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| 381 | |
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| 382 | /* |
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| 383 | * The floating point context area. |
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| 384 | */ |
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| 385 | |
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| 386 | #ifndef ASM |
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| 387 | |
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| 388 | typedef struct { |
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| 389 | double f0_f1; |
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| 390 | double f2_f3; |
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| 391 | double f4_f5; |
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| 392 | double f6_f7; |
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| 393 | double f8_f9; |
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| 394 | double f10_f11; |
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| 395 | double f12_f13; |
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| 396 | double f14_f15; |
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| 397 | double f16_f17; |
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| 398 | double f18_f19; |
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| 399 | double f20_f21; |
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| 400 | double f22_f23; |
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| 401 | double f24_f25; |
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| 402 | double f26_f27; |
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| 403 | double f28_f29; |
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| 404 | double f30_f31; |
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| 405 | unsigned32 fsr; |
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| 406 | } Context_Control_fp; |
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| 407 | |
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| 408 | #endif /* ASM */ |
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| 409 | |
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| 410 | /* |
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| 411 | * Offsets of fields with Context_Control_fp for assembly routines. |
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| 412 | */ |
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| 413 | |
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| 414 | #define FO_F1_OFFSET 0x00 |
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| 415 | #define F2_F3_OFFSET 0x08 |
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| 416 | #define F4_F5_OFFSET 0x10 |
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| 417 | #define F6_F7_OFFSET 0x18 |
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| 418 | #define F8_F9_OFFSET 0x20 |
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| 419 | #define F1O_F11_OFFSET 0x28 |
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| 420 | #define F12_F13_OFFSET 0x30 |
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| 421 | #define F14_F15_OFFSET 0x38 |
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| 422 | #define F16_F17_OFFSET 0x40 |
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| 423 | #define F18_F19_OFFSET 0x48 |
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| 424 | #define F2O_F21_OFFSET 0x50 |
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| 425 | #define F22_F23_OFFSET 0x58 |
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| 426 | #define F24_F25_OFFSET 0x60 |
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| 427 | #define F26_F27_OFFSET 0x68 |
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| 428 | #define F28_F29_OFFSET 0x70 |
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| 429 | #define F3O_F31_OFFSET 0x78 |
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| 430 | #define FSR_OFFSET 0x80 |
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| 431 | |
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| 432 | #define CONTEXT_CONTROL_FP_SIZE 0x84 |
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| 433 | |
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| 434 | #ifndef ASM |
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| 435 | |
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| 436 | /* |
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| 437 | * Context saved on stack for an interrupt. |
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| 438 | * |
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| 439 | * NOTE: The PSR, PC, and NPC are only saved in this structure for the |
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| 440 | * benefit of the user's handler. |
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| 441 | */ |
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| 442 | |
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| 443 | typedef struct { |
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| 444 | CPU_Minimum_stack_frame Stack_frame; |
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| 445 | unsigned32 psr; |
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| 446 | unsigned32 pc; |
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| 447 | unsigned32 npc; |
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| 448 | unsigned32 g1; |
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| 449 | unsigned32 g2; |
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| 450 | unsigned32 g3; |
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| 451 | unsigned32 g4; |
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| 452 | unsigned32 g5; |
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| 453 | unsigned32 g6; |
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| 454 | unsigned32 g7; |
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| 455 | unsigned32 i0; |
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| 456 | unsigned32 i1; |
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| 457 | unsigned32 i2; |
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| 458 | unsigned32 i3; |
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| 459 | unsigned32 i4; |
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| 460 | unsigned32 i5; |
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| 461 | unsigned32 i6_fp; |
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| 462 | unsigned32 i7; |
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| 463 | unsigned32 y; |
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| 464 | unsigned32 tpc; |
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| 465 | } CPU_Interrupt_frame; |
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| 466 | |
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| 467 | #endif /* ASM */ |
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| 468 | |
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| 469 | /* |
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| 470 | * Offsets of fields with CPU_Interrupt_frame for assembly routines. |
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| 471 | */ |
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| 472 | |
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| 473 | #define ISF_STACK_FRAME_OFFSET 0x00 |
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| 474 | #define ISF_PSR_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x00 |
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| 475 | #define ISF_PC_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x04 |
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| 476 | #define ISF_NPC_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x08 |
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| 477 | #define ISF_G1_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x0c |
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| 478 | #define ISF_G2_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x10 |
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| 479 | #define ISF_G3_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x14 |
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| 480 | #define ISF_G4_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x18 |
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| 481 | #define ISF_G5_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x1c |
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| 482 | #define ISF_G6_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x20 |
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| 483 | #define ISF_G7_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x24 |
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| 484 | #define ISF_I0_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x28 |
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| 485 | #define ISF_I1_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x2c |
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| 486 | #define ISF_I2_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x30 |
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| 487 | #define ISF_I3_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x34 |
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| 488 | #define ISF_I4_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x38 |
---|
| 489 | #define ISF_I5_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x3c |
---|
| 490 | #define ISF_I6_FP_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x40 |
---|
| 491 | #define ISF_I7_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x44 |
---|
| 492 | #define ISF_Y_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x48 |
---|
| 493 | #define ISF_TPC_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x4c |
---|
| 494 | |
---|
| 495 | #define CONTEXT_CONTROL_INTERRUPT_FRAME_SIZE CPU_MINIMUM_STACK_FRAME_SIZE + 0x50 |
---|
| 496 | #ifndef ASM |
---|
| 497 | |
---|
| 498 | /* |
---|
| 499 | * The following table contains the information required to configure |
---|
| 500 | * the processor specific parameters. |
---|
| 501 | */ |
---|
| 502 | |
---|
| 503 | typedef struct { |
---|
| 504 | void (*pretasking_hook)( void ); |
---|
| 505 | void (*predriver_hook)( void ); |
---|
| 506 | void (*postdriver_hook)( void ); |
---|
| 507 | void (*idle_task)( void ); |
---|
| 508 | boolean do_zero_of_workspace; |
---|
| 509 | unsigned32 idle_task_stack_size; |
---|
| 510 | unsigned32 interrupt_stack_size; |
---|
| 511 | unsigned32 extra_mpci_receive_server_stack; |
---|
| 512 | void * (*stack_allocate_hook)( unsigned32 ); |
---|
| 513 | void (*stack_free_hook)( void* ); |
---|
| 514 | /* end of fields required on all CPUs */ |
---|
| 515 | |
---|
| 516 | } rtems_cpu_table; |
---|
| 517 | |
---|
[458bd34] | 518 | /* |
---|
| 519 | * Macros to access required entires in the CPU Table are in |
---|
| 520 | * the file rtems/system.h. |
---|
| 521 | */ |
---|
| 522 | |
---|
| 523 | /* |
---|
| 524 | * Macros to access SPARC specific additions to the CPU Table |
---|
| 525 | */ |
---|
| 526 | |
---|
| 527 | /* There are no CPU specific additions to the CPU Table for this port. */ |
---|
| 528 | |
---|
[7908ba5b] | 529 | /* |
---|
| 530 | * This variable is contains the initialize context for the FP unit. |
---|
| 531 | * It is filled in by _CPU_Initialize and copied into the task's FP |
---|
| 532 | * context area during _CPU_Context_Initialize. |
---|
| 533 | */ |
---|
| 534 | |
---|
| 535 | SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context CPU_STRUCTURE_ALIGNMENT; |
---|
| 536 | |
---|
| 537 | /* |
---|
| 538 | * This stack is allocated by the Interrupt Manager and the switch |
---|
| 539 | * is performed in _ISR_Handler. These variables contain pointers |
---|
| 540 | * to the lowest and highest addresses in the chunk of memory allocated |
---|
| 541 | * for the interrupt stack. Since it is unknown whether the stack |
---|
| 542 | * grows up or down (in general), this give the CPU dependent |
---|
| 543 | * code the option of picking the version it wants to use. Thus |
---|
| 544 | * both must be present if either is. |
---|
| 545 | * |
---|
| 546 | * The SPARC supports a software based interrupt stack and these |
---|
| 547 | * are required. |
---|
| 548 | */ |
---|
| 549 | |
---|
| 550 | SCORE_EXTERN void *_CPU_Interrupt_stack_low; |
---|
| 551 | SCORE_EXTERN void *_CPU_Interrupt_stack_high; |
---|
| 552 | |
---|
| 553 | /* |
---|
| 554 | * The following type defines an entry in the SPARC's trap table. |
---|
| 555 | * |
---|
| 556 | * NOTE: The instructions chosen are RTEMS dependent although one is |
---|
| 557 | * obligated to use two of the four instructions to perform a |
---|
| 558 | * long jump. The other instructions load one register with the |
---|
| 559 | * trap type (a.k.a. vector) and another with the psr. |
---|
| 560 | */ |
---|
| 561 | |
---|
| 562 | typedef struct { |
---|
| 563 | unsigned32 mov_psr_l0; /* mov %psr, %l0 */ |
---|
| 564 | unsigned32 sethi_of_handler_to_l4; /* sethi %hi(_handler), %l4 */ |
---|
| 565 | unsigned32 jmp_to_low_of_handler_plus_l4; /* jmp %l4 + %lo(_handler) */ |
---|
| 566 | unsigned32 mov_vector_l3; /* mov _vector, %l3 */ |
---|
| 567 | } CPU_Trap_table_entry; |
---|
| 568 | |
---|
| 569 | /* |
---|
| 570 | * This is the set of opcodes for the instructions loaded into a trap |
---|
| 571 | * table entry. The routine which installs a handler is responsible |
---|
| 572 | * for filling in the fields for the _handler address and the _vector |
---|
| 573 | * trap type. |
---|
| 574 | * |
---|
| 575 | * The constants following this structure are masks for the fields which |
---|
| 576 | * must be filled in when the handler is installed. |
---|
| 577 | */ |
---|
| 578 | |
---|
| 579 | extern const CPU_Trap_table_entry _CPU_Trap_slot_template; |
---|
| 580 | |
---|
| 581 | /* |
---|
| 582 | * This is the executive's trap table which is installed into the TBR |
---|
| 583 | * register. |
---|
| 584 | * |
---|
| 585 | * NOTE: Unfortunately, this must be aligned on a 4096 byte boundary. |
---|
| 586 | * The GNU tools as of binutils 2.5.2 and gcc 2.7.0 would not |
---|
| 587 | * align an entity to anything greater than a 512 byte boundary. |
---|
| 588 | * |
---|
| 589 | * Because of this, we pull a little bit of a trick. We allocate |
---|
| 590 | * enough memory so we can grab an address on a 4096 byte boundary |
---|
| 591 | * from this area. |
---|
| 592 | */ |
---|
| 593 | |
---|
| 594 | #define SPARC_TRAP_TABLE_ALIGNMENT 4096 |
---|
| 595 | |
---|
| 596 | #ifndef NO_TABLE_MOVE |
---|
| 597 | |
---|
| 598 | SCORE_EXTERN unsigned8 _CPU_Trap_Table_area[ 8192 ] |
---|
| 599 | __attribute__ ((aligned (SPARC_TRAP_TABLE_ALIGNMENT))); |
---|
| 600 | #endif |
---|
| 601 | |
---|
| 602 | |
---|
| 603 | /* |
---|
| 604 | * The size of the floating point context area. |
---|
| 605 | */ |
---|
| 606 | |
---|
| 607 | #define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) |
---|
| 608 | |
---|
| 609 | #endif |
---|
| 610 | |
---|
| 611 | /* |
---|
| 612 | * Amount of extra stack (above minimum stack size) required by |
---|
| 613 | * MPCI receive server thread. Remember that in a multiprocessor |
---|
| 614 | * system this thread must exist and be able to process all directives. |
---|
| 615 | */ |
---|
| 616 | |
---|
| 617 | #define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 1024 |
---|
| 618 | |
---|
| 619 | /* |
---|
| 620 | * This defines the number of entries in the ISR_Vector_table managed |
---|
| 621 | * by the executive. |
---|
| 622 | * |
---|
| 623 | * On the SPARC, there are really only 256 vectors. However, the executive |
---|
| 624 | * has no easy, fast, reliable way to determine which traps are synchronous |
---|
| 625 | * and which are asynchronous. By default, synchronous traps return to the |
---|
| 626 | * instruction which caused the interrupt. So if you install a software |
---|
| 627 | * trap handler as an executive interrupt handler (which is desirable since |
---|
| 628 | * RTEMS takes care of window and register issues), then the executive needs |
---|
| 629 | * to know that the return address is to the trap rather than the instruction |
---|
| 630 | * following the trap. |
---|
| 631 | * |
---|
| 632 | * So vectors 0 through 255 are treated as regular asynchronous traps which |
---|
| 633 | * provide the "correct" return address. Vectors 256 through 512 are assumed |
---|
| 634 | * by the executive to be synchronous and to require that the return address |
---|
| 635 | * be fudged. |
---|
| 636 | * |
---|
| 637 | * If you use this mechanism to install a trap handler which must reexecute |
---|
| 638 | * the instruction which caused the trap, then it should be installed as |
---|
| 639 | * an asynchronous trap. This will avoid the executive changing the return |
---|
| 640 | * address. |
---|
| 641 | */ |
---|
| 642 | |
---|
| 643 | #define CPU_INTERRUPT_NUMBER_OF_VECTORS 256 |
---|
| 644 | #define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER 511 |
---|
| 645 | |
---|
| 646 | #define SPARC_SYNCHRONOUS_TRAP_BIT_MASK 0x100 |
---|
| 647 | #define SPARC_ASYNCHRONOUS_TRAP( _trap ) (_trap) |
---|
| 648 | #define SPARC_SYNCHRONOUS_TRAP( _trap ) ((_trap) + 256 ) |
---|
| 649 | |
---|
| 650 | #define SPARC_REAL_TRAP_NUMBER( _trap ) ((_trap) % 256) |
---|
| 651 | |
---|
[4db30283] | 652 | /* |
---|
| 653 | * This is defined if the port has a special way to report the ISR nesting |
---|
| 654 | * level. Most ports maintain the variable _ISR_Nest_level. |
---|
| 655 | */ |
---|
| 656 | |
---|
| 657 | #define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE |
---|
| 658 | |
---|
[7908ba5b] | 659 | /* |
---|
| 660 | * Should be large enough to run all tests. This insures |
---|
| 661 | * that a "reasonable" small application should not have any problems. |
---|
| 662 | * |
---|
| 663 | * This appears to be a fairly generous number for the SPARC since |
---|
| 664 | * represents a call depth of about 20 routines based on the minimum |
---|
| 665 | * stack frame. |
---|
| 666 | */ |
---|
| 667 | |
---|
[20385957] | 668 | #define CPU_STACK_MINIMUM_SIZE (1024*4) |
---|
[7908ba5b] | 669 | |
---|
| 670 | /* |
---|
| 671 | * CPU's worst alignment requirement for data types on a byte boundary. This |
---|
| 672 | * alignment does not take into account the requirements for the stack. |
---|
| 673 | * |
---|
| 674 | * On the SPARC, this is required for double word loads and stores. |
---|
| 675 | */ |
---|
| 676 | |
---|
| 677 | #define CPU_ALIGNMENT 8 |
---|
| 678 | |
---|
| 679 | /* |
---|
| 680 | * This number corresponds to the byte alignment requirement for the |
---|
| 681 | * heap handler. This alignment requirement may be stricter than that |
---|
| 682 | * for the data types alignment specified by CPU_ALIGNMENT. It is |
---|
| 683 | * common for the heap to follow the same alignment requirement as |
---|
| 684 | * CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict enough for the heap, |
---|
| 685 | * then this should be set to CPU_ALIGNMENT. |
---|
| 686 | * |
---|
| 687 | * NOTE: This does not have to be a power of 2. It does have to |
---|
| 688 | * be greater or equal to than CPU_ALIGNMENT. |
---|
| 689 | */ |
---|
| 690 | |
---|
| 691 | #define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT |
---|
| 692 | |
---|
| 693 | /* |
---|
| 694 | * This number corresponds to the byte alignment requirement for memory |
---|
| 695 | * buffers allocated by the partition manager. This alignment requirement |
---|
| 696 | * may be stricter than that for the data types alignment specified by |
---|
| 697 | * CPU_ALIGNMENT. It is common for the partition to follow the same |
---|
| 698 | * alignment requirement as CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict |
---|
| 699 | * enough for the partition, then this should be set to CPU_ALIGNMENT. |
---|
| 700 | * |
---|
| 701 | * NOTE: This does not have to be a power of 2. It does have to |
---|
| 702 | * be greater or equal to than CPU_ALIGNMENT. |
---|
| 703 | */ |
---|
| 704 | |
---|
| 705 | #define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT |
---|
| 706 | |
---|
| 707 | /* |
---|
| 708 | * This number corresponds to the byte alignment requirement for the |
---|
| 709 | * stack. This alignment requirement may be stricter than that for the |
---|
| 710 | * data types alignment specified by CPU_ALIGNMENT. If the CPU_ALIGNMENT |
---|
| 711 | * is strict enough for the stack, then this should be set to 0. |
---|
| 712 | * |
---|
| 713 | * NOTE: This must be a power of 2 either 0 or greater than CPU_ALIGNMENT. |
---|
| 714 | * |
---|
| 715 | * The alignment restrictions for the SPARC are not that strict but this |
---|
| 716 | * should unsure that the stack is always sufficiently alignment that the |
---|
| 717 | * window overflow, underflow, and flush routines can use double word loads |
---|
| 718 | * and stores. |
---|
| 719 | */ |
---|
| 720 | |
---|
| 721 | #define CPU_STACK_ALIGNMENT 16 |
---|
| 722 | |
---|
| 723 | #ifndef ASM |
---|
| 724 | |
---|
[b73e57b] | 725 | extern unsigned int sparc_disable_interrupts(); |
---|
| 726 | extern void sparc_enable_interrupts(); |
---|
| 727 | |
---|
[fe7acdcf] | 728 | /* |
---|
| 729 | * ISR handler macros |
---|
| 730 | */ |
---|
| 731 | |
---|
| 732 | /* |
---|
| 733 | * Support routine to initialize the RTEMS vector table after it is allocated. |
---|
| 734 | */ |
---|
| 735 | |
---|
| 736 | #define _CPU_Initialize_vectors() |
---|
[7908ba5b] | 737 | |
---|
| 738 | /* |
---|
| 739 | * Disable all interrupts for a critical section. The previous |
---|
| 740 | * level is returned in _level. |
---|
| 741 | */ |
---|
| 742 | |
---|
| 743 | #define _CPU_ISR_Disable( _level ) \ |
---|
[b73e57b] | 744 | (_level) = sparc_disable_interrupts() |
---|
[7908ba5b] | 745 | |
---|
| 746 | /* |
---|
| 747 | * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). |
---|
| 748 | * This indicates the end of a critical section. The parameter |
---|
| 749 | * _level is not modified. |
---|
| 750 | */ |
---|
| 751 | |
---|
| 752 | #define _CPU_ISR_Enable( _level ) \ |
---|
| 753 | sparc_enable_interrupts( _level ) |
---|
| 754 | /* |
---|
| 755 | * This temporarily restores the interrupt to _level before immediately |
---|
| 756 | * disabling them again. This is used to divide long critical |
---|
| 757 | * sections into two or more parts. The parameter _level is not |
---|
| 758 | * modified. |
---|
| 759 | */ |
---|
| 760 | |
---|
| 761 | #define _CPU_ISR_Flash( _level ) \ |
---|
| 762 | sparc_flash_interrupts( _level ) |
---|
| 763 | |
---|
| 764 | /* |
---|
| 765 | * Map interrupt level in task mode onto the hardware that the CPU |
---|
| 766 | * actually provides. Currently, interrupt levels which do not |
---|
| 767 | * map onto the CPU in a straight fashion are undefined. |
---|
| 768 | */ |
---|
| 769 | |
---|
| 770 | #define _CPU_ISR_Set_level( _newlevel ) \ |
---|
[b73e57b] | 771 | sparc_enable_interrupts( _newlevel << 8) |
---|
[7908ba5b] | 772 | |
---|
| 773 | unsigned32 _CPU_ISR_Get_level( void ); |
---|
| 774 | |
---|
| 775 | /* end of ISR handler macros */ |
---|
| 776 | |
---|
| 777 | /* Context handler macros */ |
---|
| 778 | |
---|
| 779 | /* |
---|
| 780 | * Initialize the context to a state suitable for starting a |
---|
| 781 | * task after a context restore operation. Generally, this |
---|
| 782 | * involves: |
---|
| 783 | * |
---|
| 784 | * - setting a starting address |
---|
| 785 | * - preparing the stack |
---|
| 786 | * - preparing the stack and frame pointers |
---|
| 787 | * - setting the proper interrupt level in the context |
---|
| 788 | * - initializing the floating point context |
---|
| 789 | * |
---|
| 790 | * NOTE: Implemented as a subroutine for the SPARC port. |
---|
| 791 | */ |
---|
| 792 | |
---|
| 793 | void _CPU_Context_Initialize( |
---|
| 794 | Context_Control *the_context, |
---|
| 795 | unsigned32 *stack_base, |
---|
| 796 | unsigned32 size, |
---|
| 797 | unsigned32 new_level, |
---|
| 798 | void *entry_point, |
---|
| 799 | boolean is_fp |
---|
| 800 | ); |
---|
| 801 | |
---|
| 802 | /* |
---|
| 803 | * This routine is responsible for somehow restarting the currently |
---|
| 804 | * executing task. |
---|
| 805 | * |
---|
| 806 | * On the SPARC, this is is relatively painless but requires a small |
---|
| 807 | * amount of wrapper code before using the regular restore code in |
---|
| 808 | * of the context switch. |
---|
| 809 | */ |
---|
| 810 | |
---|
| 811 | #define _CPU_Context_Restart_self( _the_context ) \ |
---|
| 812 | _CPU_Context_restore( (_the_context) ); |
---|
| 813 | |
---|
| 814 | /* |
---|
| 815 | * The FP context area for the SPARC is a simple structure and nothing |
---|
| 816 | * special is required to find the "starting load point" |
---|
| 817 | */ |
---|
| 818 | |
---|
| 819 | #define _CPU_Context_Fp_start( _base, _offset ) \ |
---|
| 820 | ( (void *) _Addresses_Add_offset( (_base), (_offset) ) ) |
---|
| 821 | |
---|
| 822 | /* |
---|
| 823 | * This routine initializes the FP context area passed to it to. |
---|
| 824 | * |
---|
| 825 | * The SPARC allows us to use the simple initialization model |
---|
| 826 | * in which an "initial" FP context was saved into _CPU_Null_fp_context |
---|
| 827 | * at CPU initialization and it is simply copied into the destination |
---|
| 828 | * context. |
---|
| 829 | */ |
---|
| 830 | |
---|
| 831 | #define _CPU_Context_Initialize_fp( _destination ) \ |
---|
| 832 | do { \ |
---|
| 833 | *((Context_Control_fp *) *((void **) _destination)) = _CPU_Null_fp_context; \ |
---|
| 834 | } while (0) |
---|
| 835 | |
---|
| 836 | /* end of Context handler macros */ |
---|
| 837 | |
---|
| 838 | /* Fatal Error manager macros */ |
---|
| 839 | |
---|
| 840 | /* |
---|
| 841 | * This routine copies _error into a known place -- typically a stack |
---|
| 842 | * location or a register, optionally disables interrupts, and |
---|
| 843 | * halts/stops the CPU. |
---|
| 844 | */ |
---|
| 845 | |
---|
| 846 | #define _CPU_Fatal_halt( _error ) \ |
---|
| 847 | do { \ |
---|
| 848 | unsigned32 level; \ |
---|
| 849 | \ |
---|
[b73e57b] | 850 | level = sparc_disable_interrupts(); \ |
---|
[7908ba5b] | 851 | asm volatile ( "mov %0, %%g1 " : "=r" (level) : "0" (level) ); \ |
---|
| 852 | while (1); /* loop forever */ \ |
---|
| 853 | } while (0) |
---|
| 854 | |
---|
| 855 | /* end of Fatal Error manager macros */ |
---|
| 856 | |
---|
| 857 | /* Bitfield handler macros */ |
---|
| 858 | |
---|
| 859 | /* |
---|
| 860 | * The SPARC port uses the generic C algorithm for bitfield scan if the |
---|
| 861 | * CPU model does not have a scan instruction. |
---|
| 862 | */ |
---|
| 863 | |
---|
| 864 | #if ( SPARC_HAS_BITSCAN == 0 ) |
---|
| 865 | #define CPU_USE_GENERIC_BITFIELD_CODE TRUE |
---|
| 866 | #define CPU_USE_GENERIC_BITFIELD_DATA TRUE |
---|
| 867 | #else |
---|
| 868 | #error "scan instruction not currently supported by RTEMS!!" |
---|
| 869 | #endif |
---|
| 870 | |
---|
| 871 | /* end of Bitfield handler macros */ |
---|
| 872 | |
---|
| 873 | /* Priority handler handler macros */ |
---|
| 874 | |
---|
| 875 | /* |
---|
| 876 | * The SPARC port uses the generic C algorithm for bitfield scan if the |
---|
| 877 | * CPU model does not have a scan instruction. |
---|
| 878 | */ |
---|
| 879 | |
---|
| 880 | #if ( SPARC_HAS_BITSCAN == 1 ) |
---|
| 881 | #error "scan instruction not currently supported by RTEMS!!" |
---|
| 882 | #endif |
---|
| 883 | |
---|
| 884 | /* end of Priority handler macros */ |
---|
| 885 | |
---|
| 886 | /* functions */ |
---|
| 887 | |
---|
| 888 | /* |
---|
| 889 | * _CPU_Initialize |
---|
| 890 | * |
---|
| 891 | * This routine performs CPU dependent initialization. |
---|
| 892 | */ |
---|
| 893 | |
---|
| 894 | void _CPU_Initialize( |
---|
| 895 | rtems_cpu_table *cpu_table, |
---|
| 896 | void (*thread_dispatch) |
---|
| 897 | ); |
---|
| 898 | |
---|
| 899 | /* |
---|
| 900 | * _CPU_ISR_install_raw_handler |
---|
| 901 | * |
---|
| 902 | * This routine installs new_handler to be directly called from the trap |
---|
| 903 | * table. |
---|
| 904 | */ |
---|
| 905 | |
---|
| 906 | void _CPU_ISR_install_raw_handler( |
---|
| 907 | unsigned32 vector, |
---|
| 908 | proc_ptr new_handler, |
---|
| 909 | proc_ptr *old_handler |
---|
| 910 | ); |
---|
| 911 | |
---|
| 912 | /* |
---|
| 913 | * _CPU_ISR_install_vector |
---|
| 914 | * |
---|
| 915 | * This routine installs an interrupt vector. |
---|
| 916 | */ |
---|
| 917 | |
---|
| 918 | void _CPU_ISR_install_vector( |
---|
| 919 | unsigned32 vector, |
---|
| 920 | proc_ptr new_handler, |
---|
| 921 | proc_ptr *old_handler |
---|
| 922 | ); |
---|
| 923 | |
---|
| 924 | #if (CPU_PROVIDES_IDLE_THREAD_BODY == TRUE) |
---|
| 925 | |
---|
| 926 | /* |
---|
| 927 | * _CPU_Thread_Idle_body |
---|
| 928 | * |
---|
| 929 | * Some SPARC implementations have low power, sleep, or idle modes. This |
---|
| 930 | * tries to take advantage of those models. |
---|
| 931 | */ |
---|
| 932 | |
---|
| 933 | void _CPU_Thread_Idle_body( void ); |
---|
| 934 | |
---|
| 935 | #endif /* CPU_PROVIDES_IDLE_THREAD_BODY */ |
---|
| 936 | |
---|
| 937 | /* |
---|
| 938 | * _CPU_Context_switch |
---|
| 939 | * |
---|
| 940 | * This routine switches from the run context to the heir context. |
---|
| 941 | */ |
---|
| 942 | |
---|
| 943 | void _CPU_Context_switch( |
---|
| 944 | Context_Control *run, |
---|
| 945 | Context_Control *heir |
---|
| 946 | ); |
---|
| 947 | |
---|
| 948 | /* |
---|
| 949 | * _CPU_Context_restore |
---|
| 950 | * |
---|
| 951 | * This routine is generally used only to restart self in an |
---|
| 952 | * efficient manner. |
---|
| 953 | */ |
---|
| 954 | |
---|
| 955 | void _CPU_Context_restore( |
---|
| 956 | Context_Control *new_context |
---|
| 957 | ); |
---|
| 958 | |
---|
| 959 | /* |
---|
| 960 | * _CPU_Context_save_fp |
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| 961 | * |
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| 962 | * This routine saves the floating point context passed to it. |
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| 963 | */ |
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| 964 | |
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| 965 | void _CPU_Context_save_fp( |
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| 966 | void **fp_context_ptr |
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| 967 | ); |
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| 968 | |
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| 969 | /* |
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| 970 | * _CPU_Context_restore_fp |
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| 971 | * |
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| 972 | * This routine restores the floating point context passed to it. |
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| 973 | */ |
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| 974 | |
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| 975 | void _CPU_Context_restore_fp( |
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| 976 | void **fp_context_ptr |
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| 977 | ); |
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| 978 | |
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| 979 | /* |
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| 980 | * CPU_swap_u32 |
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| 981 | * |
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| 982 | * The following routine swaps the endian format of an unsigned int. |
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| 983 | * It must be static because it is referenced indirectly. |
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| 984 | * |
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| 985 | * This version will work on any processor, but if you come across a better |
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| 986 | * way for the SPARC PLEASE use it. The most common way to swap a 32-bit |
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| 987 | * entity as shown below is not any more efficient on the SPARC. |
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| 988 | * |
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| 989 | * swap least significant two bytes with 16-bit rotate |
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| 990 | * swap upper and lower 16-bits |
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| 991 | * swap most significant two bytes with 16-bit rotate |
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| 992 | * |
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| 993 | * It is not obvious how the SPARC can do significantly better than the |
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| 994 | * generic code. gcc 2.7.0 only generates about 12 instructions for the |
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| 995 | * following code at optimization level four (i.e. -O4). |
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| 996 | */ |
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| 997 | |
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| 998 | static inline unsigned int CPU_swap_u32( |
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| 999 | unsigned int value |
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| 1000 | ) |
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| 1001 | { |
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| 1002 | unsigned32 byte1, byte2, byte3, byte4, swapped; |
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| 1003 | |
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| 1004 | byte4 = (value >> 24) & 0xff; |
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| 1005 | byte3 = (value >> 16) & 0xff; |
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| 1006 | byte2 = (value >> 8) & 0xff; |
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| 1007 | byte1 = value & 0xff; |
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| 1008 | |
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| 1009 | swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; |
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| 1010 | return( swapped ); |
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| 1011 | } |
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| 1012 | |
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| 1013 | #define CPU_swap_u16( value ) \ |
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| 1014 | (((value&0xff) << 8) | ((value >> 8)&0xff)) |
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| 1015 | |
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| 1016 | #endif ASM |
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| 1017 | |
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| 1018 | #ifdef __cplusplus |
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| 1019 | } |
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| 1020 | #endif |
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| 1021 | |
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| 1022 | #endif |
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