[c62d36f] | 1 | /* cpu_asm.s |
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| 2 | * |
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| 3 | * This file contains the basic algorithms for all assembly code used |
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| 4 | * in an specific CPU port of RTEMS. These algorithms must be implemented |
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[9700578] | 5 | * in assembly language. |
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[c62d36f] | 6 | * |
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[c4808ca] | 7 | * COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994. |
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| 8 | * On-Line Applications Research Corporation (OAR). |
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| 9 | * All rights assigned to U.S. Government, 1994. |
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| 10 | * |
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| 11 | * This material may be reproduced by or for the U.S. Government pursuant |
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| 12 | * to the copyright license under the clause at DFARS 252.227-7013. This |
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| 13 | * notice must appear in all copies of this file and its derivatives. |
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| 14 | * |
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| 15 | * Ported to ERC32 implementation of the SPARC by On-Line Applications |
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| 16 | * Research Corporation (OAR) under contract to the European Space |
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| 17 | * Agency (ESA). |
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| 18 | * |
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| 19 | * ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995. |
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| 20 | * European Space Agency. |
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| 21 | * |
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[c62d36f] | 22 | * $Id$ |
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| 23 | */ |
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| 24 | |
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| 25 | #include <asm.h> |
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| 26 | #include <rtems/score/cpu.h> |
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| 27 | |
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[9700578] | 28 | #if (SPARC_HAS_FPU == 1) |
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| 29 | |
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[c62d36f] | 30 | /* |
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[9700578] | 31 | * void _CPU_Context_save_fp( |
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| 32 | * void **fp_context_ptr |
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| 33 | * ) |
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[c62d36f] | 34 | * |
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| 35 | * This routine is responsible for saving the FP context |
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| 36 | * at *fp_context_ptr. If the point to load the FP context |
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| 37 | * from is changed then the pointer is modified by this routine. |
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| 38 | * |
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[9700578] | 39 | * NOTE: See the README in this directory for information on the |
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| 40 | * management of the "EF" bit in the PSR. |
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[c62d36f] | 41 | */ |
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| 42 | |
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| 43 | .align 4 |
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| 44 | PUBLIC(_CPU_Context_save_fp) |
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| 45 | SYM(_CPU_Context_save_fp): |
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[9700578] | 46 | save %sp, -CPU_MINIMUM_STACK_FRAME_SIZE, %sp |
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| 47 | |
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| 48 | /* |
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| 49 | * The following enables the floating point unit. |
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| 50 | */ |
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| 51 | |
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| 52 | mov %psr, %l0 |
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| 53 | sethi %hi(SPARC_PSR_EF_MASK), %l1 |
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| 54 | or %l1, %lo(SPARC_PSR_EF_MASK), %l1 |
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| 55 | or %l0, %l1, %l0 |
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| 56 | mov %l0, %psr ! **** ENABLE FLOAT ACCESS **** |
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| 57 | |
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| 58 | ld [%i0], %l0 |
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| 59 | std %f0, [%l0 + FO_F1_OFFSET] |
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| 60 | std %f2, [%l0 + F2_F3_OFFSET] |
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| 61 | std %f4, [%l0 + F4_F5_OFFSET] |
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| 62 | std %f6, [%l0 + F6_F7_OFFSET] |
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| 63 | std %f8, [%l0 + F8_F9_OFFSET] |
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| 64 | std %f10, [%l0 + F1O_F11_OFFSET] |
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| 65 | std %f12, [%l0 + F12_F13_OFFSET] |
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| 66 | std %f14, [%l0 + F14_F15_OFFSET] |
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| 67 | std %f16, [%l0 + F16_F17_OFFSET] |
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| 68 | std %f18, [%l0 + F18_F19_OFFSET] |
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| 69 | std %f20, [%l0 + F2O_F21_OFFSET] |
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| 70 | std %f22, [%l0 + F22_F23_OFFSET] |
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| 71 | std %f24, [%l0 + F24_F25_OFFSET] |
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| 72 | std %f26, [%l0 + F26_F27_OFFSET] |
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| 73 | std %f28, [%l0 + F28_F29_OFFSET] |
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| 74 | std %f30, [%l0 + F3O_F31_OFFSET] |
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| 75 | st %fsr, [%l0 + FSR_OFFSET] |
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[c62d36f] | 76 | ret |
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| 77 | restore |
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| 78 | |
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| 79 | /* |
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[9700578] | 80 | * void _CPU_Context_restore_fp( |
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| 81 | * void **fp_context_ptr |
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| 82 | * ) |
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[c62d36f] | 83 | * |
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| 84 | * This routine is responsible for restoring the FP context |
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| 85 | * at *fp_context_ptr. If the point to load the FP context |
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| 86 | * from is changed then the pointer is modified by this routine. |
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| 87 | * |
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[9700578] | 88 | * NOTE: See the README in this directory for information on the |
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| 89 | * management of the "EF" bit in the PSR. |
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[c62d36f] | 90 | */ |
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| 91 | |
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| 92 | .align 4 |
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| 93 | PUBLIC(_CPU_Context_restore_fp) |
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| 94 | SYM(_CPU_Context_restore_fp): |
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[9700578] | 95 | save %sp, -CPU_MINIMUM_STACK_FRAME_SIZE , %sp |
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| 96 | |
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| 97 | /* |
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| 98 | * The following enables the floating point unit. |
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| 99 | */ |
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| 100 | |
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| 101 | mov %psr, %l0 |
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| 102 | sethi %hi(SPARC_PSR_EF_MASK), %l1 |
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| 103 | or %l1, %lo(SPARC_PSR_EF_MASK), %l1 |
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| 104 | or %l0, %l1, %l0 |
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| 105 | mov %l0, %psr ! **** ENABLE FLOAT ACCESS **** |
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| 106 | |
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| 107 | ld [%i0], %l0 |
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| 108 | ldd [%l0 + FO_F1_OFFSET], %f0 |
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| 109 | ldd [%l0 + F2_F3_OFFSET], %f2 |
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| 110 | ldd [%l0 + F4_F5_OFFSET], %f4 |
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| 111 | ldd [%l0 + F6_F7_OFFSET], %f6 |
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| 112 | ldd [%l0 + F8_F9_OFFSET], %f8 |
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| 113 | ldd [%l0 + F1O_F11_OFFSET], %f10 |
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| 114 | ldd [%l0 + F12_F13_OFFSET], %f12 |
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| 115 | ldd [%l0 + F14_F15_OFFSET], %f14 |
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| 116 | ldd [%l0 + F16_F17_OFFSET], %f16 |
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| 117 | ldd [%l0 + F18_F19_OFFSET], %f18 |
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| 118 | ldd [%l0 + F2O_F21_OFFSET], %f20 |
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| 119 | ldd [%l0 + F22_F23_OFFSET], %f22 |
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| 120 | ldd [%l0 + F24_F25_OFFSET], %f24 |
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| 121 | ldd [%l0 + F26_F27_OFFSET], %f26 |
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| 122 | ldd [%l0 + F28_F29_OFFSET], %f28 |
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| 123 | ldd [%l0 + F3O_F31_OFFSET], %f30 |
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| 124 | ld [%l0 + FSR_OFFSET], %fsr |
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[c62d36f] | 125 | ret |
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| 126 | restore |
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| 127 | |
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[9700578] | 128 | #endif /* SPARC_HAS_FPU */ |
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| 129 | |
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| 130 | /* |
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[c62d36f] | 131 | * void _CPU_Context_switch( |
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| 132 | * Context_Control *run, |
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| 133 | * Context_Control *heir |
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| 134 | * ) |
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[9700578] | 135 | * |
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| 136 | * This routine performs a normal non-FP context switch. |
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[c62d36f] | 137 | */ |
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| 138 | |
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| 139 | .align 4 |
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| 140 | PUBLIC(_CPU_Context_switch) |
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| 141 | SYM(_CPU_Context_switch): |
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[9700578] | 142 | ! skip g0 |
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| 143 | st %g1, [%o0 + G1_OFFSET] ! save the global registers |
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| 144 | std %g2, [%o0 + G2_OFFSET] |
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| 145 | std %g4, [%o0 + G4_OFFSET] |
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| 146 | std %g6, [%o0 + G6_OFFSET] |
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| 147 | |
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| 148 | std %l0, [%o0 + L0_OFFSET] ! save the local registers |
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| 149 | std %l2, [%o0 + L2_OFFSET] |
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| 150 | std %l4, [%o0 + L4_OFFSET] |
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| 151 | std %l6, [%o0 + L6_OFFSET] |
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| 152 | |
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| 153 | std %i0, [%o0 + I0_OFFSET] ! save the input registers |
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| 154 | std %i2, [%o0 + I2_OFFSET] |
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| 155 | std %i4, [%o0 + I4_OFFSET] |
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| 156 | std %i6, [%o0 + I6_FP_OFFSET] |
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| 157 | |
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| 158 | std %o0, [%o0 + O0_OFFSET] ! save the output registers |
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| 159 | std %o2, [%o0 + O2_OFFSET] |
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| 160 | std %o4, [%o0 + O4_OFFSET] |
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| 161 | std %o6, [%o0 + O6_SP_OFFSET] |
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| 162 | |
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| 163 | rd %psr, %o2 |
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| 164 | st %o2, [%o0 + PSR_OFFSET] ! save status register |
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| 165 | |
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| 166 | /* |
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| 167 | * This is entered from _CPU_Context_restore with: |
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| 168 | * o1 = context to restore |
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| 169 | * o2 = psr |
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| 170 | */ |
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| 171 | |
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| 172 | PUBLIC(_CPU_Context_restore_heir) |
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| 173 | SYM(_CPU_Context_restore_heir): |
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| 174 | /* |
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| 175 | * Flush all windows with valid contents except the current one. |
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| 176 | * In examining the set register windows, one may logically divide |
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| 177 | * the windows into sets (some of which may be empty) based on their |
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| 178 | * current status: |
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| 179 | * |
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| 180 | * + current (i.e. in use), |
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| 181 | * + used (i.e. a restore would not trap) |
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| 182 | * + invalid (i.e. 1 in corresponding bit in WIM) |
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| 183 | * + unused |
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| 184 | * |
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| 185 | * Either the used or unused set of windows may be empty. |
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| 186 | * |
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| 187 | * NOTE: We assume only one bit is set in the WIM at a time. |
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| 188 | * |
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| 189 | * Given a CWP of 5 and a WIM of 0x1, the registers are divided |
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| 190 | * into sets as follows: |
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| 191 | * |
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| 192 | * + 0 - invalid |
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| 193 | * + 1-4 - unused |
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| 194 | * + 5 - current |
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| 195 | * + 6-7 - used |
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| 196 | * |
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| 197 | * In this case, we only would save the used windows -- 6 and 7. |
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| 198 | * |
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| 199 | * Traps are disabled for the same logical period as in a |
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| 200 | * flush all windows trap handler. |
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| 201 | * |
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| 202 | * Register Usage while saving the windows: |
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| 203 | * g1 = current PSR |
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| 204 | * g2 = current wim |
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| 205 | * g3 = CWP |
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| 206 | * g4 = wim scratch |
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| 207 | * g5 = scratch |
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| 208 | */ |
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| 209 | |
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| 210 | ld [%o1 + PSR_OFFSET], %g1 ! g1 = saved psr |
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| 211 | |
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| 212 | and %o2, SPARC_PSR_CWP_MASK, %g3 ! g3 = CWP |
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| 213 | ! g1 = psr w/o cwp |
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| 214 | andn %g1, SPARC_PSR_ET_MASK | SPARC_PSR_CWP_MASK, %g1 |
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| 215 | or %g1, %g3, %g1 ! g1 = heirs psr |
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| 216 | mov %g1, %psr ! restore status register and |
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| 217 | ! **** DISABLE TRAPS **** |
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| 218 | mov %wim, %g2 ! g2 = wim |
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| 219 | mov 1, %g4 |
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| 220 | sll %g4, %g3, %g4 ! g4 = WIM mask for CW invalid |
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| 221 | |
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| 222 | save_frame_loop: |
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| 223 | sll %g4, 1, %g5 ! rotate the "wim" left 1 |
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| 224 | srl %g4, SPARC_NUMBER_OF_REGISTER_WINDOWS - 1, %g4 |
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| 225 | or %g4, %g5, %g4 ! g4 = wim if we do one restore |
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| 226 | |
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| 227 | /* |
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| 228 | * If a restore would not underflow, then continue. |
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| 229 | */ |
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| 230 | |
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| 231 | andcc %g4, %g2, %g0 ! Any windows to flush? |
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| 232 | bnz done_flushing ! No, then continue |
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| 233 | nop |
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| 234 | |
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| 235 | restore ! back one window |
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| 236 | |
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| 237 | /* |
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| 238 | * Now save the window just as if we overflowed to it. |
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| 239 | */ |
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| 240 | |
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| 241 | std %l0, [%sp + CPU_STACK_FRAME_L0_OFFSET] |
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| 242 | std %l2, [%sp + CPU_STACK_FRAME_L2_OFFSET] |
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| 243 | std %l4, [%sp + CPU_STACK_FRAME_L4_OFFSET] |
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| 244 | std %l6, [%sp + CPU_STACK_FRAME_L6_OFFSET] |
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| 245 | |
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| 246 | std %i0, [%sp + CPU_STACK_FRAME_I0_OFFSET] |
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| 247 | std %i2, [%sp + CPU_STACK_FRAME_I2_OFFSET] |
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| 248 | std %i4, [%sp + CPU_STACK_FRAME_I4_OFFSET] |
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| 249 | std %i6, [%sp + CPU_STACK_FRAME_I6_FP_OFFSET] |
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| 250 | |
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| 251 | ba save_frame_loop |
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| 252 | nop |
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| 253 | |
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| 254 | done_flushing: |
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| 255 | |
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| 256 | add %g3, 1, %g3 ! calculate desired WIM |
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| 257 | and %g3, SPARC_NUMBER_OF_REGISTER_WINDOWS - 1, %g3 |
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| 258 | mov 1, %g4 |
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| 259 | sll %g4, %g3, %g4 ! g4 = new WIM |
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| 260 | mov %g4, %wim |
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| 261 | |
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| 262 | or %g1, SPARC_PSR_ET_MASK, %g1 |
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| 263 | mov %g1, %psr ! **** ENABLE TRAPS **** |
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| 264 | ! and restore CWP |
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| 265 | nop |
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| 266 | nop |
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| 267 | nop |
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| 268 | |
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| 269 | ! skip g0 |
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| 270 | ld [%o1 + G1_OFFSET], %g1 ! restore the global registers |
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| 271 | ldd [%o1 + G2_OFFSET], %g2 |
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| 272 | ldd [%o1 + G4_OFFSET], %g4 |
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| 273 | ldd [%o1 + G6_OFFSET], %g6 |
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| 274 | |
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| 275 | ldd [%o1 + L0_OFFSET], %l0 ! restore the local registers |
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| 276 | ldd [%o1 + L2_OFFSET], %l2 |
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| 277 | ldd [%o1 + L4_OFFSET], %l4 |
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| 278 | ldd [%o1 + L6_OFFSET], %l6 |
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| 279 | |
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| 280 | ldd [%o1 + I0_OFFSET], %i0 ! restore the output registers |
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| 281 | ldd [%o1 + I2_OFFSET], %i2 |
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| 282 | ldd [%o1 + I4_OFFSET], %i4 |
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| 283 | ldd [%o1 + I6_FP_OFFSET], %i6 |
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| 284 | |
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| 285 | ldd [%o1 + O2_OFFSET], %o2 ! restore the output registers |
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| 286 | ldd [%o1 + O4_OFFSET], %o4 |
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| 287 | ldd [%o1 + O6_SP_OFFSET], %o6 |
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| 288 | ! do o0/o1 last to avoid destroying heir context pointer |
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| 289 | ldd [%o1 + O0_OFFSET], %o0 ! overwrite heir pointer |
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| 290 | |
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| 291 | jmp %o7 + 8 ! return |
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| 292 | nop ! delay slot |
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[c62d36f] | 293 | |
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| 294 | /* |
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| 295 | * void _CPU_Context_restore( |
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| 296 | * Context_Control *new_context |
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| 297 | * ) |
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[9700578] | 298 | * |
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| 299 | * This routine is generally used only to perform restart self. |
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| 300 | * |
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| 301 | * NOTE: It is unnecessary to reload some registers. |
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[c62d36f] | 302 | */ |
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| 303 | |
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| 304 | .align 4 |
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| 305 | PUBLIC(_CPU_Context_restore) |
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| 306 | SYM(_CPU_Context_restore): |
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[9700578] | 307 | save %sp, -CPU_MINIMUM_STACK_FRAME_SIZE, %sp |
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| 308 | rd %psr, %o2 |
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| 309 | ba SYM(_CPU_Context_restore_heir) |
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| 310 | mov %i0, %o1 ! in the delay slot |
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[c62d36f] | 311 | |
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[9700578] | 312 | /* |
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| 313 | * void _ISR_Handler() |
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[c62d36f] | 314 | * |
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| 315 | * This routine provides the RTEMS interrupt management. |
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| 316 | * |
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[9700578] | 317 | * We enter this handler from the 4 instructions in the trap table with |
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| 318 | * the following registers assumed to be set as shown: |
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| 319 | * |
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| 320 | * l0 = PSR |
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| 321 | * l1 = PC |
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| 322 | * l2 = nPC |
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| 323 | * l3 = trap type |
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| 324 | * |
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| 325 | * NOTE: By an executive defined convention, trap type is between 0 and 255 if |
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| 326 | * it is an asynchonous trap and 256 and 511 if it is synchronous. |
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[c62d36f] | 327 | */ |
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| 328 | |
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| 329 | .align 4 |
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| 330 | PUBLIC(_ISR_Handler) |
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| 331 | SYM(_ISR_Handler): |
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[9700578] | 332 | /* |
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| 333 | * Fix the return address for synchronous traps. |
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| 334 | */ |
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| 335 | |
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| 336 | andcc %l3, SPARC_SYNCHRONOUS_TRAP_BIT_MASK, %g0 |
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| 337 | ! Is this a synchronous trap? |
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| 338 | be,a win_ovflow ! No, then skip the adjustment |
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| 339 | nop ! DELAY |
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| 340 | mov %l2, %l1 ! do not return to the instruction |
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| 341 | add %l2, 4, %l2 ! indicated |
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| 342 | |
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| 343 | win_ovflow: |
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| 344 | /* |
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| 345 | * Save the globals this block uses. |
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| 346 | * |
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| 347 | * These registers are not restored from the locals. Their contents |
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| 348 | * are saved directly from the locals into the ISF below. |
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| 349 | */ |
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| 350 | |
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| 351 | mov %g4, %l4 ! save the globals this block uses |
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| 352 | mov %g5, %l5 |
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| 353 | |
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| 354 | /* |
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| 355 | * When at a "window overflow" trap, (wim == (1 << cwp)). |
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| 356 | * If we get here like that, then process a window overflow. |
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| 357 | */ |
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| 358 | |
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| 359 | rd %wim, %g4 |
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| 360 | srl %g4, %l0, %g5 ! g5 = win >> cwp ; shift count and CWP |
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| 361 | ! are LS 5 bits ; how convenient :) |
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| 362 | cmp %g5, 1 ! Is this an invalid window? |
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| 363 | bne dont_do_the_window ! No, then skip all this stuff |
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| 364 | ! we are using the delay slot |
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| 365 | |
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| 366 | /* |
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| 367 | * The following is same as a 1 position right rotate of WIM |
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| 368 | */ |
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| 369 | |
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| 370 | srl %g4, 1, %g5 ! g5 = WIM >> 1 |
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| 371 | sll %g4, SPARC_NUMBER_OF_REGISTER_WINDOWS-1 , %g4 |
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| 372 | ! g4 = WIM << (Number Windows - 1) |
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| 373 | or %g4, %g5, %g4 ! g4 = (WIM >> 1) | |
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| 374 | ! (WIM << (Number Windows - 1)) |
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| 375 | |
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| 376 | /* |
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| 377 | * At this point: |
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| 378 | * |
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| 379 | * g4 = the new WIM |
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| 380 | * g5 is free |
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| 381 | */ |
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| 382 | |
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| 383 | /* |
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| 384 | * Since we are tinkering with the register windows, we need to |
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| 385 | * make sure that all the required information is in global registers. |
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| 386 | */ |
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| 387 | |
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| 388 | save ! Save into the window |
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| 389 | wr %g4, 0, %wim ! WIM = new WIM |
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| 390 | nop ! delay slots |
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| 391 | nop |
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| 392 | nop |
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| 393 | |
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| 394 | /* |
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| 395 | * Now save the window just as if we overflowed to it. |
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| 396 | */ |
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| 397 | |
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| 398 | std %l0, [%sp + CPU_STACK_FRAME_L0_OFFSET] |
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| 399 | std %l2, [%sp + CPU_STACK_FRAME_L2_OFFSET] |
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| 400 | std %l4, [%sp + CPU_STACK_FRAME_L4_OFFSET] |
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| 401 | std %l6, [%sp + CPU_STACK_FRAME_L6_OFFSET] |
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| 402 | |
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| 403 | std %i0, [%sp + CPU_STACK_FRAME_I0_OFFSET] |
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| 404 | std %i2, [%sp + CPU_STACK_FRAME_I2_OFFSET] |
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| 405 | std %i4, [%sp + CPU_STACK_FRAME_I4_OFFSET] |
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| 406 | std %i6, [%sp + CPU_STACK_FRAME_I6_FP_OFFSET] |
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| 407 | |
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| 408 | restore |
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| 409 | nop |
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| 410 | |
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| 411 | dont_do_the_window: |
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| 412 | /* |
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| 413 | * Global registers %g4 and %g5 are saved directly from %l4 and |
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| 414 | * %l5 directly into the ISF below. |
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| 415 | */ |
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| 416 | |
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| 417 | save_isf: |
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| 418 | |
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| 419 | /* |
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| 420 | * Save the state of the interrupted task -- especially the global |
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| 421 | * registers -- in the Interrupt Stack Frame. Note that the ISF |
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| 422 | * includes a regular minimum stack frame which will be used if |
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| 423 | * needed by register window overflow and underflow handlers. |
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| 424 | * |
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| 425 | * REGISTERS SAME AS AT _ISR_Handler |
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| 426 | */ |
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| 427 | |
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| 428 | sub %fp, CONTEXT_CONTROL_INTERRUPT_FRAME_SIZE, %sp |
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| 429 | ! make space for ISF |
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| 430 | |
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| 431 | std %l0, [%sp + ISF_PSR_OFFSET] ! save psr, PC |
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| 432 | st %l2, [%sp + ISF_NPC_OFFSET] ! save nPC |
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| 433 | st %g1, [%sp + ISF_G1_OFFSET] ! save g1 |
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| 434 | std %g2, [%sp + ISF_G2_OFFSET] ! save g2, g3 |
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| 435 | std %l4, [%sp + ISF_G4_OFFSET] ! save g4, g5 -- see above |
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| 436 | std %g6, [%sp + ISF_G6_OFFSET] ! save g6, g7 |
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| 437 | |
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| 438 | std %i0, [%sp + ISF_I0_OFFSET] ! save i0, i1 |
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| 439 | std %i2, [%sp + ISF_I2_OFFSET] ! save i2, i3 |
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| 440 | std %i4, [%sp + ISF_I4_OFFSET] ! save i4, i5 |
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| 441 | std %i6, [%sp + ISF_I6_FP_OFFSET] ! save i6/fp, i7 |
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| 442 | |
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| 443 | rd %y, %g1 |
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| 444 | st %g1, [%sp + ISF_Y_OFFSET] ! save y |
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| 445 | |
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| 446 | mov %sp, %o1 ! 2nd arg to ISR Handler |
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| 447 | |
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| 448 | /* |
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| 449 | * Increment ISR nest level and Thread dispatch disable level. |
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| 450 | * |
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| 451 | * Register usage for this section: |
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| 452 | * |
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| 453 | * l4 = _Thread_Dispatch_disable_level pointer |
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| 454 | * l5 = _ISR_Nest_level pointer |
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| 455 | * l6 = _Thread_Dispatch_disable_level value |
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| 456 | * l7 = _ISR_Nest_level value |
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| 457 | * |
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| 458 | * NOTE: It is assumed that l4 - l7 will be preserved until the ISR |
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| 459 | * nest and thread dispatch disable levels are unnested. |
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| 460 | */ |
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| 461 | |
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| 462 | sethi %hi(SYM(_Thread_Dispatch_disable_level)), %l4 |
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| 463 | ld [%l4 + %lo(SYM(_Thread_Dispatch_disable_level))], %l6 |
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| 464 | sethi %hi(SYM(_ISR_Nest_level)), %l5 |
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| 465 | ld [%l5 + %lo(SYM(_ISR_Nest_level))], %l7 |
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| 466 | |
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| 467 | add %l6, 1, %l6 |
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| 468 | st %l6, [%l4 + %lo(SYM(_Thread_Dispatch_disable_level))] |
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| 469 | |
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| 470 | add %l7, 1, %l7 |
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| 471 | st %l7, [%l5 + %lo(SYM(_ISR_Nest_level))] |
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| 472 | |
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| 473 | /* |
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| 474 | * If ISR nest level was zero (now 1), then switch stack. |
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| 475 | */ |
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| 476 | |
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| 477 | mov %sp, %fp |
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| 478 | subcc %l7, 1, %l7 ! outermost interrupt handler? |
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| 479 | bnz dont_switch_stacks ! No, then do not switch stacks |
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| 480 | |
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| 481 | sethi %hi(SYM(_CPU_Interrupt_stack_high)), %g4 |
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| 482 | ld [%g4 + %lo(SYM(_CPU_Interrupt_stack_high))], %sp |
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| 483 | |
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| 484 | dont_switch_stacks: |
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| 485 | /* |
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| 486 | * Make sure we have a place on the stack for the window overflow |
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| 487 | * trap handler to write into. At this point it is safe to |
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| 488 | * enable traps again. |
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| 489 | */ |
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| 490 | |
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| 491 | sub %sp, CPU_MINIMUM_STACK_FRAME_SIZE, %sp |
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| 492 | |
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| 493 | wr %l0, SPARC_PSR_ET_MASK, %psr ! **** ENABLE TRAPS **** |
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| 494 | |
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| 495 | /* |
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| 496 | * Vector to user's handler. |
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| 497 | * |
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| 498 | * NOTE: TBR may no longer have vector number in it since |
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| 499 | * we just enabled traps. It is definitely in l3. |
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| 500 | */ |
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| 501 | |
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| 502 | sethi %hi(SYM(_ISR_Vector_table)), %g4 |
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| 503 | or %g4, %lo(SYM(_ISR_Vector_table)), %g4 |
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| 504 | and %l3, 0xFF, %g5 ! remove synchronous trap indicator |
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| 505 | sll %g5, 2, %g5 ! g5 = offset into table |
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| 506 | ld [%g4 + %g5], %g4 ! g4 = _ISR_Vector_table[ vector ] |
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| 507 | |
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| 508 | |
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| 509 | ! o1 = 2nd arg = address of the ISF |
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| 510 | ! WAS LOADED WHEN ISF WAS SAVED!!! |
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| 511 | mov %l3, %o0 ! o0 = 1st arg = vector number |
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| 512 | call %g4, 0 |
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| 513 | nop ! delay slot |
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| 514 | |
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| 515 | /* |
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| 516 | * Redisable traps so we can finish up the interrupt processing. |
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| 517 | * This is a VERY conservative place to do this. |
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| 518 | * |
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| 519 | * NOTE: %l0 has the PSR which was in place when we took the trap. |
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| 520 | */ |
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| 521 | |
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| 522 | mov %l0, %psr ! **** DISABLE TRAPS **** |
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| 523 | |
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| 524 | /* |
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| 525 | * Decrement ISR nest level and Thread dispatch disable level. |
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| 526 | * |
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| 527 | * Register usage for this section: |
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| 528 | * |
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| 529 | * l4 = _Thread_Dispatch_disable_level pointer |
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| 530 | * l5 = _ISR_Nest_level pointer |
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| 531 | * l6 = _Thread_Dispatch_disable_level value |
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| 532 | * l7 = _ISR_Nest_level value |
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| 533 | */ |
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| 534 | |
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| 535 | sub %l6, 1, %l6 |
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| 536 | st %l6, [%l4 + %lo(SYM(_Thread_Dispatch_disable_level))] |
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| 537 | |
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| 538 | st %l7, [%l5 + %lo(SYM(_ISR_Nest_level))] |
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| 539 | |
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| 540 | /* |
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| 541 | * If dispatching is disabled (includes nested interrupt case), |
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| 542 | * then do a "simple" exit. |
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| 543 | */ |
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| 544 | |
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| 545 | orcc %l6, %g0, %g0 ! Is dispatching disabled? |
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| 546 | bnz simple_return ! Yes, then do a "simple" exit |
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| 547 | nop ! delay slot |
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| 548 | |
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| 549 | /* |
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| 550 | * If a context switch is necessary, then do fudge stack to |
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| 551 | * return to the interrupt dispatcher. |
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| 552 | */ |
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| 553 | |
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| 554 | sethi %hi(SYM(_Context_Switch_necessary)), %l4 |
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| 555 | ld [%l4 + %lo(SYM(_Context_Switch_necessary))], %l5 |
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| 556 | |
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| 557 | orcc %l5, %g0, %g0 ! Is thread switch necessary? |
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| 558 | bnz SYM(_ISR_Dispatch) ! yes, then invoke the dispatcher |
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| 559 | nop ! delay slot |
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| 560 | |
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| 561 | /* |
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| 562 | * Finally, check to see if signals were sent to the currently |
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| 563 | * executing task. If so, we need to invoke the interrupt dispatcher. |
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| 564 | */ |
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| 565 | |
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| 566 | sethi %hi(SYM(_ISR_Signals_to_thread_executing)), %l6 |
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| 567 | ld [%l6 + %lo(SYM(_ISR_Signals_to_thread_executing))], %l7 |
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| 568 | |
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| 569 | orcc %l7, %g0, %g0 ! Were signals sent to the currently |
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| 570 | ! executing thread? |
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| 571 | bz simple_return ! yes, then invoke the dispatcher |
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[6ca1184] | 572 | ! use the delay slot to clear the signals |
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| 573 | ! to the currently executing task flag |
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| 574 | st %g0, [%l6 + %lo(SYM(_ISR_Signals_to_thread_executing))] |
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| 575 | |
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[9700578] | 576 | |
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| 577 | /* |
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| 578 | * Invoke interrupt dispatcher. |
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| 579 | */ |
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| 580 | |
---|
| 581 | PUBLIC(_ISR_Dispatch) |
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| 582 | SYM(_ISR_Dispatch): |
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| 583 | |
---|
| 584 | /* |
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| 585 | * The following subtract should get us back on the interrupted |
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| 586 | * tasks stack and add enough room to invoke the dispatcher. |
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| 587 | * When we enable traps, we are mostly back in the context |
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| 588 | * of the task and subsequent interrupts can operate normally. |
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| 589 | */ |
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| 590 | |
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| 591 | sub %fp, CPU_MINIMUM_STACK_FRAME_SIZE, %sp |
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| 592 | |
---|
| 593 | or %l0, SPARC_PSR_ET_MASK, %l7 ! l7 = PSR with ET=1 |
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| 594 | mov %l7, %psr ! **** ENABLE TRAPS **** |
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| 595 | nop |
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| 596 | nop |
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| 597 | nop |
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| 598 | |
---|
| 599 | call SYM(_Thread_Dispatch), 0 |
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| 600 | nop |
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| 601 | |
---|
| 602 | /* |
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| 603 | * The CWP in place at this point may be different from |
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| 604 | * that which was in effect at the beginning of the ISR if we |
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| 605 | * have been context switched between the beginning of this invocation |
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| 606 | * of _ISR_Handler and this point. Thus the CWP and WIM should |
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| 607 | * not be changed back to their values at ISR entry time. Any |
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| 608 | * changes to the PSR must preserve the CWP. |
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| 609 | */ |
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| 610 | |
---|
| 611 | simple_return: |
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| 612 | ld [%fp + ISF_Y_OFFSET], %l5 ! restore y |
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| 613 | wr %l5, 0, %y |
---|
| 614 | |
---|
| 615 | ldd [%fp + ISF_PSR_OFFSET], %l0 ! restore psr, PC |
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| 616 | ld [%fp + ISF_NPC_OFFSET], %l2 ! restore nPC |
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| 617 | rd %psr, %l3 |
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| 618 | and %l3, SPARC_PSR_CWP_MASK, %l3 ! want "current" CWP |
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| 619 | andn %l0, SPARC_PSR_CWP_MASK, %l0 ! want rest from task |
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| 620 | or %l3, %l0, %l0 ! install it later... |
---|
| 621 | andn %l0, SPARC_PSR_ET_MASK, %l0 |
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| 622 | |
---|
| 623 | /* |
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| 624 | * Restore tasks global and out registers |
---|
| 625 | */ |
---|
| 626 | |
---|
| 627 | mov %fp, %g1 |
---|
| 628 | |
---|
| 629 | ! g1 is restored later |
---|
| 630 | ldd [%fp + ISF_G2_OFFSET], %g2 ! restore g2, g3 |
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| 631 | ldd [%fp + ISF_G4_OFFSET], %g4 ! restore g4, g5 |
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| 632 | ldd [%fp + ISF_G6_OFFSET], %g6 ! restore g6, g7 |
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| 633 | |
---|
| 634 | ldd [%fp + ISF_I0_OFFSET], %i0 ! restore i0, i1 |
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| 635 | ldd [%fp + ISF_I2_OFFSET], %i2 ! restore i2, i3 |
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| 636 | ldd [%fp + ISF_I4_OFFSET], %i4 ! restore i4, i5 |
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| 637 | ldd [%fp + ISF_I6_FP_OFFSET], %i6 ! restore i6/fp, i7 |
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| 638 | |
---|
| 639 | /* |
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| 640 | * Registers: |
---|
| 641 | * |
---|
| 642 | * ALL global registers EXCEPT G1 and the input registers have |
---|
| 643 | * already been restored and thuse off limits. |
---|
| 644 | * |
---|
| 645 | * The following is the contents of the local registers: |
---|
| 646 | * |
---|
| 647 | * l0 = original psr |
---|
| 648 | * l1 = return address (i.e. PC) |
---|
| 649 | * l2 = nPC |
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| 650 | * l3 = CWP |
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| 651 | */ |
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| 652 | |
---|
| 653 | /* |
---|
| 654 | * if (CWP + 1) is an invalid window then we need to reload it. |
---|
| 655 | * |
---|
| 656 | * WARNING: Traps should now be disabled |
---|
| 657 | */ |
---|
| 658 | |
---|
| 659 | mov %l0, %psr ! **** DISABLE TRAPS **** |
---|
| 660 | nop |
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| 661 | nop |
---|
| 662 | nop |
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| 663 | rd %wim, %l4 |
---|
| 664 | add %l0, 1, %l6 ! l6 = cwp + 1 |
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| 665 | and %l6, SPARC_PSR_CWP_MASK, %l6 ! do the modulo on it |
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| 666 | srl %l4, %l6, %l5 ! l5 = win >> cwp + 1 ; shift count |
---|
| 667 | ! and CWP are conveniently LS 5 bits |
---|
| 668 | cmp %l5, 1 ! Is tasks window invalid? |
---|
| 669 | bne good_task_window |
---|
| 670 | |
---|
| 671 | /* |
---|
| 672 | * The following code is the same as a 1 position left rotate of WIM. |
---|
| 673 | */ |
---|
| 674 | |
---|
| 675 | sll %l4, 1, %l5 ! l5 = WIM << 1 |
---|
| 676 | srl %l4, SPARC_NUMBER_OF_REGISTER_WINDOWS-1 , %l4 |
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| 677 | ! l4 = WIM >> (Number Windows - 1) |
---|
| 678 | or %l4, %l5, %l4 ! l4 = (WIM << 1) | |
---|
| 679 | ! (WIM >> (Number Windows - 1)) |
---|
| 680 | |
---|
| 681 | /* |
---|
| 682 | * Now restore the window just as if we underflowed to it. |
---|
| 683 | */ |
---|
| 684 | |
---|
| 685 | wr %l4, 0, %wim ! WIM = new WIM |
---|
| 686 | restore ! now into the tasks window |
---|
| 687 | |
---|
| 688 | ldd [%g1 + CPU_STACK_FRAME_L0_OFFSET], %l0 |
---|
| 689 | ldd [%g1 + CPU_STACK_FRAME_L2_OFFSET], %l2 |
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| 690 | ldd [%g1 + CPU_STACK_FRAME_L4_OFFSET], %l4 |
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| 691 | ldd [%g1 + CPU_STACK_FRAME_L6_OFFSET], %l6 |
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| 692 | ldd [%g1 + CPU_STACK_FRAME_I0_OFFSET], %i0 |
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| 693 | ldd [%g1 + CPU_STACK_FRAME_I2_OFFSET], %i2 |
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| 694 | ldd [%g1 + CPU_STACK_FRAME_I4_OFFSET], %i4 |
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| 695 | ldd [%g1 + CPU_STACK_FRAME_I6_FP_OFFSET], %i6 |
---|
| 696 | ! reload of sp clobbers ISF |
---|
| 697 | save ! Back to ISR dispatch window |
---|
| 698 | |
---|
| 699 | good_task_window: |
---|
| 700 | |
---|
| 701 | mov %l0, %psr ! **** DISABLE TRAPS **** |
---|
| 702 | ! and restore condition codes. |
---|
| 703 | ld [%g1 + ISF_G1_OFFSET], %g1 ! restore g1 |
---|
| 704 | jmp %l1 ! transfer control and |
---|
| 705 | rett %l2 ! go back to tasks window |
---|
[c62d36f] | 706 | |
---|
[9700578] | 707 | /* end of file */ |
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