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cpu_asm.S @ 20f54e9

4.104.114.84.95

Last change on this file since 20f54e9 was b73e57b, checked in by Joel Sherrill <joel.sherrill@…>, on 07/09/99 at 17:08:48

Patch from Jiri Gaisler <jgais@…>:

+ interrupt masking correction
+ FPU rev.B workaround
+ minor erc32 related fixes

Property mode set to 100644

File size: 26.8 KB

Line
1	/* cpu_asm.s
2	*
3	* This file contains the basic algorithms for all assembly code used
4	* in an specific CPU port of RTEMS. These algorithms must be implemented
5	* in assembly language.
6	*
7	* COPYRIGHT (c) 1989-1998.
8	* On-Line Applications Research Corporation (OAR).
9	* Copyright assigned to U.S. Government, 1994.
10	*
11	* The license and distribution terms for this file may be
12	* found in the file LICENSE in this distribution or at
13	* http://www.OARcorp.com/rtems/license.html.
14	*
15	* Ported to ERC32 implementation of the SPARC by On-Line Applications
16	* Research Corporation (OAR) under contract to the European Space
17	* Agency (ESA).
18	*
19	* ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995.
20	* European Space Agency.
21	*
22	* $Id$
23	*/
24
25	#include <asm.h>
26
27	#if (SPARC_HAS_FPU == 1)
28
29	/*
30	* void _CPU_Context_save_fp(
31	* void **fp_context_ptr
32	* )
33	*
34	* This routine is responsible for saving the FP context
35	* at *fp_context_ptr. If the point to load the FP context
36	* from is changed then the pointer is modified by this routine.
37	*
38	* NOTE: See the README in this directory for information on the
39	* management of the "EF" bit in the PSR.
40	*/
41
42	.align 4
43	PUBLIC(_CPU_Context_save_fp)
44	SYM(_CPU_Context_save_fp):
45	save %sp, -CPU_MINIMUM_STACK_FRAME_SIZE, %sp
46
47	/*
48	* The following enables the floating point unit.
49	*/
50
51	mov %psr, %l0
52	sethi %hi(SPARC_PSR_EF_MASK), %l1
53	or %l1, %lo(SPARC_PSR_EF_MASK), %l1
54	or %l0, %l1, %l0
55	mov %l0, %psr ! ** ENABLE FLOAT ACCESS **
56
57	ld [%i0], %l0
58	std %f0, [%l0 + FO_F1_OFFSET]
59	std %f2, [%l0 + F2_F3_OFFSET]
60	std %f4, [%l0 + F4_F5_OFFSET]
61	std %f6, [%l0 + F6_F7_OFFSET]
62	std %f8, [%l0 + F8_F9_OFFSET]
63	std %f10, [%l0 + F1O_F11_OFFSET]
64	std %f12, [%l0 + F12_F13_OFFSET]
65	std %f14, [%l0 + F14_F15_OFFSET]
66	std %f16, [%l0 + F16_F17_OFFSET]
67	std %f18, [%l0 + F18_F19_OFFSET]
68	std %f20, [%l0 + F2O_F21_OFFSET]
69	std %f22, [%l0 + F22_F23_OFFSET]
70	std %f24, [%l0 + F24_F25_OFFSET]
71	std %f26, [%l0 + F26_F27_OFFSET]
72	std %f28, [%l0 + F28_F29_OFFSET]
73	std %f30, [%l0 + F3O_F31_OFFSET]
74	st %fsr, [%l0 + FSR_OFFSET]
75	ret
76	restore
77
78	/*
79	* void _CPU_Context_restore_fp(
80	* void **fp_context_ptr
81	* )
82	*
83	* This routine is responsible for restoring the FP context
84	* at *fp_context_ptr. If the point to load the FP context
85	* from is changed then the pointer is modified by this routine.
86	*
87	* NOTE: See the README in this directory for information on the
88	* management of the "EF" bit in the PSR.
89	*/
90
91	.align 4
92	PUBLIC(_CPU_Context_restore_fp)
93	SYM(_CPU_Context_restore_fp):
94	save %sp, -CPU_MINIMUM_STACK_FRAME_SIZE , %sp
95
96	/*
97	* The following enables the floating point unit.
98	*/
99
100	mov %psr, %l0
101	sethi %hi(SPARC_PSR_EF_MASK), %l1
102	or %l1, %lo(SPARC_PSR_EF_MASK), %l1
103	or %l0, %l1, %l0
104	mov %l0, %psr ! ** ENABLE FLOAT ACCESS **
105
106	ld [%i0], %l0
107	ldd [%l0 + FO_F1_OFFSET], %f0
108	ldd [%l0 + F2_F3_OFFSET], %f2
109	ldd [%l0 + F4_F5_OFFSET], %f4
110	ldd [%l0 + F6_F7_OFFSET], %f6
111	ldd [%l0 + F8_F9_OFFSET], %f8
112	ldd [%l0 + F1O_F11_OFFSET], %f10
113	ldd [%l0 + F12_F13_OFFSET], %f12
114	ldd [%l0 + F14_F15_OFFSET], %f14
115	ldd [%l0 + F16_F17_OFFSET], %f16
116	ldd [%l0 + F18_F19_OFFSET], %f18
117	ldd [%l0 + F2O_F21_OFFSET], %f20
118	ldd [%l0 + F22_F23_OFFSET], %f22
119	ldd [%l0 + F24_F25_OFFSET], %f24
120	ldd [%l0 + F26_F27_OFFSET], %f26
121	ldd [%l0 + F28_F29_OFFSET], %f28
122	ldd [%l0 + F3O_F31_OFFSET], %f30
123	ld [%l0 + FSR_OFFSET], %fsr
124	ret
125	restore
126
127	#endif /* SPARC_HAS_FPU */
128
129	/*
130	* void _CPU_Context_switch(
131	* Context_Control *run,
132	* Context_Control *heir
133	* )
134	*
135	* This routine performs a normal non-FP context switch.
136	*/
137
138	.align 4
139	PUBLIC(_CPU_Context_switch)
140	SYM(_CPU_Context_switch):
141	! skip g0
142	st %g1, [%o0 + G1_OFFSET] ! save the global registers
143	std %g2, [%o0 + G2_OFFSET]
144	std %g4, [%o0 + G4_OFFSET]
145	std %g6, [%o0 + G6_OFFSET]
146
147	std %l0, [%o0 + L0_OFFSET] ! save the local registers
148	std %l2, [%o0 + L2_OFFSET]
149	std %l4, [%o0 + L4_OFFSET]
150	std %l6, [%o0 + L6_OFFSET]
151
152	std %i0, [%o0 + I0_OFFSET] ! save the input registers
153	std %i2, [%o0 + I2_OFFSET]
154	std %i4, [%o0 + I4_OFFSET]
155	std %i6, [%o0 + I6_FP_OFFSET]
156
157	std %o0, [%o0 + O0_OFFSET] ! save the output registers
158	std %o2, [%o0 + O2_OFFSET]
159	std %o4, [%o0 + O4_OFFSET]
160	std %o6, [%o0 + O6_SP_OFFSET]
161
162	rd %psr, %o2
163	st %o2, [%o0 + PSR_OFFSET] ! save status register
164
165	/*
166	* This is entered from _CPU_Context_restore with:
167	* o1 = context to restore
168	* o2 = psr
169	*/
170
171	PUBLIC(_CPU_Context_restore_heir)
172	SYM(_CPU_Context_restore_heir):
173	/*
174	* Flush all windows with valid contents except the current one.
175	* In examining the set register windows, one may logically divide
176	* the windows into sets (some of which may be empty) based on their
177	* current status:
178	*
179	* + current (i.e. in use),
180	* + used (i.e. a restore would not trap)
181	* + invalid (i.e. 1 in corresponding bit in WIM)
182	* + unused
183	*
184	* Either the used or unused set of windows may be empty.
185	*
186	* NOTE: We assume only one bit is set in the WIM at a time.
187	*
188	* Given a CWP of 5 and a WIM of 0x1, the registers are divided
189	* into sets as follows:
190	*
191	* + 0 - invalid
192	* + 1-4 - unused
193	* + 5 - current
194	* + 6-7 - used
195	*
196	* In this case, we only would save the used windows -- 6 and 7.
197	*
198	* Traps are disabled for the same logical period as in a
199	* flush all windows trap handler.
200	*
201	* Register Usage while saving the windows:
202	* g1 = current PSR
203	* g2 = current wim
204	* g3 = CWP
205	* g4 = wim scratch
206	* g5 = scratch
207	*/
208
209	ld [%o1 + PSR_OFFSET], %g1 ! g1 = saved psr
210
211	and %o2, SPARC_PSR_CWP_MASK, %g3 ! g3 = CWP
212	! g1 = psr w/o cwp
213	andn %g1, SPARC_PSR_ET_MASK \| SPARC_PSR_CWP_MASK, %g1
214	or %g1, %g3, %g1 ! g1 = heirs psr
215	mov %g1, %psr ! restore status register and
216	! ** DISABLE TRAPS **
217	mov %wim, %g2 ! g2 = wim
218	mov 1, %g4
219	sll %g4, %g3, %g4 ! g4 = WIM mask for CW invalid
220
221	save_frame_loop:
222	sll %g4, 1, %g5 ! rotate the "wim" left 1
223	srl %g4, SPARC_NUMBER_OF_REGISTER_WINDOWS - 1, %g4
224	or %g4, %g5, %g4 ! g4 = wim if we do one restore
225
226	/*
227	* If a restore would not underflow, then continue.
228	*/
229
230	andcc %g4, %g2, %g0 ! Any windows to flush?
231	bnz done_flushing ! No, then continue
232	nop
233
234	restore ! back one window
235
236	/*
237	* Now save the window just as if we overflowed to it.
238	*/
239
240	std %l0, [%sp + CPU_STACK_FRAME_L0_OFFSET]
241	std %l2, [%sp + CPU_STACK_FRAME_L2_OFFSET]
242	std %l4, [%sp + CPU_STACK_FRAME_L4_OFFSET]
243	std %l6, [%sp + CPU_STACK_FRAME_L6_OFFSET]
244
245	std %i0, [%sp + CPU_STACK_FRAME_I0_OFFSET]
246	std %i2, [%sp + CPU_STACK_FRAME_I2_OFFSET]
247	std %i4, [%sp + CPU_STACK_FRAME_I4_OFFSET]
248	std %i6, [%sp + CPU_STACK_FRAME_I6_FP_OFFSET]
249
250	ba save_frame_loop
251	nop
252
253	done_flushing:
254
255	add %g3, 1, %g3 ! calculate desired WIM
256	and %g3, SPARC_NUMBER_OF_REGISTER_WINDOWS - 1, %g3
257	mov 1, %g4
258	sll %g4, %g3, %g4 ! g4 = new WIM
259	mov %g4, %wim
260
261	or %g1, SPARC_PSR_ET_MASK, %g1
262	mov %g1, %psr ! ** ENABLE TRAPS **
263	! and restore CWP
264	nop
265	nop
266	nop
267
268	! skip g0
269	ld [%o1 + G1_OFFSET], %g1 ! restore the global registers
270	ldd [%o1 + G2_OFFSET], %g2
271	ldd [%o1 + G4_OFFSET], %g4
272	ldd [%o1 + G6_OFFSET], %g6
273
274	ldd [%o1 + L0_OFFSET], %l0 ! restore the local registers
275	ldd [%o1 + L2_OFFSET], %l2
276	ldd [%o1 + L4_OFFSET], %l4
277	ldd [%o1 + L6_OFFSET], %l6
278
279	ldd [%o1 + I0_OFFSET], %i0 ! restore the output registers
280	ldd [%o1 + I2_OFFSET], %i2
281	ldd [%o1 + I4_OFFSET], %i4
282	ldd [%o1 + I6_FP_OFFSET], %i6
283
284	ldd [%o1 + O2_OFFSET], %o2 ! restore the output registers
285	ldd [%o1 + O4_OFFSET], %o4
286	ldd [%o1 + O6_SP_OFFSET], %o6
287	! do o0/o1 last to avoid destroying heir context pointer
288	ldd [%o1 + O0_OFFSET], %o0 ! overwrite heir pointer
289
290	jmp %o7 + 8 ! return
291	nop ! delay slot
292
293	/*
294	* void _CPU_Context_restore(
295	* Context_Control *new_context
296	* )
297	*
298	* This routine is generally used only to perform restart self.
299	*
300	* NOTE: It is unnecessary to reload some registers.
301	*/
302
303	.align 4
304	PUBLIC(_CPU_Context_restore)
305	SYM(_CPU_Context_restore):
306	save %sp, -CPU_MINIMUM_STACK_FRAME_SIZE, %sp
307	rd %psr, %o2
308	ba SYM(_CPU_Context_restore_heir)
309	mov %i0, %o1 ! in the delay slot
310
311	/*
312	* void _ISR_Handler()
313	*
314	* This routine provides the RTEMS interrupt management.
315	*
316	* We enter this handler from the 4 instructions in the trap table with
317	* the following registers assumed to be set as shown:
318	*
319	* l0 = PSR
320	* l1 = PC
321	* l2 = nPC
322	* l3 = trap type
323	*
324	* NOTE: By an executive defined convention, trap type is between 0 and 255 if
325	* it is an asynchonous trap and 256 and 511 if it is synchronous.
326	*/
327
328	.align 4
329	PUBLIC(_ISR_Handler)
330	SYM(_ISR_Handler):
331	/*
332	* Fix the return address for synchronous traps.
333	*/
334
335	andcc %l3, SPARC_SYNCHRONOUS_TRAP_BIT_MASK, %g0
336	! Is this a synchronous trap?
337	be,a win_ovflow ! No, then skip the adjustment
338	nop ! DELAY
339	mov %l1, %l6 ! save trapped pc for debug info
340	mov %l2, %l1 ! do not return to the instruction
341	add %l2, 4, %l2 ! indicated
342
343	win_ovflow:
344	/*
345	* Save the globals this block uses.
346	*
347	* These registers are not restored from the locals. Their contents
348	* are saved directly from the locals into the ISF below.
349	*/
350
351	mov %g4, %l4 ! save the globals this block uses
352	mov %g5, %l5
353
354	/*
355	* When at a "window overflow" trap, (wim == (1 << cwp)).
356	* If we get here like that, then process a window overflow.
357	*/
358
359	rd %wim, %g4
360	srl %g4, %l0, %g5 ! g5 = win >> cwp ; shift count and CWP
361	! are LS 5 bits ; how convenient :)
362	cmp %g5, 1 ! Is this an invalid window?
363	bne dont_do_the_window ! No, then skip all this stuff
364	! we are using the delay slot
365
366	/*
367	* The following is same as a 1 position right rotate of WIM
368	*/
369
370	srl %g4, 1, %g5 ! g5 = WIM >> 1
371	sll %g4, SPARC_NUMBER_OF_REGISTER_WINDOWS-1 , %g4
372	! g4 = WIM << (Number Windows - 1)
373	or %g4, %g5, %g4 ! g4 = (WIM >> 1) \|
374	! (WIM << (Number Windows - 1))
375
376	/*
377	* At this point:
378	*
379	* g4 = the new WIM
380	* g5 is free
381	*/
382
383	/*
384	* Since we are tinkering with the register windows, we need to
385	* make sure that all the required information is in global registers.
386	*/
387
388	save ! Save into the window
389	wr %g4, 0, %wim ! WIM = new WIM
390	nop ! delay slots
391	nop
392	nop
393
394	/*
395	* Now save the window just as if we overflowed to it.
396	*/
397
398	std %l0, [%sp + CPU_STACK_FRAME_L0_OFFSET]
399	std %l2, [%sp + CPU_STACK_FRAME_L2_OFFSET]
400	std %l4, [%sp + CPU_STACK_FRAME_L4_OFFSET]
401	std %l6, [%sp + CPU_STACK_FRAME_L6_OFFSET]
402
403	std %i0, [%sp + CPU_STACK_FRAME_I0_OFFSET]
404	std %i2, [%sp + CPU_STACK_FRAME_I2_OFFSET]
405	std %i4, [%sp + CPU_STACK_FRAME_I4_OFFSET]
406	std %i6, [%sp + CPU_STACK_FRAME_I6_FP_OFFSET]
407
408	restore
409	nop
410
411	dont_do_the_window:
412	/*
413	* Global registers %g4 and %g5 are saved directly from %l4 and
414	* %l5 directly into the ISF below.
415	*/
416
417	save_isf:
418
419	/*
420	* Save the state of the interrupted task -- especially the global
421	* registers -- in the Interrupt Stack Frame. Note that the ISF
422	* includes a regular minimum stack frame which will be used if
423	* needed by register window overflow and underflow handlers.
424	*
425	* REGISTERS SAME AS AT _ISR_Handler
426	*/
427
428	sub %fp, CONTEXT_CONTROL_INTERRUPT_FRAME_SIZE, %sp
429	! make space for ISF
430
431	std %l0, [%sp + ISF_PSR_OFFSET] ! save psr, PC
432	st %l2, [%sp + ISF_NPC_OFFSET] ! save nPC
433	st %g1, [%sp + ISF_G1_OFFSET] ! save g1
434	std %g2, [%sp + ISF_G2_OFFSET] ! save g2, g3
435	std %l4, [%sp + ISF_G4_OFFSET] ! save g4, g5 -- see above
436	std %g6, [%sp + ISF_G6_OFFSET] ! save g6, g7
437
438	std %i0, [%sp + ISF_I0_OFFSET] ! save i0, i1
439	std %i2, [%sp + ISF_I2_OFFSET] ! save i2, i3
440	std %i4, [%sp + ISF_I4_OFFSET] ! save i4, i5
441	std %i6, [%sp + ISF_I6_FP_OFFSET] ! save i6/fp, i7
442
443	rd %y, %g1
444	st %g1, [%sp + ISF_Y_OFFSET] ! save y
445	st %l6, [%sp + ISF_TPC_OFFSET] ! save real trapped pc
446
447	mov %sp, %o1 ! 2nd arg to ISR Handler
448
449	/*
450	* Increment ISR nest level and Thread dispatch disable level.
451	*
452	* Register usage for this section:
453	*
454	* l4 = _Thread_Dispatch_disable_level pointer
455	* l5 = _ISR_Nest_level pointer
456	* l6 = _Thread_Dispatch_disable_level value
457	* l7 = _ISR_Nest_level value
458	*
459	* NOTE: It is assumed that l4 - l7 will be preserved until the ISR
460	* nest and thread dispatch disable levels are unnested.
461	*/
462
463	sethi %hi(SYM(_Thread_Dispatch_disable_level)), %l4
464	ld [%l4 + %lo(SYM(_Thread_Dispatch_disable_level))], %l6
465	sethi %hi(SYM(_ISR_Nest_level)), %l5
466	ld [%l5 + %lo(SYM(_ISR_Nest_level))], %l7
467
468	add %l6, 1, %l6
469	st %l6, [%l4 + %lo(SYM(_Thread_Dispatch_disable_level))]
470
471	add %l7, 1, %l7
472	st %l7, [%l5 + %lo(SYM(_ISR_Nest_level))]
473
474	/*
475	* If ISR nest level was zero (now 1), then switch stack.
476	*/
477
478	mov %sp, %fp
479	subcc %l7, 1, %l7 ! outermost interrupt handler?
480	bnz dont_switch_stacks ! No, then do not switch stacks
481
482	sethi %hi(SYM(_CPU_Interrupt_stack_high)), %g4
483	ld [%g4 + %lo(SYM(_CPU_Interrupt_stack_high))], %sp
484
485	dont_switch_stacks:
486	/*
487	* Make sure we have a place on the stack for the window overflow
488	* trap handler to write into. At this point it is safe to
489	* enable traps again.
490	*/
491
492	sub %sp, CPU_MINIMUM_STACK_FRAME_SIZE, %sp
493
494	/*
495	* Check if we have an external interrupt (trap 0x11 - 0x1f). If so,
496	* set the PIL in the %psr to mask off interrupts with lower priority.
497	* The original %psr in %l0 is not modified since it will be restored
498	* when the interrupt handler returns.
499	*/
500
501	/* This is a fix for ERC32 with FPU rev.B or rev.C */
502
503	#if defined(FPU_REVB)
504
505
506	mov %l0, %g5
507	and %l3, 0x0ff, %g4
508	subcc %g4, 0x08, %g0
509	be fpu_revb
510	subcc %g4, 0x11, %g0
511	bl dont_fix_pil
512	subcc %g4, 0x1f, %g0
513	bg dont_fix_pil
514	sll %g4, 8, %g4
515	and %g4, SPARC_PSR_PIL_MASK, %g4
516	andn %l0, SPARC_PSR_PIL_MASK, %g5
517	or %g4, %g5, %g5
518	srl %l0, 12, %g4
519	andcc %g4, 1, %g0
520	be dont_fix_pil
521	nop
522	ba,a enable_irq
523
524
525	fpu_revb:
526	srl %l0, 12, %g4 ! check if EF is set in %psr
527	andcc %g4, 1, %g0
528	be dont_fix_pil ! if FPU disabled than continue as normal
529	and %l3, 0xff, %g4
530	subcc %g4, 0x08, %g0
531	bne enable_irq ! if not a FPU exception then do two fmovs
532	set __sparc_fq, %g4
533	st %fsr, [%g4] ! if FQ is not empty and FQ[1] = fmovs
534	ld [%g4], %g4 ! than this is bug 3.14
535	srl %g4, 13, %g4
536	andcc %g4, 1, %g0
537	be dont_fix_pil
538	set __sparc_fq, %g4
539	std %fq, [%g4]
540	ld [%g4+4], %g4
541	set 0x81a00020, %g5
542	subcc %g4, %g5, %g0
543	bne,a dont_fix_pil2
544	wr %l0, SPARC_PSR_ET_MASK, %psr ! ** ENABLE TRAPS **
545	ba,a simple_return
546
547	enable_irq:
548	or %g5, SPARC_PSR_PIL_MASK, %g4
549	wr %g4, SPARC_PSR_ET_MASK, %psr ! ** ENABLE TRAPS **
550	nop; nop; nop
551	fmovs %f0, %f0
552	ba dont_fix_pil
553	fmovs %f0, %f0
554
555	.data
556	.global __sparc_fq
557	.align 8
558	__sparc_fq:
559	.word 0,0
560
561	.text
562	/* end of ERC32 FPU rev.B/C fix */
563
564	#else
565
566	mov %l0, %g5
567	subcc %g4, 0x11, %g0
568	bl dont_fix_pil
569	subcc %g4, 0x1f, %g0
570	bg dont_fix_pil
571	sll %g4, 8, %g4
572	and %g4, SPARC_PSR_PIL_MASK, %g4
573	andn %l0, SPARC_PSR_PIL_MASK, %g5
574	or %g4, %g5, %g5
575	#endif
576
577	dont_fix_pil:
578	wr %g5, SPARC_PSR_ET_MASK, %psr ! ** ENABLE TRAPS **
579	dont_fix_pil2:
580
581	/*
582	* Vector to user's handler.
583	*
584	* NOTE: TBR may no longer have vector number in it since
585	* we just enabled traps. It is definitely in l3.
586	*/
587
588	sethi %hi(SYM(_ISR_Vector_table)), %g4
589	or %g4, %lo(SYM(_ISR_Vector_table)), %g4
590	and %l3, 0xFF, %g5 ! remove synchronous trap indicator
591	sll %g5, 2, %g5 ! g5 = offset into table
592	ld [%g4 + %g5], %g4 ! g4 = _ISR_Vector_table[ vector ]
593
594
595	! o1 = 2nd arg = address of the ISF
596	! WAS LOADED WHEN ISF WAS SAVED!!!
597	mov %l3, %o0 ! o0 = 1st arg = vector number
598	call %g4, 0
599	nop ! delay slot
600
601	/*
602	* Redisable traps so we can finish up the interrupt processing.
603	* This is a VERY conservative place to do this.
604	*
605	* NOTE: %l0 has the PSR which was in place when we took the trap.
606	*/
607
608	mov %l0, %psr ! ** DISABLE TRAPS **
609
610	/*
611	* Decrement ISR nest level and Thread dispatch disable level.
612	*
613	* Register usage for this section:
614	*
615	* l4 = _Thread_Dispatch_disable_level pointer
616	* l5 = _ISR_Nest_level pointer
617	* l6 = _Thread_Dispatch_disable_level value
618	* l7 = _ISR_Nest_level value
619	*/
620
621	sub %l6, 1, %l6
622	st %l6, [%l4 + %lo(SYM(_Thread_Dispatch_disable_level))]
623
624	st %l7, [%l5 + %lo(SYM(_ISR_Nest_level))]
625
626	/*
627	* If dispatching is disabled (includes nested interrupt case),
628	* then do a "simple" exit.
629	*/
630
631	orcc %l6, %g0, %g0 ! Is dispatching disabled?
632	bnz simple_return ! Yes, then do a "simple" exit
633	nop ! delay slot
634
635	/*
636	* If a context switch is necessary, then do fudge stack to
637	* return to the interrupt dispatcher.
638	*/
639
640	sethi %hi(SYM(_Context_Switch_necessary)), %l4
641	ld [%l4 + %lo(SYM(_Context_Switch_necessary))], %l5
642
643	orcc %l5, %g0, %g0 ! Is thread switch necessary?
644	bnz SYM(_ISR_Dispatch) ! yes, then invoke the dispatcher
645	nop ! delay slot
646
647	/*
648	* Finally, check to see if signals were sent to the currently
649	* executing task. If so, we need to invoke the interrupt dispatcher.
650	*/
651
652	sethi %hi(SYM(_ISR_Signals_to_thread_executing)), %l6
653	ld [%l6 + %lo(SYM(_ISR_Signals_to_thread_executing))], %l7
654
655	orcc %l7, %g0, %g0 ! Were signals sent to the currently
656	! executing thread?
657	bz simple_return ! yes, then invoke the dispatcher
658	! use the delay slot to clear the signals
659	! to the currently executing task flag
660	st %g0, [%l6 + %lo(SYM(_ISR_Signals_to_thread_executing))]
661
662
663	/*
664	* Invoke interrupt dispatcher.
665	*/
666
667	PUBLIC(_ISR_Dispatch)
668	SYM(_ISR_Dispatch):
669
670	/*
671	* The following subtract should get us back on the interrupted
672	* tasks stack and add enough room to invoke the dispatcher.
673	* When we enable traps, we are mostly back in the context
674	* of the task and subsequent interrupts can operate normally.
675	*/
676
677	sub %fp, CPU_MINIMUM_STACK_FRAME_SIZE, %sp
678
679	or %l0, SPARC_PSR_ET_MASK, %l7 ! l7 = PSR with ET=1
680	mov %l7, %psr ! ** ENABLE TRAPS **
681	nop
682	nop
683	nop
684
685	call SYM(_Thread_Dispatch), 0
686	nop
687
688	/*
689	* The CWP in place at this point may be different from
690	* that which was in effect at the beginning of the ISR if we
691	* have been context switched between the beginning of this invocation
692	* of _ISR_Handler and this point. Thus the CWP and WIM should
693	* not be changed back to their values at ISR entry time. Any
694	* changes to the PSR must preserve the CWP.
695	*/
696
697	simple_return:
698	ld [%fp + ISF_Y_OFFSET], %l5 ! restore y
699	wr %l5, 0, %y
700
701	ldd [%fp + ISF_PSR_OFFSET], %l0 ! restore psr, PC
702	ld [%fp + ISF_NPC_OFFSET], %l2 ! restore nPC
703	rd %psr, %l3
704	and %l3, SPARC_PSR_CWP_MASK, %l3 ! want "current" CWP
705	andn %l0, SPARC_PSR_CWP_MASK, %l0 ! want rest from task
706	or %l3, %l0, %l0 ! install it later...
707	andn %l0, SPARC_PSR_ET_MASK, %l0
708
709	/*
710	* Restore tasks global and out registers
711	*/
712
713	mov %fp, %g1
714
715	! g1 is restored later
716	ldd [%fp + ISF_G2_OFFSET], %g2 ! restore g2, g3
717	ldd [%fp + ISF_G4_OFFSET], %g4 ! restore g4, g5
718	ldd [%fp + ISF_G6_OFFSET], %g6 ! restore g6, g7
719
720	ldd [%fp + ISF_I0_OFFSET], %i0 ! restore i0, i1
721	ldd [%fp + ISF_I2_OFFSET], %i2 ! restore i2, i3
722	ldd [%fp + ISF_I4_OFFSET], %i4 ! restore i4, i5
723	ldd [%fp + ISF_I6_FP_OFFSET], %i6 ! restore i6/fp, i7
724
725	/*
726	* Registers:
727	*
728	* ALL global registers EXCEPT G1 and the input registers have
729	* already been restored and thuse off limits.
730	*
731	* The following is the contents of the local registers:
732	*
733	* l0 = original psr
734	* l1 = return address (i.e. PC)
735	* l2 = nPC
736	* l3 = CWP
737	*/
738
739	/*
740	* if (CWP + 1) is an invalid window then we need to reload it.
741	*
742	* WARNING: Traps should now be disabled
743	*/
744
745	mov %l0, %psr ! ** DISABLE TRAPS **
746	nop
747	nop
748	nop
749	rd %wim, %l4
750	add %l0, 1, %l6 ! l6 = cwp + 1
751	and %l6, SPARC_PSR_CWP_MASK, %l6 ! do the modulo on it
752	srl %l4, %l6, %l5 ! l5 = win >> cwp + 1 ; shift count
753	! and CWP are conveniently LS 5 bits
754	cmp %l5, 1 ! Is tasks window invalid?
755	bne good_task_window
756
757	/*
758	* The following code is the same as a 1 position left rotate of WIM.
759	*/
760
761	sll %l4, 1, %l5 ! l5 = WIM << 1
762	srl %l4, SPARC_NUMBER_OF_REGISTER_WINDOWS-1 , %l4
763	! l4 = WIM >> (Number Windows - 1)
764	or %l4, %l5, %l4 ! l4 = (WIM << 1) \|
765	! (WIM >> (Number Windows - 1))
766
767	/*
768	* Now restore the window just as if we underflowed to it.
769	*/
770
771	wr %l4, 0, %wim ! WIM = new WIM
772	nop ! must delay after writing WIM
773	nop
774	nop
775	restore ! now into the tasks window
776
777	ldd [%g1 + CPU_STACK_FRAME_L0_OFFSET], %l0
778	ldd [%g1 + CPU_STACK_FRAME_L2_OFFSET], %l2
779	ldd [%g1 + CPU_STACK_FRAME_L4_OFFSET], %l4
780	ldd [%g1 + CPU_STACK_FRAME_L6_OFFSET], %l6
781	ldd [%g1 + CPU_STACK_FRAME_I0_OFFSET], %i0
782	ldd [%g1 + CPU_STACK_FRAME_I2_OFFSET], %i2
783	ldd [%g1 + CPU_STACK_FRAME_I4_OFFSET], %i4
784	ldd [%g1 + CPU_STACK_FRAME_I6_FP_OFFSET], %i6
785	! reload of sp clobbers ISF
786	save ! Back to ISR dispatch window
787
788	good_task_window:
789
790	mov %l0, %psr ! ** DISABLE TRAPS **
791	! and restore condition codes.
792	ld [%g1 + ISF_G1_OFFSET], %g1 ! restore g1
793	jmp %l1 ! transfer control and
794	rett %l2 ! go back to tasks window
795
796	/* end of file */

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