source: rtems/c/src/exec/score/cpu/sh/rtems/score/ispsh7032.h @ df49c60

4.104.114.84.95
Last change on this file since df49c60 was 7908ba5b, checked in by Joel Sherrill <joel.sherrill@…>, on 02/18/99 at 18:28:24

Part of the automake VI patch from Ralf Corsepius <corsepiu@…>:

4) rtems-rc-19990202-0.diff /reorg-score-cpu.sh

reorg-score-cpu.sh reorganizes the cpu/<cpu>/* subdirectories in a
similar manner than previous reorg scripts did. rtems-rc-19990202-0.diff
contains the diffs after reorg-score-cpu.sh has been run on a
rtems-19981215 snapshot + my patches up to rtems-rc-19990131-2.diff.

This patch is rather nasty and may break something. However, I've tested
it for about 10 different target/bsp pairs and believe to have shaken
out most bugs.

I wonder about the following .h files that were not moved:

a29k/asm.h
a29k/cpu_asm.h
i386/asm.h
i960/asm.h
m68k/asm.h
m68k/m68302.h
m68k/m68360.h
m68k/qsm.h
m68k/sim.h
mips64orion/asm.h
mips64orion/cpu_asm.h
mips64orion/mips64orion.h
no_cpu/asm.h
no_cpu/cpu_asm.h
powerpc/asm.h
powerpc/mpc860.h
sh/asm.h
sparc/asm.h
sparc/erc32.h

  • Property mode set to 100644
File size: 3.6 KB
Line 
1/*
2 *  This include file contains information pertaining to the Hitachi SH
3 *  processor.
4 *
5 *  Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
6 *           Bernd Becker (becker@faw.uni-ulm.de)
7 *
8 *  COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
9 *
10 *  This program is distributed in the hope that it will be useful,
11 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
12 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
13 *
14 *
15 *  COPYRIGHT (c) 1998.
16 *  On-Line Applications Research Corporation (OAR).
17 *  Copyright assigned to U.S. Government, 1994.
18 *
19 *  The license and distribution terms for this file may be
20 *  found in the file LICENSE in this distribution or at
21 *  http://www.OARcorp.com/rtems/license.html.
22 *
23 *  $Id$
24 */
25
26#ifndef __CPU_ISPS_H
27#define __CPU_ISPS_H
28
29#ifdef __cplusplus
30extern "C" {
31#endif
32
33#include <rtems/score/shtypes.h>
34
35extern void __ISR_Handler( unsigned32 vector );
36
37
38/*
39 * interrupt vector table offsets
40 */
41#define NMI_ISP_V 11
42#define USB_ISP_V 12
43#define IRQ0_ISP_V 64
44#define IRQ1_ISP_V 65
45#define IRQ2_ISP_V 66
46#define IRQ3_ISP_V 67
47#define IRQ4_ISP_V 68
48#define IRQ5_ISP_V 69
49#define IRQ6_ISP_V 70
50#define IRQ7_ISP_V 71
51#define DMA0_ISP_V 72
52#define DMA1_ISP_V 74
53#define DMA2_ISP_V 76
54#define DMA3_ISP_V 78
55
56#define IMIA0_ISP_V 80
57#define IMIB0_ISP_V 81
58#define OVI0_ISP_V 82
59
60#define IMIA1_ISP_V 84
61#define IMIB1_ISP_V 85
62#define OVI1_ISP_V 86
63
64#define IMIA2_ISP_V 88
65#define IMIB2_ISP_V 89
66#define OVI2_ISP_V 90
67
68#define IMIA3_ISP_V 92
69#define IMIB3_ISP_V 93
70#define OVI3_ISP_V 94
71
72#define IMIA4_ISP_V 96
73#define IMIB4_ISP_V 97
74#define OVI4_ISP_V 98
75
76#define ERI0_ISP_V 100
77#define RXI0_ISP_V 101
78#define TXI0_ISP_V 102
79#define TEI0_ISP_V 103
80
81#define ERI1_ISP_V 104
82#define RXI1_ISP_V 105
83#define TXI1_ISP_V 106
84#define TEI1_ISP_V 107
85
86#define PRT_ISP_V 108
87#define ADU_ISP_V 109
88#define WDT_ISP_V 112
89#define DREF_ISP_V 113
90
91
92/* dummy ISP */
93extern void _dummy_isp( void );
94
95/* Non Maskable Interrupt */
96extern void _nmi_isp( void );
97
98/* User Break Controller */
99extern void _usb_isp( void );
100
101/* External interrupts 0-7 */
102extern void _irq0_isp( void );
103extern void _irq1_isp( void );
104extern void _irq2_isp( void );
105extern void _irq3_isp( void );
106extern void _irq4_isp( void );
107extern void _irq5_isp( void );
108extern void _irq6_isp( void );
109extern void _irq7_isp( void );
110
111/* DMA - Controller */
112extern void _dma0_isp( void );
113extern void _dma1_isp( void );
114extern void _dma2_isp( void );
115extern void _dma3_isp( void );
116
117/* Interrupt Timer Unit */
118/* Timer 0 */
119extern void _imia0_isp( void );
120extern void _imib0_isp( void );
121extern void _ovi0_isp( void );
122/* Timer 1 */
123extern void _imia1_isp( void );
124extern void _imib1_isp( void );
125extern void _ovi1_isp( void );
126/* Timer 2 */
127extern void _imia2_isp( void );
128extern void _imib2_isp( void );
129extern void _ovi2_isp( void );
130/* Timer 3 */
131extern void _imia3_isp( void );
132extern void _imib3_isp( void );
133extern void _ovi3_isp( void );
134/* Timer 4 */
135extern void _imia4_isp( void );
136extern void _imib4_isp( void );
137extern void _ovi4_isp( void );
138
139/* seriell interfaces */
140extern void _eri0_isp( void );
141extern void _rxi0_isp( void );
142extern void _txi0_isp( void );
143extern void _tei0_isp( void );
144extern void _eri1_isp( void );
145extern void _rxi1_isp( void );
146extern void _txi1_isp( void );
147extern void _tei1_isp( void );
148
149/* Parity Control Unit of the Bus State Controllers */
150extern void _prt_isp( void );
151
152/* ADC */
153extern void _adu_isp( void );
154
155/* Watchdog Timer */
156extern void _wdt_isp( void );
157
158/* DRAM refresh control unit of bus state controller */
159extern void _dref_isp( void );
160
161#ifdef __cplusplus
162}
163#endif
164
165#endif
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