1 | /* |
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2 | * This include file contains information pertaining to the Hitachi SH |
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3 | * processor. |
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4 | * |
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5 | * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and |
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6 | * Bernd Becker (becker@faw.uni-ulm.de) |
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7 | * |
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8 | * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany |
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9 | * |
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10 | * This program is distributed in the hope that it will be useful, |
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11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
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13 | * |
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14 | * |
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15 | * COPYRIGHT (c) 1998. |
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16 | * On-Line Applications Research Corporation (OAR). |
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17 | * Copyright assigned to U.S. Government, 1994. |
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18 | * |
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19 | * The license and distribution terms for this file may be |
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20 | * found in the file LICENSE in this distribution or at |
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21 | * http://www.OARcorp.com/rtems/license.html. |
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22 | * |
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23 | * $Id$ |
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24 | */ |
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25 | |
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26 | #ifndef __CPU_ISPS_H |
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27 | #define __CPU_ISPS_H |
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28 | |
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29 | #ifdef __cplusplus |
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30 | extern "C" { |
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31 | #endif |
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32 | |
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33 | #include <rtems/score/shtypes.h> |
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34 | |
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35 | extern void __ISR_Handler( unsigned32 vector ); |
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36 | |
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37 | |
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38 | /* |
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39 | * interrupt vector table offsets |
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40 | */ |
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41 | #define NMI_ISP_V 11 |
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42 | #define USB_ISP_V 12 |
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43 | #define IRQ0_ISP_V 64 |
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44 | #define IRQ1_ISP_V 65 |
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45 | #define IRQ2_ISP_V 66 |
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46 | #define IRQ3_ISP_V 67 |
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47 | #define IRQ4_ISP_V 68 |
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48 | #define IRQ5_ISP_V 69 |
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49 | #define IRQ6_ISP_V 70 |
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50 | #define IRQ7_ISP_V 71 |
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51 | #define DMA0_ISP_V 72 |
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52 | #define DMA1_ISP_V 74 |
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53 | #define DMA2_ISP_V 76 |
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54 | #define DMA3_ISP_V 78 |
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55 | |
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56 | #define IMIA0_ISP_V 80 |
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57 | #define IMIB0_ISP_V 81 |
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58 | #define OVI0_ISP_V 82 |
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59 | |
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60 | #define IMIA1_ISP_V 84 |
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61 | #define IMIB1_ISP_V 85 |
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62 | #define OVI1_ISP_V 86 |
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63 | |
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64 | #define IMIA2_ISP_V 88 |
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65 | #define IMIB2_ISP_V 89 |
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66 | #define OVI2_ISP_V 90 |
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67 | |
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68 | #define IMIA3_ISP_V 92 |
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69 | #define IMIB3_ISP_V 93 |
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70 | #define OVI3_ISP_V 94 |
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71 | |
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72 | #define IMIA4_ISP_V 96 |
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73 | #define IMIB4_ISP_V 97 |
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74 | #define OVI4_ISP_V 98 |
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75 | |
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76 | #define ERI0_ISP_V 100 |
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77 | #define RXI0_ISP_V 101 |
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78 | #define TXI0_ISP_V 102 |
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79 | #define TEI0_ISP_V 103 |
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80 | |
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81 | #define ERI1_ISP_V 104 |
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82 | #define RXI1_ISP_V 105 |
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83 | #define TXI1_ISP_V 106 |
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84 | #define TEI1_ISP_V 107 |
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85 | |
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86 | #define PRT_ISP_V 108 |
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87 | #define ADU_ISP_V 109 |
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88 | #define WDT_ISP_V 112 |
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89 | #define DREF_ISP_V 113 |
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90 | |
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91 | |
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92 | /* dummy ISP */ |
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93 | extern void _dummy_isp( void ); |
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94 | |
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95 | /* Non Maskable Interrupt */ |
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96 | extern void _nmi_isp( void ); |
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97 | |
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98 | /* User Break Controller */ |
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99 | extern void _usb_isp( void ); |
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100 | |
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101 | /* External interrupts 0-7 */ |
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102 | extern void _irq0_isp( void ); |
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103 | extern void _irq1_isp( void ); |
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104 | extern void _irq2_isp( void ); |
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105 | extern void _irq3_isp( void ); |
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106 | extern void _irq4_isp( void ); |
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107 | extern void _irq5_isp( void ); |
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108 | extern void _irq6_isp( void ); |
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109 | extern void _irq7_isp( void ); |
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110 | |
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111 | /* DMA - Controller */ |
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112 | extern void _dma0_isp( void ); |
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113 | extern void _dma1_isp( void ); |
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114 | extern void _dma2_isp( void ); |
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115 | extern void _dma3_isp( void ); |
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116 | |
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117 | /* Interrupt Timer Unit */ |
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118 | /* Timer 0 */ |
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119 | extern void _imia0_isp( void ); |
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120 | extern void _imib0_isp( void ); |
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121 | extern void _ovi0_isp( void ); |
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122 | /* Timer 1 */ |
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123 | extern void _imia1_isp( void ); |
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124 | extern void _imib1_isp( void ); |
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125 | extern void _ovi1_isp( void ); |
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126 | /* Timer 2 */ |
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127 | extern void _imia2_isp( void ); |
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128 | extern void _imib2_isp( void ); |
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129 | extern void _ovi2_isp( void ); |
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130 | /* Timer 3 */ |
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131 | extern void _imia3_isp( void ); |
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132 | extern void _imib3_isp( void ); |
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133 | extern void _ovi3_isp( void ); |
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134 | /* Timer 4 */ |
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135 | extern void _imia4_isp( void ); |
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136 | extern void _imib4_isp( void ); |
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137 | extern void _ovi4_isp( void ); |
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138 | |
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139 | /* seriell interfaces */ |
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140 | extern void _eri0_isp( void ); |
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141 | extern void _rxi0_isp( void ); |
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142 | extern void _txi0_isp( void ); |
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143 | extern void _tei0_isp( void ); |
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144 | extern void _eri1_isp( void ); |
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145 | extern void _rxi1_isp( void ); |
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146 | extern void _txi1_isp( void ); |
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147 | extern void _tei1_isp( void ); |
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148 | |
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149 | /* Parity Control Unit of the Bus State Controllers */ |
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150 | extern void _prt_isp( void ); |
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151 | |
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152 | /* ADC */ |
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153 | extern void _adu_isp( void ); |
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154 | |
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155 | /* Watchdog Timer */ |
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156 | extern void _wdt_isp( void ); |
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157 | |
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158 | /* DRAM refresh control unit of bus state controller */ |
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159 | extern void _dref_isp( void ); |
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160 | |
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161 | #ifdef __cplusplus |
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162 | } |
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163 | #endif |
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164 | |
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165 | #endif |
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