source: rtems/c/src/exec/score/cpu/sh/rtems/score/cpu.h @ df49c60

4.104.114.84.95
Last change on this file since df49c60 was 4a238002, checked in by Joel Sherrill <joel.sherrill@…>, on Nov 18, 1999 at 9:22:58 PM

Patch from "John M. Mills" <jmills@…> with subsequent cleanup from
Ralf Corsepius <corsepiu@…> that adds initial Hitachi SH-2
support to RTEMS. Ralf's comments are:

Changes:
------

  1. SH-Port:
  • Many files renamed.
  • CONSOLE_DEVNAME and MHZ defines removed from libcpu.
  • console.c moved to libbsp/sh/shared, build in libbsp/sh/<BSP>/console applying VPATH.
  • CONSOLE_DEVNAME made BSP-specific, replacement is defined in bsp.h
  • MHZ define replaced with HZ (extendent resolution) in custom/*.cfg
  • -DHZ=HZ used in bspstart.c, only
  • Makefile variable HZ used in bsp-dependent directories only.
  1. SH1-Port
  • clock-driver rewritten to provide better resolution for odd CPU frequencies. This driver is only partially tested on hardware, ie. sightly experimental, but I don't expect severe problems with it.
  • Polling SCI-driver added. This driver is experimental and completly untested yet. Therefore it is not yet used for the console (/dev/console is still pointing to /dev/null, cf. gensh1/bsp.h).
  • minor changes to the timer driver
  • SH1 specific delay()/CPU_delay() now is implemented as a function
  1. SH2-Port
  • Merged
  • IMO, the code is still in its infancy. Therefore I have interspersed comments (FIXME) it for items which I think John should look after.
  • sci and console drivers partially rewritten and extended (John, I hope you don't mind).
  • Copyright notices are not yet adapted
  • Property mode set to 100644
File size: 28.1 KB
Line 
1/*
2 *  This include file contains information pertaining to the Hitachi SH
3 *  processor.
4 *
5 *  Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
6 *           Bernd Becker (becker@faw.uni-ulm.de)
7 *
8 *  COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
9 *
10 *  This program is distributed in the hope that it will be useful,
11 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
12 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
13 *
14 *
15 *  COPYRIGHT (c) 1998.
16 *  On-Line Applications Research Corporation (OAR).
17 *  Copyright assigned to U.S. Government, 1994.
18 *
19 *  The license and distribution terms for this file may be
20 *  found in the file LICENSE in this distribution or at
21 *  http://www.OARcorp.com/rtems/license.html.
22 *
23 *  $Id$
24 */
25
26#ifndef _SH_CPU_h
27#define _SH_CPU_h
28
29#ifdef __cplusplus
30extern "C" {
31#endif
32
33#include <rtems/score/sh.h>              /* pick up machine definitions */
34#ifndef ASM
35#include <rtems/score/shtypes.h>
36#endif
37
38/* conditional compilation parameters */
39
40/*
41 *  Should the calls to _Thread_Enable_dispatch be inlined?
42 *
43 *  If TRUE, then they are inlined.
44 *  If FALSE, then a subroutine call is made.
45 *
46 *  Basically this is an example of the classic trade-off of size
47 *  versus speed.  Inlining the call (TRUE) typically increases the
48 *  size of RTEMS while speeding up the enabling of dispatching.
49 *  [NOTE: In general, the _Thread_Dispatch_disable_level will
50 *  only be 0 or 1 unless you are in an interrupt handler and that
51 *  interrupt handler invokes the executive.]  When not inlined
52 *  something calls _Thread_Enable_dispatch which in turns calls
53 *  _Thread_Dispatch.  If the enable dispatch is inlined, then
54 *  one subroutine call is avoided entirely.]
55 */
56
57#define CPU_INLINE_ENABLE_DISPATCH       FALSE
58
59/*
60 *  Should the body of the search loops in _Thread_queue_Enqueue_priority
61 *  be unrolled one time?  In unrolled each iteration of the loop examines
62 *  two "nodes" on the chain being searched.  Otherwise, only one node
63 *  is examined per iteration.
64 *
65 *  If TRUE, then the loops are unrolled.
66 *  If FALSE, then the loops are not unrolled.
67 *
68 *  The primary factor in making this decision is the cost of disabling
69 *  and enabling interrupts (_ISR_Flash) versus the cost of rest of the
70 *  body of the loop.  On some CPUs, the flash is more expensive than
71 *  one iteration of the loop body.  In this case, it might be desirable
72 *  to unroll the loop.  It is important to note that on some CPUs, this
73 *  code is the longest interrupt disable period in RTEMS.  So it is
74 *  necessary to strike a balance when setting this parameter.
75 */
76
77#define CPU_UNROLL_ENQUEUE_PRIORITY      TRUE
78
79/*
80 *  Does RTEMS manage a dedicated interrupt stack in software?
81 *
82 *  If TRUE, then a stack is allocated in _Interrupt_Manager_initialization.
83 *  If FALSE, nothing is done.
84 *
85 *  If the CPU supports a dedicated interrupt stack in hardware,
86 *  then it is generally the responsibility of the BSP to allocate it
87 *  and set it up.
88 *
89 *  If the CPU does not support a dedicated interrupt stack, then
90 *  the porter has two options: (1) execute interrupts on the
91 *  stack of the interrupted task, and (2) have RTEMS manage a dedicated
92 *  interrupt stack.
93 *
94 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
95 *
96 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
97 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
98 *  possible that both are FALSE for a particular CPU.  Although it
99 *  is unclear what that would imply about the interrupt processing
100 *  procedure on that CPU.
101 */
102
103#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE
104#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
105
106/*
107 * We define the interrupt stack in the linker script
108 */
109#define CPU_ALLOCATE_INTERRUPT_STACK FALSE
110
111/*
112 *  Does the RTEMS invoke the user's ISR with the vector number and
113 *  a pointer to the saved interrupt frame (1) or just the vector
114 *  number (0)?
115 */
116
117#define CPU_ISR_PASSES_FRAME_POINTER 0
118
119/*
120 *  Does the CPU have hardware floating point?
121 *
122 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
123 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
124 *
125 *  We currently support sh1 only, which has no FPU, other SHes have an FPU
126 *
127 *  The macro name "NO_CPU_HAS_FPU" should be made CPU specific.
128 *  It indicates whether or not this CPU model has FP support.  For
129 *  example, it would be possible to have an i386_nofp CPU model
130 *  which set this to false to indicate that you have an i386 without
131 *  an i387 and wish to leave floating point support out of RTEMS.
132 */
133
134#define CPU_HARDWARE_FP     FALSE
135
136/*
137 *  Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
138 *
139 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
140 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
141 *
142 *  So far, the only CPU in which this option has been used is the
143 *  HP PA-RISC.  The HP C compiler and gcc both implicitly use the
144 *  floating point registers to perform integer multiplies.  If
145 *  a function which you would not think utilize the FP unit DOES,
146 *  then one can not easily predict which tasks will use the FP hardware.
147 *  In this case, this option should be TRUE.
148 *
149 *  If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
150 */
151
152#define CPU_ALL_TASKS_ARE_FP     FALSE
153
154/*
155 *  Should the IDLE task have a floating point context?
156 *
157 *  If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
158 *  and it has a floating point context which is switched in and out.
159 *  If FALSE, then the IDLE task does not have a floating point context.
160 *
161 *  Setting this to TRUE negatively impacts the time required to preempt
162 *  the IDLE task from an interrupt because the floating point context
163 *  must be saved as part of the preemption.
164 */
165
166#define CPU_IDLE_TASK_IS_FP      FALSE
167
168/*
169 *  Should the saving of the floating point registers be deferred
170 *  until a context switch is made to another different floating point
171 *  task?
172 *
173 *  If TRUE, then the floating point context will not be stored until
174 *  necessary.  It will remain in the floating point registers and not
175 *  disturned until another floating point task is switched to.
176 *
177 *  If FALSE, then the floating point context is saved when a floating
178 *  point task is switched out and restored when the next floating point
179 *  task is restored.  The state of the floating point registers between
180 *  those two operations is not specified.
181 *
182 *  If the floating point context does NOT have to be saved as part of
183 *  interrupt dispatching, then it should be safe to set this to TRUE.
184 *
185 *  Setting this flag to TRUE results in using a different algorithm
186 *  for deciding when to save and restore the floating point context.
187 *  The deferred FP switch algorithm minimizes the number of times
188 *  the FP context is saved and restored.  The FP context is not saved
189 *  until a context switch is made to another, different FP task.
190 *  Thus in a system with only one FP task, the FP context will never
191 *  be saved or restored.
192 */
193
194#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
195
196/*
197 *  Does this port provide a CPU dependent IDLE task implementation?
198 *
199 *  If TRUE, then the routine _CPU_Thread_Idle_body
200 *  must be provided and is the default IDLE thread body instead of
201 *  _CPU_Thread_Idle_body.
202 *
203 *  If FALSE, then use the generic IDLE thread body if the BSP does
204 *  not provide one.
205 *
206 *  This is intended to allow for supporting processors which have
207 *  a low power or idle mode.  When the IDLE thread is executed, then
208 *  the CPU can be powered down.
209 *
210 *  The order of precedence for selecting the IDLE thread body is:
211 *
212 *    1.  BSP provided
213 *    2.  CPU dependent (if provided)
214 *    3.  generic (if no BSP and no CPU dependent)
215 */
216
217#define CPU_PROVIDES_IDLE_THREAD_BODY    TRUE
218
219/*
220 *  Does the stack grow up (toward higher addresses) or down
221 *  (toward lower addresses)?
222 *
223 *  If TRUE, then the grows upward.
224 *  If FALSE, then the grows toward smaller addresses.
225 */
226
227#define CPU_STACK_GROWS_UP               FALSE
228
229/*
230 *  The following is the variable attribute used to force alignment
231 *  of critical RTEMS structures.  On some processors it may make
232 *  sense to have these aligned on tighter boundaries than
233 *  the minimum requirements of the compiler in order to have as
234 *  much of the critical data area as possible in a cache line.
235 *
236 *  The placement of this macro in the declaration of the variables
237 *  is based on the syntactically requirements of the GNU C
238 *  "__attribute__" extension.  For example with GNU C, use
239 *  the following to force a structures to a 32 byte boundary.
240 *
241 *      __attribute__ ((aligned (32)))
242 *
243 *  NOTE:  Currently only the Priority Bit Map table uses this feature.
244 *         To benefit from using this, the data must be heavily
245 *         used so it will stay in the cache and used frequently enough
246 *         in the executive to justify turning this on.
247 */
248
249#define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned(16)))
250
251/*
252 *  Define what is required to specify how the network to host conversion
253 *  routines are handled.
254 *
255 *  NOTE: SHes can be big or little endian, the default is big endian
256 */
257
258#define CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES     FALSE
259
260/* __LITTLE_ENDIAN__ is defined if -ml is given to gcc */
261#if defined(__LITTLE_ENDIAN__)
262#define CPU_BIG_ENDIAN                           FALSE
263#define CPU_LITTLE_ENDIAN                        TRUE
264#else
265#define CPU_BIG_ENDIAN                           TRUE
266#define CPU_LITTLE_ENDIAN                        FALSE
267#endif
268 
269/*
270 *  The following defines the number of bits actually used in the
271 *  interrupt field of the task mode.  How those bits map to the
272 *  CPU interrupt levels is defined by the routine _CPU_ISR_Set_level().
273 */
274
275#define CPU_MODES_INTERRUPT_MASK   0x0000000f
276
277/*
278 *  Processor defined structures
279 *
280 *  Examples structures include the descriptor tables from the i386
281 *  and the processor control structure on the i960ca.
282 */
283
284/* may need to put some structures here.  */
285
286/*
287 * Contexts
288 *
289 *  Generally there are 2 types of context to save.
290 *     1. Interrupt registers to save
291 *     2. Task level registers to save
292 *
293 *  This means we have the following 3 context items:
294 *     1. task level context stuff::  Context_Control
295 *     2. floating point task stuff:: Context_Control_fp
296 *     3. special interrupt level context :: Context_Control_interrupt
297 *
298 *  On some processors, it is cost-effective to save only the callee
299 *  preserved registers during a task context switch.  This means
300 *  that the ISR code needs to save those registers which do not
301 *  persist across function calls.  It is not mandatory to make this
302 *  distinctions between the caller/callee saves registers for the
303 *  purpose of minimizing context saved during task switch and on interrupts.
304 *  If the cost of saving extra registers is minimal, simplicity is the
305 *  choice.  Save the same context on interrupt entry as for tasks in
306 *  this case.
307 *
308 *  Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
309 *  care should be used in designing the context area.
310 *
311 *  On some CPUs with hardware floating point support, the Context_Control_fp
312 *  structure will not be used or it simply consist of an array of a
313 *  fixed number of bytes.   This is done when the floating point context
314 *  is dumped by a "FP save context" type instruction and the format
315 *  is not really defined by the CPU.  In this case, there is no need
316 *  to figure out the exact format -- only the size.  Of course, although
317 *  this is enough information for RTEMS, it is probably not enough for
318 *  a debugger such as gdb.  But that is another problem.
319 */
320
321typedef struct {
322  unsigned32 *r15;      /* stack pointer */
323
324  unsigned32 macl;
325  unsigned32 mach;
326  unsigned32 *pr;
327
328  unsigned32 *r14;      /* frame pointer/call saved */
329
330  unsigned32 r13;       /* call saved */
331  unsigned32 r12;       /* call saved */
332  unsigned32 r11;       /* call saved */
333  unsigned32 r10;       /* call saved */
334  unsigned32 r9;        /* call saved */
335  unsigned32 r8;        /* call saved */
336
337  unsigned32 *r7;       /* arg in */
338  unsigned32 *r6;       /* arg in */
339
340#if 0
341  unsigned32 *r5;       /* arg in */
342  unsigned32 *r4;       /* arg in */
343#endif
344
345  unsigned32 *r3;       /* scratch */
346  unsigned32 *r2;       /* scratch */
347  unsigned32 *r1;       /* scratch */
348
349  unsigned32 *r0;       /* arg return */
350
351  unsigned32 gbr;
352  unsigned32 sr; 
353
354} Context_Control;
355
356typedef struct {
357} Context_Control_fp;
358
359typedef struct {
360} CPU_Interrupt_frame;
361
362
363/*
364 *  The following table contains the information required to configure
365 *  the SH processor specific parameters.
366 */
367
368typedef struct {
369  void       (*pretasking_hook)( void );
370  void       (*predriver_hook)( void );
371  void       (*postdriver_hook)( void );
372  void       (*idle_task)( void );
373  boolean      do_zero_of_workspace;
374  unsigned32   idle_task_stack_size;
375  unsigned32   interrupt_stack_size;
376  unsigned32   extra_mpci_receive_server_stack;
377  void *     (*stack_allocate_hook)( unsigned32 );
378  void       (*stack_free_hook)( void* );
379  /* end of fields required on all CPUs */
380  unsigned32    clicks_per_second ; /* cpu frequency in Hz */
381}   rtems_cpu_table;
382
383/*
384 *  Macros to access required entires in the CPU Table are in
385 *  the file rtems/system.h.
386 */
387
388/*
389 *  Macros to access SH specific additions to the CPU Table
390 */
391
392#define rtems_cpu_configuration_get_clicks_per_second() \
393  (_CPU_Table.clicks_per_second)
394   
395/*
396 *  This variable is optional.  It is used on CPUs on which it is difficult
397 *  to generate an "uninitialized" FP context.  It is filled in by
398 *  _CPU_Initialize and copied into the task's FP context area during
399 *  _CPU_Context_Initialize.
400 */
401
402/*
403SCORE_EXTERN Context_Control_fp  _CPU_Null_fp_context;
404*/
405
406/*
407 *  On some CPUs, RTEMS supports a software managed interrupt stack.
408 *  This stack is allocated by the Interrupt Manager and the switch
409 *  is performed in _ISR_Handler.  These variables contain pointers
410 *  to the lowest and highest addresses in the chunk of memory allocated
411 *  for the interrupt stack.  Since it is unknown whether the stack
412 *  grows up or down (in general), this give the CPU dependent
413 *  code the option of picking the version it wants to use.
414 *
415 *  NOTE: These two variables are required if the macro
416 *        CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
417 */
418
419SCORE_EXTERN void               *_CPU_Interrupt_stack_low;
420SCORE_EXTERN void               *_CPU_Interrupt_stack_high;
421
422/*
423 *  With some compilation systems, it is difficult if not impossible to
424 *  call a high-level language routine from assembly language.  This
425 *  is especially true of commercial Ada compilers and name mangling
426 *  C++ ones.  This variable can be optionally defined by the CPU porter
427 *  and contains the address of the routine _Thread_Dispatch.  This
428 *  can make it easier to invoke that routine at the end of the interrupt
429 *  sequence (if a dispatch is necessary).
430 */
431
432SCORE_EXTERN void           (*_CPU_Thread_dispatch_pointer)();
433
434/*
435 *  Nothing prevents the porter from declaring more CPU specific variables.
436 */
437
438/* XXX: if needed, put more variables here */
439SCORE_EXTERN void CPU_delay( unsigned32 microseconds );
440
441/*
442 *  The size of the floating point context area.  On some CPUs this
443 *  will not be a "sizeof" because the format of the floating point
444 *  area is not defined -- only the size is.  This is usually on
445 *  CPUs with a "floating point save context" instruction.
446 */
447
448#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
449
450/*
451 *  Amount of extra stack (above minimum stack size) required by
452 *  MPCI receive server thread.  Remember that in a multiprocessor
453 *  system this thread must exist and be able to process all directives.
454 */
455
456#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
457
458/*
459 *  This defines the number of entries in the ISR_Vector_table managed
460 *  by RTEMS.
461 */
462
463#define CPU_INTERRUPT_NUMBER_OF_VECTORS      256
464#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
465
466/*
467 *  Should be large enough to run all RTEMS tests.  This insures
468 *  that a "reasonable" small application should not have any problems.
469 *
470 *  We have been able to run the sptests with this value, but have not
471 *  been able to run the tmtest suite.
472 */
473
474#define CPU_STACK_MINIMUM_SIZE          4096
475
476/*
477 *  CPU's worst alignment requirement for data types on a byte boundary.  This
478 *  alignment does not take into account the requirements for the stack.
479 */
480
481#define CPU_ALIGNMENT              4
482
483/*
484 *  This number corresponds to the byte alignment requirement for the
485 *  heap handler.  This alignment requirement may be stricter than that
486 *  for the data types alignment specified by CPU_ALIGNMENT.  It is
487 *  common for the heap to follow the same alignment requirement as
488 *  CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict enough for the heap,
489 *  then this should be set to CPU_ALIGNMENT.
490 *
491 *  NOTE:  This does not have to be a power of 2.  It does have to
492 *         be greater or equal to than CPU_ALIGNMENT.
493 */
494
495#define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT
496
497/*
498 *  This number corresponds to the byte alignment requirement for memory
499 *  buffers allocated by the partition manager.  This alignment requirement
500 *  may be stricter than that for the data types alignment specified by
501 *  CPU_ALIGNMENT.  It is common for the partition to follow the same
502 *  alignment requirement as CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict
503 *  enough for the partition, then this should be set to CPU_ALIGNMENT.
504 *
505 *  NOTE:  This does not have to be a power of 2.  It does have to
506 *         be greater or equal to than CPU_ALIGNMENT.
507 */
508
509#define CPU_PARTITION_ALIGNMENT    CPU_ALIGNMENT
510
511/*
512 *  This number corresponds to the byte alignment requirement for the
513 *  stack.  This alignment requirement may be stricter than that for the
514 *  data types alignment specified by CPU_ALIGNMENT.  If the CPU_ALIGNMENT
515 *  is strict enough for the stack, then this should be set to 0.
516 *
517 *  NOTE:  This must be a power of 2 either 0 or greater than CPU_ALIGNMENT.
518 */
519
520#define CPU_STACK_ALIGNMENT        CPU_ALIGNMENT
521
522/* ISR handler macros */
523
524/*
525 *  Disable all interrupts for an RTEMS critical section.  The previous
526 *  level is returned in _level.
527 */
528
529#define _CPU_ISR_Disable( _level) \
530  sh_disable_interrupts( _level )
531
532/*
533 *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
534 *  This indicates the end of an RTEMS critical section.  The parameter
535 *  _level is not modified.
536 */
537
538#define _CPU_ISR_Enable( _level) \
539   sh_enable_interrupts( _level)
540
541/*
542 *  This temporarily restores the interrupt to _level before immediately
543 *  disabling them again.  This is used to divide long RTEMS critical
544 *  sections into two or more parts.  The parameter _level is not
545 * modified.
546 */
547
548#define _CPU_ISR_Flash( _level) \
549  sh_flash_interrupts( _level)
550
551/*
552 *  Map interrupt level in task mode onto the hardware that the CPU
553 *  actually provides.  Currently, interrupt levels which do not
554 *  map onto the CPU in a generic fashion are undefined.  Someday,
555 *  it would be nice if these were "mapped" by the application
556 *  via a callout.  For example, m68k has 8 levels 0 - 7, levels
557 *  8 - 255 would be available for bsp/application specific meaning.
558 *  This could be used to manage a programmable interrupt controller
559 *  via the rtems_task_mode directive.
560 */
561
562#define _CPU_ISR_Set_level( _newlevel) \
563  sh_set_interrupt_level(_newlevel)
564
565unsigned32 _CPU_ISR_Get_level( void );
566
567/* end of ISR handler macros */
568
569/* Context handler macros */
570
571/*
572 *  Initialize the context to a state suitable for starting a
573 *  task after a context restore operation.  Generally, this
574 *  involves:
575 *
576 *     - setting a starting address
577 *     - preparing the stack
578 *     - preparing the stack and frame pointers
579 *     - setting the proper interrupt level in the context
580 *     - initializing the floating point context
581 *
582 *  This routine generally does not set any unnecessary register
583 *  in the context.  The state of the "general data" registers is
584 *  undefined at task start time.
585 *
586 *  NOTE: This is_fp parameter is TRUE if the thread is to be a floating
587 *        point thread.  This is typically only used on CPUs where the
588 *        FPU may be easily disabled by software such as on the SPARC
589 *        where the PSR contains an enable FPU bit.
590 */
591
592/*
593 * FIXME: defined as a function for debugging - should be a macro
594 */
595SCORE_EXTERN void _CPU_Context_Initialize(
596  Context_Control       *_the_context,
597  void                  *_stack_base,
598  unsigned32            _size,
599  unsigned32            _isr,
600  void    (*_entry_point)(void),
601  int                   _is_fp );
602
603/*
604 *  This routine is responsible for somehow restarting the currently
605 *  executing task.  If you are lucky, then all that is necessary
606 *  is restoring the context.  Otherwise, there will need to be
607 *  a special assembly routine which does something special in this
608 *  case.  Context_Restore should work most of the time.  It will
609 *  not work if restarting self conflicts with the stack frame
610 *  assumptions of restoring a context.
611 */
612
613#define _CPU_Context_Restart_self( _the_context ) \
614   _CPU_Context_restore( (_the_context) );
615
616/*
617 *  The purpose of this macro is to allow the initial pointer into
618 *  a floating point context area (used to save the floating point
619 *  context) to be at an arbitrary place in the floating point
620 *  context area.
621 *
622 *  This is necessary because some FP units are designed to have
623 *  their context saved as a stack which grows into lower addresses.
624 *  Other FP units can be saved by simply moving registers into offsets
625 *  from the base of the context area.  Finally some FP units provide
626 *  a "dump context" instruction which could fill in from high to low
627 *  or low to high based on the whim of the CPU designers.
628 */
629
630#define _CPU_Context_Fp_start( _base, _offset ) \
631   ( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
632
633/*
634 *  This routine initializes the FP context area passed to it to.
635 *  There are a few standard ways in which to initialize the
636 *  floating point context.  The code included for this macro assumes
637 *  that this is a CPU in which a "initial" FP context was saved into
638 *  _CPU_Null_fp_context and it simply copies it to the destination
639 *  context passed to it.
640 *
641 *  Other models include (1) not doing anything, and (2) putting
642 *  a "null FP status word" in the correct place in the FP context.
643 *  SH1, SH2, SH3 have no FPU, but the SH3e and SH4 have.
644 */
645
646#define _CPU_Context_Initialize_fp( _destination ) \
647  {  }
648
649/* end of Context handler macros */
650
651/* Fatal Error manager macros */
652
653/*
654 * FIXME: Trap32 ???
655 *
656 *  This routine copies _error into a known place -- typically a stack
657 *  location or a register, optionally disables interrupts, and
658 *  invokes a Trap32 Instruction which returns to the breakpoint
659 *  routine of cmon.
660 */
661
662#ifdef BSP_FATAL_HALT
663  /* we manage the fatal error in the board support package */
664  void bsp_fatal_halt( unsigned32 _error);
665#define _CPU_Fatal_halt( _error ) bsp_fatal_halt( _error)
666#else
667#define _CPU_Fatal_halt( _error)\
668{ \
669  asm volatile("mov.l %0,r0"::"m" (_error)); \
670  asm volatile("trapa #34"); \
671}
672#endif
673
674/* end of Fatal Error manager macros */
675
676/* Bitfield handler macros */
677
678/*
679 *  This routine sets _output to the bit number of the first bit
680 *  set in _value.  _value is of CPU dependent type Priority_Bit_map_control.
681 *  This type may be either 16 or 32 bits wide although only the 16
682 *  least significant bits will be used.
683 *
684 *  There are a number of variables in using a "find first bit" type
685 *  instruction.
686 *
687 *    (1) What happens when run on a value of zero?
688 *    (2) Bits may be numbered from MSB to LSB or vice-versa.
689 *    (3) The numbering may be zero or one based.
690 *    (4) The "find first bit" instruction may search from MSB or LSB.
691 *
692 *  RTEMS guarantees that (1) will never happen so it is not a concern.
693 *  (2),(3), (4) are handled by the macros _CPU_Priority_mask() and
694 *  _CPU_Priority_bits_index().  These three form a set of routines
695 *  which must logically operate together.  Bits in the _value are
696 *  set and cleared based on masks built by _CPU_Priority_mask().
697 *  The basic major and minor values calculated by _Priority_Major()
698 *  and _Priority_Minor() are "massaged" by _CPU_Priority_bits_index()
699 *  to properly range between the values returned by the "find first bit"
700 *  instruction.  This makes it possible for _Priority_Get_highest() to
701 *  calculate the major and directly index into the minor table.
702 *  This mapping is necessary to ensure that 0 (a high priority major/minor)
703 *  is the first bit found.
704 *
705 *  This entire "find first bit" and mapping process depends heavily
706 *  on the manner in which a priority is broken into a major and minor
707 *  components with the major being the 4 MSB of a priority and minor
708 *  the 4 LSB.  Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
709 *  priority.  And (15 << 4) + 14 corresponds to priority 254 -- the next
710 *  to the lowest priority.
711 *
712 *  If your CPU does not have a "find first bit" instruction, then
713 *  there are ways to make do without it.  Here are a handful of ways
714 *  to implement this in software:
715 *
716 *    - a series of 16 bit test instructions
717 *    - a "binary search using if's"
718 *    - _number = 0
719 *      if _value > 0x00ff
720 *        _value >>=8
721 *        _number = 8;
722 *
723 *      if _value > 0x0000f
724 *        _value >=8
725 *        _number += 4
726 *
727 *      _number += bit_set_table[ _value ]
728 *
729 *    where bit_set_table[ 16 ] has values which indicate the first
730 *      bit set
731 */
732
733#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
734#define CPU_USE_GENERIC_BITFIELD_DATA TRUE
735
736#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
737
738extern unsigned8 _bit_set_table[];
739
740#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
741  { \
742      _output = 0;\
743      if(_value > 0x00ff) \
744      { _value >>= 8; _output = 8; } \
745      if(_value > 0x000f) \
746        { _output += 4; _value >>= 4; } \
747      _output += _bit_set_table[ _value]; }
748
749#endif
750
751/* end of Bitfield handler macros */
752
753/*
754 *  This routine builds the mask which corresponds to the bit fields
755 *  as searched by _CPU_Bitfield_Find_first_bit().  See the discussion
756 *  for that routine.
757 */
758
759#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
760
761#define _CPU_Priority_Mask( _bit_number ) \
762  ( 1 << (_bit_number) )
763
764#endif
765
766/*
767 *  This routine translates the bit numbers returned by
768 *  _CPU_Bitfield_Find_first_bit() into something suitable for use as
769 *  a major or minor component of a priority.  See the discussion
770 *  for that routine.
771 */
772
773#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
774
775#define _CPU_Priority_bits_index( _priority ) \
776  (_priority)
777
778#endif
779
780/* end of Priority handler macros */
781
782/* functions */
783
784/*
785 *  _CPU_Initialize
786 *
787 *  This routine performs CPU dependent initialization.
788 */
789
790void _CPU_Initialize(
791  rtems_cpu_table  *cpu_table,
792  void      (*thread_dispatch)
793);
794
795/*
796 *  _CPU_ISR_install_raw_handler
797 *
798 *  This routine installs a "raw" interrupt handler directly into the
799 *  processor's vector table.
800 */
801 
802void _CPU_ISR_install_raw_handler(
803  unsigned32  vector,
804  proc_ptr    new_handler,
805  proc_ptr   *old_handler
806);
807
808/*
809 *  _CPU_ISR_install_vector
810 *
811 *  This routine installs an interrupt vector.
812 */
813
814void _CPU_ISR_install_vector(
815  unsigned32  vector,
816  proc_ptr    new_handler,
817  proc_ptr   *old_handler
818);
819
820/*
821 *  _CPU_Install_interrupt_stack
822 *
823 *  This routine installs the hardware interrupt stack pointer.
824 *
825 *  NOTE:  It needs only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK
826 *         is TRUE.
827 */
828
829void _CPU_Install_interrupt_stack( void );
830
831/*
832 *  _CPU_Thread_Idle_body
833 *
834 *  This routine is the CPU dependent IDLE thread body.
835 *
836 *  NOTE:  It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY
837 *         is TRUE.
838 */
839
840void _CPU_Thread_Idle_body( void );
841
842/*
843 *  _CPU_Context_switch
844 *
845 *  This routine switches from the run context to the heir context.
846 */
847
848void _CPU_Context_switch(
849  Context_Control  *run,
850  Context_Control  *heir
851);
852
853/*
854 *  _CPU_Context_restore
855 *
856 *  This routine is generally used only to restart self in an
857 *  efficient manner.  It may simply be a label in _CPU_Context_switch.
858 */
859
860void _CPU_Context_restore(
861  Context_Control *new_context
862);
863
864/*
865 *  _CPU_Context_save_fp
866 *
867 *  This routine saves the floating point context passed to it.
868 */
869
870void _CPU_Context_save_fp(
871  void **fp_context_ptr
872);
873
874/*
875 *  _CPU_Context_restore_fp
876 *
877 *  This routine restores the floating point context passed to it.
878 */
879
880void _CPU_Context_restore_fp(
881  void **fp_context_ptr
882);
883
884
885#ifdef __cplusplus
886}
887#endif
888
889#endif
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