[50cf94da] | 1 | /* |
---|
| 2 | * This include file contains information pertaining to the Hitachi SH |
---|
| 3 | * processor. |
---|
| 4 | * |
---|
| 5 | * NOTE: NOT ALL VALUES HAVE BEEN CHECKED !! |
---|
| 6 | * |
---|
| 7 | * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and |
---|
| 8 | * Bernd Becker (becker@faw.uni-ulm.de) |
---|
| 9 | * |
---|
| 10 | * Based on "iosh7030.h" distributed with Hitachi's EVB's tutorials, which |
---|
| 11 | * contained no copyright notice. |
---|
| 12 | * |
---|
| 13 | * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany |
---|
| 14 | * |
---|
| 15 | * This program is distributed in the hope that it will be useful, |
---|
| 16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
---|
| 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
---|
| 18 | * |
---|
| 19 | * |
---|
| 20 | * COPYRIGHT (c) 1998. |
---|
| 21 | * On-Line Applications Research Corporation (OAR). |
---|
| 22 | * Copyright assigned to U.S. Government, 1994. |
---|
| 23 | * |
---|
| 24 | * The license and distribution terms for this file may be |
---|
| 25 | * found in the file LICENSE in this distribution or at |
---|
| 26 | * http://www.OARcorp.com/rtems/license.html. |
---|
| 27 | * |
---|
| 28 | * $Id$ |
---|
| 29 | */ |
---|
| 30 | |
---|
| 31 | #ifndef __IOSH7030_H |
---|
| 32 | #define __IOSH7030_H |
---|
| 33 | |
---|
| 34 | /* |
---|
| 35 | * After each line is explained whether the access is char short or long. |
---|
| 36 | * The functions read/writeb, w, l, 8, 16, 32 can be found |
---|
| 37 | * in exec/score/cpu/sh/sh_io.h |
---|
| 38 | * |
---|
| 39 | * 8 bit == char ( readb, writeb, read8, write8) |
---|
| 40 | * 16 bit == short ( readw, writew, read16, write16 ) |
---|
| 41 | * 32 bit == long ( readl, writel, read32, write32 ) |
---|
| 42 | */ |
---|
| 43 | |
---|
| 44 | #define SCI0_SMR 0x05fffec0 /* char */ |
---|
| 45 | #define SCI0_BRR 0x05fffec1 /* char */ |
---|
| 46 | #define SCI0_SCR 0x05fffec2 /* char */ |
---|
| 47 | #define SCI0_TDR 0x05fffec3 /* char */ |
---|
| 48 | #define SCI0_SSR 0x05fffec4 /* char */ |
---|
| 49 | #define SCI0_RDR 0x05fffec5 /* char */ |
---|
| 50 | |
---|
| 51 | #define SCI1_SMR 0x05fffec8 /* char */ |
---|
| 52 | #define SCI1_BRR 0x05fffec9 /* char */ |
---|
| 53 | #define SCI1_SCR 0x05fffeca /* char */ |
---|
| 54 | #define SCI1_TDR 0x05fffecb /* char */ |
---|
| 55 | #define SCI1_SSR 0x05fffecc /* char */ |
---|
| 56 | #define SCI1_RDR 0x05fffecd /* char */ |
---|
| 57 | |
---|
| 58 | |
---|
| 59 | #define ADDRAH 0x05fffee0 /* char */ |
---|
| 60 | #define ADDRAL 0x05fffee1 /* char */ |
---|
| 61 | #define ADDRBH 0x05fffee2 /* char */ |
---|
| 62 | #define ADDRBL 0x05fffee3 /* char */ |
---|
| 63 | #define ADDRCH 0x05fffee4 /* char */ |
---|
| 64 | #define ADDRCL 0x05fffee5 /* char */ |
---|
| 65 | #define ADDRDH 0x05fffee6 /* char */ |
---|
| 66 | #define ADDRDL 0x05fffee7 /* char */ |
---|
| 67 | #define AD_DRA 0x05fffee0 /* short */ |
---|
| 68 | #define AD_DRB 0x05fffee2 /* short */ |
---|
| 69 | #define AD_DRC 0x05fffee4 /* short */ |
---|
| 70 | #define AD_DRD 0x05fffee6 /* short */ |
---|
| 71 | #define ADCSR 0x05fffee8 /* char */ |
---|
| 72 | #define ADCR 0x05fffee9 /* char */ |
---|
| 73 | |
---|
| 74 | /*ITU SHARED*/ |
---|
| 75 | #define ITU_TSTR 0x05ffff00 /* char */ |
---|
| 76 | #define ITU_TSNC 0x05ffff01 /* char */ |
---|
| 77 | #define ITU_TMDR 0x05ffff02 /* char */ |
---|
| 78 | #define ITU_TFCR 0x05ffff03 /* char */ |
---|
| 79 | |
---|
| 80 | /*ITU CHANNEL 0*/ |
---|
| 81 | #define ITU_TCR0 0x05ffff04 /* char */ |
---|
| 82 | #define ITU_TIOR0 0x05ffff05 /* char */ |
---|
| 83 | #define ITU_TIER0 0x05ffff06 /* char */ |
---|
| 84 | #define ITU_TSR0 0x05ffff07 /* char */ |
---|
| 85 | #define ITU_TCNT0 0x05ffff08 /* short */ |
---|
| 86 | #define ITU_GRA0 0x05ffff0a /* short */ |
---|
| 87 | #define ITU_GRB0 0x05ffff0c /* short */ |
---|
| 88 | |
---|
| 89 | /*ITU CHANNEL 1*/ |
---|
| 90 | #define ITU_TCR1 0x05ffff0E /* char */ |
---|
| 91 | #define ITU_TIOR1 0x05ffff0F /* char */ |
---|
| 92 | #define ITU_TIER1 0x05ffff10 /* char */ |
---|
| 93 | #define ITU_TSR1 0x05ffff11 /* char */ |
---|
| 94 | #define ITU_TCNT1 0x05ffff12 /* short */ |
---|
| 95 | #define ITU_GRA1 0x05ffff14 /* short */ |
---|
| 96 | #define ITU_GRB1 0x05ffff16 /* short */ |
---|
| 97 | |
---|
| 98 | |
---|
| 99 | /*ITU CHANNEL 2*/ |
---|
| 100 | #define ITU_TCR2 0x05ffff18 /* char */ |
---|
| 101 | #define ITU_TIOR2 0x05ffff19 /* char */ |
---|
| 102 | #define ITU_TIER2 0x05ffff1A /* char */ |
---|
| 103 | #define ITU_TSR2 0x05ffff1B /* char */ |
---|
| 104 | #define ITU_TCNT2 0x05ffff1C /* short */ |
---|
| 105 | #define ITU_GRA2 0x05ffff1E /* short */ |
---|
| 106 | #define ITU_GRB2 0x05ffff20 /* short */ |
---|
| 107 | |
---|
| 108 | /*ITU CHANNEL 3*/ |
---|
| 109 | #define ITU_TCR3 0x05ffff22 /* char */ |
---|
| 110 | #define ITU_TIOR3 0x05ffff23 /* char */ |
---|
| 111 | #define ITU_TIER3 0x05ffff24 /* char */ |
---|
| 112 | #define ITU_TSR3 0x05ffff25 /* char */ |
---|
| 113 | #define ITU_TCNT3 0x05ffff26 /* short */ |
---|
| 114 | #define ITU_GRA3 0x05ffff28 /* short */ |
---|
| 115 | #define ITU_GRB3 0x05ffff2A /* short */ |
---|
| 116 | #define ITU_BRA3 0x05ffff2C /* short */ |
---|
| 117 | #define ITU_BRB3 0x05ffff2E /* short */ |
---|
| 118 | |
---|
| 119 | /*ITU CHANNELS 0-4 SHARED*/ |
---|
| 120 | #define ITU_TOCR 0x05ffff31 /* char */ |
---|
| 121 | |
---|
| 122 | /*ITU CHANNEL 4*/ |
---|
| 123 | #define ITU_TCR4 0x05ffff32 /* char */ |
---|
| 124 | #define ITU_TIOR4 0x05ffff33 /* char */ |
---|
| 125 | #define ITU_TIER4 0x05ffff34 /* char */ |
---|
| 126 | #define ITU_TSR4 0x05ffff35 /* char */ |
---|
| 127 | #define ITU_TCNT4 0x05ffff36 /* short */ |
---|
| 128 | #define ITU_GRA4 0x05ffff38 /* short */ |
---|
| 129 | #define ITU_GRB4 0x05ffff3A /* short */ |
---|
| 130 | #define ITU_BRA4 0x05ffff3C /* short */ |
---|
| 131 | #define ITU_BRB4 0x05ffff3E /* short */ |
---|
| 132 | |
---|
| 133 | /*DMAC CHANNELS 0-3 SHARED*/ |
---|
| 134 | #define DMAOR 0x05ffff48 /* short */ |
---|
| 135 | |
---|
| 136 | /*DMAC CHANNEL 0*/ |
---|
| 137 | #define DMA_SAR0 0x05ffff40 /* long */ |
---|
| 138 | #define DMA_DAR0 0x05ffff44 /* long */ |
---|
| 139 | #define DMA_TCR0 0x05ffff4a /* short */ |
---|
| 140 | #define DMA_CHCR0 0x05ffff4e /* short */ |
---|
| 141 | |
---|
| 142 | /*DMAC CHANNEL 1*/ |
---|
| 143 | #define DMA_SAR1 0x05ffff50 /* long */ |
---|
| 144 | #define DMA_DAR1 0x05ffff54 /* long */ |
---|
| 145 | #define DMA_TCR1 0x05fffF5a /* short */ |
---|
| 146 | #define DMA_CHCR1 0x05ffff5e /* short */ |
---|
| 147 | |
---|
| 148 | /*DMAC CHANNEL 3*/ |
---|
| 149 | #define DMA_SAR3 0x05ffff60 /* long */ |
---|
| 150 | #define DMA_DAR3 0x05ffff64 /* long */ |
---|
| 151 | #define DMA_TCR3 0x05fffF6a /* short */ |
---|
| 152 | #define DMA_CHCR3 0x05ffff6e /* short */ |
---|
| 153 | |
---|
| 154 | /*DMAC CHANNEL 4*/ |
---|
| 155 | #define DMA_SAR4 0x05ffff70 /* long */ |
---|
| 156 | #define DMA_DAR4 0x05ffff74 /* long */ |
---|
| 157 | #define DMA_TCR4 0x05fffF7a /* short */ |
---|
| 158 | #define DMA_CHCR4 0x05ffff7e /* short */ |
---|
| 159 | |
---|
| 160 | /*INTC*/ |
---|
| 161 | #define INTC_IPRA 0x05ffff84 /* short */ |
---|
| 162 | #define INTC_IPRB 0x05ffff86 /* short */ |
---|
| 163 | #define INTC_IPRC 0x05ffff88 /* short */ |
---|
| 164 | #define INTC_IPRD 0x05ffff8A /* short */ |
---|
| 165 | #define INTC_IPRE 0x05ffff8C /* short */ |
---|
| 166 | #define INTC_ICR 0x05ffff8E /* short */ |
---|
| 167 | |
---|
| 168 | /*UBC*/ |
---|
| 169 | #define UBC_BARH 0x05ffff90 /* short */ |
---|
| 170 | #define UBC_BARL 0x05ffff92 /* short */ |
---|
| 171 | #define UBC_BAMRH 0x05ffff94 /* short */ |
---|
| 172 | #define UBC_BAMRL 0x05ffff96 /* short */ |
---|
| 173 | #define UBC_BBR 0x05ffff98 /* short */ |
---|
| 174 | |
---|
| 175 | /*BSC*/ |
---|
| 176 | #define BSC_BCR 0x05ffffA0 /* short */ |
---|
| 177 | #define BSC_WCR1 0x05ffffA2 /* short */ |
---|
| 178 | #define BSC_WCR2 0x05ffffA4 /* short */ |
---|
| 179 | #define BSC_WCR3 0x05ffffA6 /* short */ |
---|
| 180 | #define BSC_DCR 0x05ffffA8 /* short */ |
---|
| 181 | #define BSC_PCR 0x05ffffAA /* short */ |
---|
| 182 | #define BSC_RCR 0x05ffffAC /* short */ |
---|
| 183 | #define BSC_RTCSR 0x05ffffAE /* short */ |
---|
| 184 | #define BSC_RTCNT 0x05ffffB0 /* short */ |
---|
| 185 | #define BSC_RTCOR 0x05ffffB2 /* short */ |
---|
| 186 | |
---|
| 187 | /*WDT*/ |
---|
| 188 | #define WDT_TCSR 0x05ffffB8 /* char */ |
---|
| 189 | #define WDT_TCNT 0x05ffffB9 /* char */ |
---|
| 190 | #define WDT_RSTCSR 0x05ffffBB /* char */ |
---|
| 191 | |
---|
| 192 | /*POWER DOWN STATE*/ |
---|
| 193 | #define PDT_SBYCR 0x05ffffBC /* char */ |
---|
| 194 | |
---|
| 195 | /*PORT A*/ |
---|
| 196 | #define PADR 0x05ffffC0 /* short */ |
---|
| 197 | |
---|
| 198 | /*PORT B*/ |
---|
| 199 | #define PBDR 0x05ffffC2 /* short */ |
---|
| 200 | |
---|
| 201 | /*PORT C*/ |
---|
| 202 | #define PCDR 0x05ffffD0 /* short */ |
---|
| 203 | |
---|
| 204 | /*PFC*/ |
---|
| 205 | #define PFC_PAIOR 0x05ffffC4 /* short */ |
---|
| 206 | #define PFC_PBIOR 0x05ffffC6 /* short */ |
---|
| 207 | #define PFC_PACR1 0x05ffffC8 /* short */ |
---|
| 208 | #define PFC_PACR2 0x05ffffCA /* short */ |
---|
| 209 | #define PFC_PBCR1 0x05ffffCC /* short */ |
---|
| 210 | #define PFC_PBCR2 0x05ffffCE /* short */ |
---|
| 211 | #define PFC_CASCR 0x05ffffEE /* short */ |
---|
| 212 | |
---|
| 213 | /*TPC*/ |
---|
| 214 | #define TPC_TPMR 0x05ffffF0 /* short */ |
---|
| 215 | #define TPC_TPCR 0x05ffffF1 /* short */ |
---|
| 216 | #define TPC_NDERH 0x05ffffF2 /* short */ |
---|
| 217 | #define TPC_NDERL 0x05ffffF3 /* short */ |
---|
| 218 | #define TPC_NDRB 0x05ffffF4 /* char */ |
---|
| 219 | #define TPC_NDRA 0x05ffff5F /* char */ |
---|
| 220 | #define TPC_NDRB1 0x05ffffF6 /* char */ |
---|
| 221 | #define TPC_NDRA1 0x05ffffF7 /* char */ |
---|
| 222 | |
---|
| 223 | #endif |
---|