source: rtems/c/src/exec/score/cpu/sh/cpu.c @ 7d953c2

4.104.114.84.95
Last change on this file since 7d953c2 was 7d953c2, checked in by Joel Sherrill <joel.sherrill@…>, on 10/12/01 at 17:46:47

2001-10-12 Joel Sherrill <joel@…>

  • asm.h, cpu.c, rtems.c, rtems/score/cpu.h, rtems/score/sh.h, rtems/score/sh_io.h, rtems/score/shtypes.h: Consistency changes and made sure there were no includes from the libcpu tree.
  • Property mode set to 100644
File size: 5.7 KB
Line 
1/*
2 *  This file contains information pertaining to the Hitachi SH
3 *  processor.
4 *
5 *  Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
6 *           Bernd Becker (becker@faw.uni-ulm.de)
7 *
8 *  COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
9 *
10 *  This program is distributed in the hope that it will be useful,
11 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
12 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
13 *
14 *
15 *  COPYRIGHT (c) 1998-2001.
16 *  On-Line Applications Research Corporation (OAR).
17 *
18 *  The license and distribution terms for this file may be
19 *  found in the file LICENSE in this distribution or at
20 *  http://www.OARcorp.com/rtems/license.html.
21 *
22 *  $Id$
23 */
24 
25#include <rtems/system.h>
26#include <rtems/score/isr.h>
27#include <rtems/score/sh_io.h>
28#include <rtems/score/cpu.h>
29#include <rtems/score/sh.h>
30
31/* referenced in start.S */
32extern proc_ptr vectab[] ;
33
34proc_ptr vectab[256] ;
35
36extern proc_ptr _Hardware_isr_Table[];
37
38/*  _CPU_Initialize
39 *
40 *  This routine performs processor dependent initialization.
41 *
42 *  INPUT PARAMETERS:
43 *    cpu_table       - CPU table to initialize
44 *    thread_dispatch - address of disptaching routine
45 */
46
47
48void _CPU_Initialize(
49  rtems_cpu_table  *cpu_table,
50  void      (*thread_dispatch)      /* ignored on this CPU */
51)
52{
53  register unsigned32 level = 0;
54
55  /*
56   *  The thread_dispatch argument is the address of the entry point
57   *  for the routine called at the end of an ISR once it has been
58   *  decided a context switch is necessary.  On some compilation
59   *  systems it is difficult to call a high-level language routine
60   *  from assembly.  This allows us to trick these systems.
61   *
62   *  If you encounter this problem save the entry point in a CPU
63   *  dependent variable.
64   */
65
66  _CPU_Thread_dispatch_pointer = thread_dispatch;
67
68  /*
69   *  If there is not an easy way to initialize the FP context
70   *  during Context_Initialize, then it is usually easier to
71   *  save an "uninitialized" FP context here and copy it to
72   *  the task's during Context_Initialize.
73   */
74
75  /* FP context initialization support goes here */
76  /* FIXME: When not to use SH4_FPSCR_PR ? */
77#ifdef __SH4__
78  _CPU_Null_fp_context.fpscr = SH4_FPSCR_DN | SH4_FPSCR_RM | SH4_FPSCR_PR;
79#endif
80#ifdef __SH3E__
81  /* FIXME: Wild guess :) */
82  _CPU_Null_fp_context.fpscr = SH4_FPSCR_DN | SH4_FPSCR_RM;
83#endif
84
85  _CPU_Table = *cpu_table;
86
87  /* enable interrupts */
88  _CPU_ISR_Set_level( level);
89}
90
91/*PAGE
92 *
93 *  _CPU_ISR_Get_level
94 */
95 
96unsigned32 _CPU_ISR_Get_level( void )
97{
98  /*
99   *  This routine returns the current interrupt level.
100   */
101
102  register unsigned32 _mask ;
103 
104  sh_get_interrupt_level( _mask );
105 
106  return ( _mask);
107}
108
109/*PAGE
110 *
111 *  _CPU_ISR_install_raw_handler
112 */
113 
114void _CPU_ISR_install_raw_handler(
115  unsigned32  vector,
116  proc_ptr    new_handler,
117  proc_ptr   *old_handler
118)
119{
120  /*
121   *  This is where we install the interrupt handler into the "raw" interrupt
122   *  table used by the CPU to dispatch interrupt handlers.
123   */
124  volatile proc_ptr     *vbr ;
125
126#if SH_PARANOID_ISR 
127  unsigned32            level ;
128
129  sh_disable_interrupts( level );
130#endif   
131
132  /* get vbr */
133  asm ( "stc vbr,%0" : "=r" (vbr) );
134
135  *old_handler = vbr[vector] ;
136  vbr[vector]  = new_handler ;
137
138#if SH_PARANOID_ISR
139  sh_enable_interrupts( level );
140#endif
141}
142
143
144/*PAGE
145 *
146 *  _CPU_ISR_install_vector
147 *
148 *  This kernel routine installs the RTEMS handler for the
149 *  specified vector.
150 *
151 *  Input parameters:
152 *    vector      - interrupt vector number
153 *    old_handler - former ISR for this vector number
154 *    new_handler - replacement ISR for this vector number
155 *
156 *  Output parameters:  NONE
157 *
158 */
159
160#if defined(sh1) || defined(sh2)
161void _CPU_ISR_install_vector(
162  unsigned32  vector,
163  proc_ptr    new_handler,
164  proc_ptr   *old_handler
165)
166{
167   proc_ptr ignored ;
168#if 0
169   if(( vector <= 113) && ( vector >= 11))
170     {
171#endif
172       *old_handler = _ISR_Vector_table[ vector ];
173
174       /*
175        *  If the interrupt vector table is a table of pointer to isr entry
176        *  points, then we need to install the appropriate RTEMS interrupt
177        *  handler for this vector number.
178        */
179       _CPU_ISR_install_raw_handler(vector,
180                                    _Hardware_isr_Table[vector],
181                                    &ignored );
182
183       /*
184        *  We put the actual user ISR address in '_ISR_Vector_table'. 
185        *  This will be used by __ISR_Handler so the user gets control.
186        */
187
188       _ISR_Vector_table[ vector ] = new_handler;
189#if 0
190     }
191#endif
192}
193
194/*PAGE
195 *
196 *  _CPU_Thread_Idle_body
197 *
198 *  NOTES:
199 *
200 *  1. This is the same as the regular CPU independent algorithm.
201 *
202 *  2. If you implement this using a "halt", "idle", or "shutdown"
203 *     instruction, then don't forget to put it in an infinite loop.
204 *
205 *  3. Be warned. Some processors with onboard DMA have been known
206 *     to stop the DMA if the CPU were put in IDLE mode.  This might
207 *     also be a problem with other on-chip peripherals.  So use this
208 *     hook with caution.
209 */
210
211#if (CPU_PROVIDES_IDLE_THREAD_BODY == TRUE)
212void _CPU_Thread_Idle_body( void )
213{
214
215  for( ; ; )
216    {
217      asm volatile("nop");
218    }
219    /* insert your "halt" instruction here */ ;
220}
221#endif
222
223#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
224
225unsigned8 _bit_set_table[16] =
226  { 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 2, 2, 1,0};
227
228
229#endif
230
231void _CPU_Context_Initialize(
232  Context_Control       *_the_context,
233  void                  *_stack_base,
234  unsigned32            _size,
235  unsigned32            _isr,
236  void  (*_entry_point)(void),
237  int                   _is_fp )
238{
239  _the_context->r15 = (unsigned32*) ((unsigned32) (_stack_base) + (_size) );
240#if defined(__sh1__) || defined(__sh2__)
241  _the_context->sr  = (_isr << 4) & 0x00f0 ;
242#else
243  _the_context->sr  = SH4_SR_MD | ((_isr << 4) & 0x00f0);
244#endif
245  _the_context->pr  = (unsigned32*) _entry_point ;
246
247
248#if 0 && SH_HAS_FPU
249   /* Disable FPU if it is non-fp task */
250  if(!_is_fp)
251    _the_context->sr |= SH4_SR_FD;
252#endif
253}
254
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