[50cf94da] | 1 | /* |
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| 2 | * This file contains information pertaining to the Hitachi SH |
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| 3 | * processor. |
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| 4 | * |
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| 5 | * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and |
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| 6 | * Bernd Becker (becker@faw.uni-ulm.de) |
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| 7 | * |
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| 8 | * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany |
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| 9 | * |
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| 10 | * This program is distributed in the hope that it will be useful, |
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| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
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| 13 | * |
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| 14 | * |
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| 15 | * COPYRIGHT (c) 1998. |
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| 16 | * On-Line Applications Research Corporation (OAR). |
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| 17 | * Copyright assigned to U.S. Government, 1994. |
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| 18 | * |
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| 19 | * The license and distribution terms for this file may be |
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| 20 | * found in the file LICENSE in this distribution or at |
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| 21 | * http://www.OARcorp.com/rtems/license.html. |
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| 22 | * |
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| 23 | * $Id$ |
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| 24 | */ |
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| 25 | |
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| 26 | #include <rtems/system.h> |
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| 27 | #include <rtems/score/isr.h> |
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| 28 | #include <rtems/score/sh_io.h> |
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| 29 | #include <rtems/score/cpu.h> |
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| 30 | #include <rtems/score/sh.h> |
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| 31 | |
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| 32 | |
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[4a238002] | 33 | /* referenced in start.S */ |
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[50cf94da] | 34 | extern proc_ptr vectab[] ; |
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| 35 | |
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| 36 | proc_ptr vectab[256] ; |
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| 37 | |
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| 38 | extern proc_ptr _Hardware_isr_Table[]; |
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| 39 | |
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| 40 | /* _CPU_Initialize |
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| 41 | * |
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| 42 | * This routine performs processor dependent initialization. |
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| 43 | * |
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| 44 | * INPUT PARAMETERS: |
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| 45 | * cpu_table - CPU table to initialize |
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| 46 | * thread_dispatch - address of disptaching routine |
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| 47 | */ |
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| 48 | |
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| 49 | |
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| 50 | void _CPU_Initialize( |
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| 51 | rtems_cpu_table *cpu_table, |
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| 52 | void (*thread_dispatch) /* ignored on this CPU */ |
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| 53 | ) |
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| 54 | { |
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| 55 | register unsigned32 level = 0; |
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| 56 | |
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| 57 | /* |
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| 58 | * The thread_dispatch argument is the address of the entry point |
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| 59 | * for the routine called at the end of an ISR once it has been |
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| 60 | * decided a context switch is necessary. On some compilation |
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| 61 | * systems it is difficult to call a high-level language routine |
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| 62 | * from assembly. This allows us to trick these systems. |
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| 63 | * |
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| 64 | * If you encounter this problem save the entry point in a CPU |
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| 65 | * dependent variable. |
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| 66 | */ |
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| 67 | |
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| 68 | _CPU_Thread_dispatch_pointer = thread_dispatch; |
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| 69 | |
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| 70 | /* |
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| 71 | * If there is not an easy way to initialize the FP context |
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| 72 | * during Context_Initialize, then it is usually easier to |
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| 73 | * save an "uninitialized" FP context here and copy it to |
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| 74 | * the task's during Context_Initialize. |
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| 75 | */ |
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| 76 | |
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| 77 | /* FP context initialization support goes here */ |
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| 78 | |
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| 79 | _CPU_Table = *cpu_table; |
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| 80 | |
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| 81 | /* enable interrupts */ |
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| 82 | _CPU_ISR_Set_level( level); |
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| 83 | } |
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| 84 | |
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| 85 | /*PAGE |
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| 86 | * |
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| 87 | * _CPU_ISR_Get_level |
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| 88 | */ |
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| 89 | |
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| 90 | unsigned32 _CPU_ISR_Get_level( void ) |
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| 91 | { |
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| 92 | /* |
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| 93 | * This routine returns the current interrupt level. |
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| 94 | */ |
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| 95 | |
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| 96 | register unsigned32 _mask ; |
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| 97 | |
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| 98 | sh_get_interrupt_level( _mask ); |
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| 99 | |
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| 100 | return ( _mask); |
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| 101 | } |
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| 102 | |
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| 103 | /*PAGE |
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| 104 | * |
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| 105 | * _CPU_ISR_install_raw_handler |
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| 106 | */ |
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| 107 | |
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| 108 | void _CPU_ISR_install_raw_handler( |
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| 109 | unsigned32 vector, |
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| 110 | proc_ptr new_handler, |
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| 111 | proc_ptr *old_handler |
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| 112 | ) |
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| 113 | { |
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| 114 | /* |
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| 115 | * This is where we install the interrupt handler into the "raw" interrupt |
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| 116 | * table used by the CPU to dispatch interrupt handlers. |
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| 117 | */ |
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| 118 | volatile proc_ptr *vbr ; |
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| 119 | |
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| 120 | #if SH_PARANOID_ISR |
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| 121 | unsigned32 level ; |
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| 122 | |
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| 123 | sh_disable_interrupts( level ); |
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| 124 | #endif |
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| 125 | |
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| 126 | /* get vbr */ |
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| 127 | asm ( "stc vbr,%0" : "=r" (vbr) ); |
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| 128 | |
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| 129 | *old_handler = vbr[vector] ; |
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| 130 | vbr[vector] = new_handler ; |
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| 131 | |
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| 132 | #if SH_PARANOID_ISR |
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| 133 | sh_enable_interrupts( level ); |
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| 134 | #endif |
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| 135 | } |
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| 136 | |
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| 137 | |
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| 138 | /*PAGE |
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| 139 | * |
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| 140 | * _CPU_ISR_install_vector |
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| 141 | * |
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| 142 | * This kernel routine installs the RTEMS handler for the |
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| 143 | * specified vector. |
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| 144 | * |
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| 145 | * Input parameters: |
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| 146 | * vector - interrupt vector number |
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| 147 | * old_handler - former ISR for this vector number |
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| 148 | * new_handler - replacement ISR for this vector number |
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| 149 | * |
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| 150 | * Output parameters: NONE |
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| 151 | * |
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| 152 | */ |
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| 153 | |
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| 154 | void _CPU_ISR_install_vector( |
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| 155 | unsigned32 vector, |
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| 156 | proc_ptr new_handler, |
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| 157 | proc_ptr *old_handler |
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| 158 | ) |
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| 159 | { |
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| 160 | proc_ptr ignored ; |
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[f30a0ca9] | 161 | #if 0 |
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[50cf94da] | 162 | if(( vector <= 113) && ( vector >= 11)) |
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| 163 | { |
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[f30a0ca9] | 164 | #endif |
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[50cf94da] | 165 | *old_handler = _ISR_Vector_table[ vector ]; |
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| 166 | |
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| 167 | /* |
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| 168 | * If the interrupt vector table is a table of pointer to isr entry |
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| 169 | * points, then we need to install the appropriate RTEMS interrupt |
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| 170 | * handler for this vector number. |
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| 171 | */ |
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| 172 | _CPU_ISR_install_raw_handler(vector, |
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| 173 | _Hardware_isr_Table[vector], |
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| 174 | &ignored ); |
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| 175 | |
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| 176 | /* |
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| 177 | * We put the actual user ISR address in '_ISR_Vector_table'. |
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| 178 | * This will be used by __ISR_Handler so the user gets control. |
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| 179 | */ |
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| 180 | |
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| 181 | _ISR_Vector_table[ vector ] = new_handler; |
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[f30a0ca9] | 182 | #if 0 |
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[50cf94da] | 183 | } |
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[f30a0ca9] | 184 | #endif |
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[50cf94da] | 185 | } |
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| 186 | |
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| 187 | /*PAGE |
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| 188 | * |
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| 189 | * _CPU_Thread_Idle_body |
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| 190 | * |
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| 191 | * NOTES: |
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| 192 | * |
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| 193 | * 1. This is the same as the regular CPU independent algorithm. |
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| 194 | * |
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| 195 | * 2. If you implement this using a "halt", "idle", or "shutdown" |
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| 196 | * instruction, then don't forget to put it in an infinite loop. |
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| 197 | * |
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| 198 | * 3. Be warned. Some processors with onboard DMA have been known |
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| 199 | * to stop the DMA if the CPU were put in IDLE mode. This might |
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| 200 | * also be a problem with other on-chip peripherals. So use this |
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| 201 | * hook with caution. |
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| 202 | */ |
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| 203 | |
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| 204 | #if (CPU_PROVIDES_IDLE_THREAD_BODY == TRUE) |
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| 205 | void _CPU_Thread_Idle_body( void ) |
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| 206 | { |
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| 207 | |
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| 208 | for( ; ; ) |
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| 209 | { |
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| 210 | asm volatile("nop"); |
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| 211 | } |
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| 212 | /* insert your "halt" instruction here */ ; |
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| 213 | } |
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| 214 | #endif |
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| 215 | |
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| 216 | #if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) |
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| 217 | |
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| 218 | unsigned8 _bit_set_table[16] = |
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| 219 | { 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 2, 2, 1,0}; |
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| 220 | |
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| 221 | |
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| 222 | #endif |
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| 223 | |
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| 224 | void _CPU_Context_Initialize( |
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| 225 | Context_Control *_the_context, |
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| 226 | void *_stack_base, |
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| 227 | unsigned32 _size, |
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| 228 | unsigned32 _isr, |
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| 229 | void (*_entry_point)(void), |
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| 230 | int _is_fp ) |
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| 231 | { |
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| 232 | _the_context->r15 = (unsigned32*) ((unsigned32) (_stack_base) + (_size) ); |
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| 233 | _the_context->sr = (_isr << 4) & 0x00f0 ; |
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| 234 | _the_context->pr = (unsigned32*) _entry_point ; |
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| 235 | } |
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