source: rtems/c/src/exec/score/cpu/powerpc/shared/ppc.h @ a3f5b6b

Last change on this file since a3f5b6b was a3f5b6b, checked in by Joel Sherrill <joel.sherrill@…>, on 05/28/00 at 20:14:45

Added a special CPU model of "rtems_multilib". This is the beginnings
of an experiment to determine what it will take to multilib most of
RTEMS per GNU multilib conventions. It is thought that only
interrupt processing and IO are not multlib-able. This means that
a BSP Kit should include IRQ processing from score/cpu, all peripheral
support (header files from score/cpu, libchip, and libcpu), and the
BSPs themselves. The rest of RTEMS should be multlib-able. But to do
this, all RTEMS CPU model feature flags must be derivable from gcc
cpp predefines. By configuring the bare bsp with the rtems_multilib
CPU model, you can try any combination of CPU CFLAGS and see well how the
logic in that section of the <CPU>.h works. Once all CPU multilib
variations can be built, then RTEMS proper can be multilib'ed and
separated from the BSPs.
  • Property mode set to 100644
File size: 19.7 KB
Line 
1/*  ppc.h
2 *
3 *  This file contains definitions for the IBM/Motorola PowerPC
4 *  family members.
5 *
6 *  Author:     Andrew Bray <andy@i-cubed.co.uk>
7 *
8 *  COPYRIGHT (c) 1995 by i-cubed ltd.
9 *
10 *  MPC860 support code was added by Jay Monkman <jmonkman@frasca.com>
11 *
12 *  To anyone who acknowledges that this file is provided "AS IS"
13 *  without any express or implied warranty:
14 *      permission to use, copy, modify, and distribute this file
15 *      for any purpose is hereby granted without fee, provided that
16 *      the above copyright notice and this notice appears in all
17 *      copies, and that the name of i-cubed limited not be used in
18 *      advertising or publicity pertaining to distribution of the
19 *      software without specific, written prior permission.
20 *      i-cubed limited makes no representations about the suitability
21 *      of this software for any purpose.
22 *
23 *  Derived from c/src/exec/cpu/no_cpu/no_cpu.h:
24 *
25 *  COPYRIGHT (c) 1989-1997.
26 *  On-Line Applications Research Corporation (OAR).
27 *
28 *  The license and distribution terms for this file may in
29 *  the file LICENSE in this distribution or at
30 *  http://www.OARcorp.com/rtems/license.html.
31 *
32 *
33 * Note:
34 *      This file is included by both C and assembler code ( -DASM )
35 *
36 *  $Id$
37 */
38
39
40#ifndef _INCLUDE_PPC_h
41#define _INCLUDE_PPC_h
42
43#ifdef __cplusplus
44extern "C" {
45#endif
46
47/*
48 *  Define the name of the CPU family.
49 */
50
51#define CPU_NAME "PowerPC"
52
53/*
54 *  This file contains the information required to build
55 *  RTEMS for a particular member of the PowerPC family.  It does
56 *  this by setting variables to indicate which implementation
57 *  dependent features are present in a particular member
58 *  of the family.
59 *
60 *  The following architectural feature definitions are defaulted
61 *  unless specifically set by the model definition:
62 *
63 *    + PPC_DEBUG_MODEL          - PPC_DEBUG_MODEL_STANDARD
64 *    + PPC_INTERRUPT_MAX        - 16
65 *    + PPC_CACHE_ALIGNMENT      - 32
66 *    + PPC_LOW_POWER_MODE       - PPC_LOW_POWER_MODE_NONE
67 *    + PPC_HAS_EXCEPTION_PREFIX - 1
68 *    + PPC_HAS_FPU              - 1
69 *    + PPC_HAS_DOUBLE           - 1 if PPC_HAS_FPU,
70 *                               - 0 otherwise
71 *    + PPC_USE_MULTIPLE         - 0
72 */
73 
74/*
75 *  Define the debugging assistance models found in the PPC family.
76 *
77 *  Standard:         single step and branch trace
78 *  Single Step Only: single step only
79 *  IBM 4xx:          debug exception
80 */
81
82#define PPC_DEBUG_MODEL_STANDARD         1
83#define PPC_DEBUG_MODEL_SINGLE_STEP_ONLY 2
84#define PPC_DEBUG_MODEL_IBM4xx           3
85
86/*
87 *  Define the low power mode models
88 *
89 *  Standard:   as defined for 603e
90 *  Nap Mode:   nap mode only (604)
91 *  XXX 403GB, 603, 603e, 604, 821
92 */
93
94#define PPC_LOW_POWER_MODE_NONE      0
95#define PPC_LOW_POWER_MODE_STANDARD  1
96
97#if defined(rtems_multilib)
98/*
99 *  Figure out all CPU Model Feature Flags based upon compiler
100 *  predefines.
101 */
102
103#define CPU_MODEL_NAME           "rtems_multilib"
104#define PPC_ALIGNMENT            4 
105#define PPC_CACHE_ALIGNMENT      16
106#define PPC_HAS_RFCI             1
107#define PPC_HAS_FPU              0
108#define PPC_USE_MULTIPLE         1
109#define PPC_I_CACHE              2048
110#define PPC_D_CACHE              1024
111#define PPC_DEBUG_MODEL          PPC_DEBUG_MODEL_STANDARD
112#define PPC_HAS_EXCEPTION_PREFIX 0
113#define PPC_HAS_EVPR             0
114#define PPC_INTERRUPT_MAX        16
115#define PPC_LOW_POWER_MODE       PPC_LOW_POWER_MODE_STANDARD
116#define PPC_HAS_DOUBLE           0
117
118#elif defined(ppc403)
119/*
120 *  IBM 403
121 *
122 *  Developed for 403GA.  Book checked for 403GB.
123 *
124 *  Does not have user mode.
125 */
126 
127#define CPU_MODEL_NAME "PowerPC 403"
128#define PPC_ALIGNMENT           4 
129#define PPC_CACHE_ALIGNMENT     16
130#define PPC_HAS_RFCI            1
131#define PPC_HAS_FPU             0
132#define PPC_USE_MULTIPLE        1
133#define PPC_I_CACHE             2048
134#define PPC_D_CACHE             1024
135
136#define PPC_DEBUG_MODEL          PPC_DEBUG_MODEL_IBM4xx
137#define PPC_HAS_EXCEPTION_PREFIX 0
138#define PPC_HAS_EVPR             1
139
140
141#elif defined(mpc505) || defined(mpc509)
142/*
143 *  Submitted by Sergei Organov <osv@Javad.RU> as a patch against
144 *  3.6.0 long after 4.0 was released.   This is just an attempt
145 *  to get the setting correct.
146 */
147
148#define CPU_MODEL_NAME  "PowerPC 505/509"
149
150#define PPC_ALIGNMENT           4
151#define PPC_CACHE_ALIGNMENT     16
152#define PPC_I_CACHE             4096
153#define PPC_D_CACHE             0
154
155
156#elif defined(ppc601)
157
158/*
159 *  Submitted with original port -- book checked only.
160 */
161 
162#define CPU_MODEL_NAME  "PowerPC 601"
163
164#define PPC_ALIGNMENT           8
165#define PPC_USE_MULTIPLE        1
166#define PPC_I_CACHE             0
167#define PPC_D_CACHE             32768
168
169#define PPC_DEBUG_MODEL PPC_DEBUG_MODEL_SINGLE_STEP_ONLY
170
171#elif defined(ppc602)
172/*
173 *  Submitted with original port -- book checked only.
174 */
175 
176#define CPU_MODEL_NAME  "PowerPC 602"
177
178#define PPC_ALIGNMENT           4
179#define PPC_HAS_DOUBLE          0
180#define PPC_I_CACHE             4096
181#define PPC_D_CACHE             4096
182
183#elif defined(ppc603)
184/*
185 *  Submitted with original port -- book checked only.
186 */
187 
188#define CPU_MODEL_NAME  "PowerPC 603"
189
190#define PPC_ALIGNMENT           8
191#define PPC_I_CACHE             8192
192#define PPC_D_CACHE             8192
193
194#elif defined(ppc603e)
195 
196#define CPU_MODEL_NAME  "PowerPC 603e"
197/*
198 *  Submitted with original port.
199 *
200 *  Known to work on real hardware.
201 */
202
203#define PPC_ALIGNMENT           8
204#define PPC_I_CACHE             16384
205#define PPC_D_CACHE             16384
206
207#define PPC_LOW_POWER_MODE PPC_LOW_POWER_MODE_STANDARD
208
209#elif defined(mpc604)
210/*
211 *  Submitted with original port -- book checked only.
212 */
213 
214#define CPU_MODEL_NAME  "PowerPC 604"
215
216#define PPC_ALIGNMENT           8
217#define PPC_I_CACHE             16384
218#define PPC_D_CACHE             16384
219 
220#elif defined(mpc860)
221/*
222 *  Added by Jay Monkman (jmonkman@frasca.com) 6/28/98
223 */
224#define CPU_MODEL_NAME  "PowerPC MPC860"
225
226#define PPC_ALIGNMENT           4
227#define PPC_I_CACHE             4096
228#define PPC_D_CACHE             4096
229#define PPC_CACHE_ALIGNMENT     16
230#define PPC_INTERRUPT_MAX       71
231#define PPC_HAS_FPU             0
232#define PPC_HAS_DOUBLE          0
233#define PPC_USE_MULTIPLE        1
234#define PPC_USE_SPRG            1
235
236#define PPC_MSR_0               0x00009000
237#define PPC_MSR_1               0x00001000
238#define PPC_MSR_2               0x00001000
239#define PPC_MSR_3               0x00000000
240
241#elif defined(mpc821)
242/*
243 *  Added by Andrew Bray <andy@chaos.org.uk> 6/April/1999
244 */
245#define CPU_MODEL_NAME  "PowerPC MPC821"
246
247#define PPC_ALIGNMENT           4
248#define PPC_I_CACHE             4096
249#define PPC_D_CACHE             4096
250#define PPC_CACHE_ALIGNMENT     16
251#define PPC_INTERRUPT_MAX       71
252#define PPC_HAS_FPU             0
253#define PPC_HAS_DOUBLE          0
254
255#define PPC_MSR_0               0x00009000
256#define PPC_MSR_1               0x00001000
257#define PPC_MSR_2               0x00001000
258#define PPC_MSR_3               0x00000000
259
260#elif defined(mpc750)
261
262#define CPU_MODEL_NAME  "PowerPC 750"
263
264#define PPC_ALIGNMENT           8
265#define PPC_I_CACHE             16384
266#define PPC_D_CACHE             16384
267 
268#else
269 
270#error "Unsupported CPU Model"
271 
272#endif
273
274/*
275 *  Application binary interfaces.
276 *
277 *  PPC_ABI MUST be defined as one of these.
278 *  Only PPC_ABI_POWEROPEN is currently fully supported.
279 *  Only EABI will be supported in the end when
280 *  the tools are there.
281 *  Only big endian is currently supported.
282 */
283/*
284 *  PowerOpen ABI.  This is Andy's hack of the
285 *  PowerOpen ABI to ELF.  ELF rather than a
286 *  XCOFF assembler is used.  This may work
287 *  if PPC_ASM == PPC_ASM_XCOFF is defined.
288 */
289#define PPC_ABI_POWEROPEN       0
290/*
291 *  GCC 2.7.0 munched version of EABI, with
292 *  PowerOpen calling convention and stack frames,
293 *  but EABI style indirect function calls.
294 */
295#define PPC_ABI_GCC27           1
296/*
297 *  SVR4 ABI
298 */
299#define PPC_ABI_SVR4            2
300/*
301 *  Embedded ABI
302 */
303#define PPC_ABI_EABI            3
304
305/*
306 *  Default to the EABI used by current GNU tools
307 */
308
309#ifndef PPC_ABI
310#define PPC_ABI PPC_ABI_EABI
311#endif
312
313#if (PPC_ABI == PPC_ABI_POWEROPEN)
314#define PPC_STACK_ALIGNMENT     8
315#elif (PPC_ABI == PPC_ABI_GCC27)
316#define PPC_STACK_ALIGNMENT     8
317#elif (PPC_ABI == PPC_ABI_SVR4)
318#define PPC_STACK_ALIGNMENT     16
319#elif (PPC_ABI == PPC_ABI_EABI)
320#define PPC_STACK_ALIGNMENT     8
321#else
322#error  "PPC_ABI is not properly defined"
323#endif
324#ifndef PPC_ABI
325#error  "PPC_ABI is not properly defined"
326#endif
327
328/*
329 *  Assemblers.
330 *  PPC_ASM MUST be defined as one of these.
331 *
332 *  PPC_ASM_ELF:   ELF assembler. Currently used for all ABIs.
333 *  PPC_ASM_XCOFF: XCOFF assembler. May be needed for PowerOpen ABI.
334 *
335 *  NOTE: Only PPC_ABI_ELF is currently fully supported.
336 */
337
338#define PPC_ASM_ELF   0
339#define PPC_ASM_XCOFF 1
340
341/*
342 *  Default to the assembler format used by the current GNU tools.
343 */
344
345#ifndef PPC_ASM
346#define PPC_ASM PPC_ASM_ELF
347#endif
348
349/*
350 *  Use the default debug scheme defined in the architectural specification
351 *  if another model has not been specified.
352 */
353
354#ifndef PPC_DEBUG_MODEL
355#define PPC_DEBUG_MODEL PPC_DEBUG_MODEL_STANDARD
356#endif
357
358/*
359 *  If the maximum number of exception sources has not been defined,
360 *  then default it to 16.
361 */
362
363#ifndef PPC_INTERRUPT_MAX
364#define PPC_INTERRUPT_MAX       16
365#endif
366
367/*
368 *  Unless specified otherwise, the cache line size is defaulted to 32.
369 *
370 *  The derive the power of 2 the cache line is.
371 */
372
373#ifndef PPC_CACHE_ALIGNMENT
374#define PPC_CACHE_ALIGNMENT 32
375#endif
376
377#if (PPC_CACHE_ALIGNMENT == 16)
378#define PPC_CACHE_ALIGN_POWER 4
379#elif (PPC_CACHE_ALIGNMENT == 32)
380#define PPC_CACHE_ALIGN_POWER 5
381#else
382#error "Undefined power of 2 for PPC_CACHE_ALIGNMENT"
383#endif
384
385/*
386 *  Unless otherwise specified, assume the model has an IP/EP bit to
387 *  set the exception address prefix.
388 */
389
390#ifndef PPC_HAS_EXCEPTION_PREFIX
391#define PPC_HAS_EXCEPTION_PREFIX 1
392#endif
393
394/*
395 *  Unless otherwise specified, assume the model does NOT have
396 *  403 style EVPR register to set the exception address prefix.
397 */
398
399#ifndef PPC_HAS_EVPR
400#define PPC_HAS_EVPR 0
401#endif
402
403/*
404 *  If no low power mode model was specified, then assume there is none.
405 */
406
407#ifndef PPC_LOW_POWER_MODE
408#define PPC_LOW_POWER_MODE PPC_LOW_POWER_MODE_NONE
409#endif
410
411/*
412 *  Unless specified above, then assume the model has FP support.
413 */
414
415#ifndef PPC_HAS_FPU
416#define PPC_HAS_FPU 1
417#endif
418
419/*
420 *  Unless specified above, If the model has FP support, it is assumed to
421 *  support doubles (8-byte floating point numbers).
422 *
423 *  If the model does NOT have FP support, then the model does
424 *  NOT have double length FP registers.
425 */
426
427#ifndef PPC_HAS_DOUBLE
428#if (PPC_HAS_FPU)
429#define PPC_HAS_DOUBLE 1
430#else
431#define PPC_HAS_DOUBLE 0
432#endif
433#endif
434
435/*
436 *  Unless specified above, then assume the model does NOT have critical
437 *  interrupt support.
438 */
439
440#ifndef PPC_HAS_RFCI
441#define PPC_HAS_RFCI 0
442#endif
443
444/*
445 *  Unless specified above, do not use the load/store multiple instructions
446 *  in a context switch.
447 */
448
449#ifndef PPC_USE_MULTIPLE
450#define PPC_USE_MULTIPLE 0
451#endif
452
453/*
454 *  The following exceptions are not maskable, and are not
455 *  necessarily predictable, so cannot be offered to RTEMS:
456 *    Alignment exception - handled by the CPU module
457 *    Data exceptions.
458 *    Instruction exceptions.
459 */
460
461/*
462 *  Base Interrupt vectors supported on all models.
463 */
464#define PPC_IRQ_SYSTEM_RESET     0 /* 0x00100 - System reset.              */
465#define PPC_IRQ_MCHECK           1 /* 0x00200 - Machine check              */
466#define PPC_IRQ_PROTECT          2 /* 0x00300 - Protection violation       */
467#define PPC_IRQ_ISI              3 /* 0x00400 - Instruction Fetch error    */
468#define PPC_IRQ_EXTERNAL         4 /* 0x00500 - External interrupt         */
469#define PPC_IRQ_ALIGNMENT        5 /* 0X00600 - Alignment exception        */
470#define PPC_IRQ_PROGRAM          6 /* 0x00700 - Program exception          */
471#define PPC_IRQ_NOFP             7 /* 0x00800 - Floating point unavailable */
472#define PPC_IRQ_DECREMENTER      8 /* 0x00900 - Decrementer interrupt      */
473#define PPC_IRQ_RESERVED_A       9 /* 0x00a00 - Implementation Reserved    */
474#define PPC_IRQ_RESERVED_B      10 /* 0x00a00 - Implementation Reserved    */
475#define PPC_IRQ_SCALL           11 /* 0x00c00 - System call                */
476#define PPC_IRQ_TRACE           12 /* 0x00d00 - Trace Exception            */
477#define PPC_IRQ_FP_ASST         13 /* ox00e00 - Floating point assist      */
478#define PPC_STD_IRQ_LAST        PPC_IRQ_FP_ASST
479
480#define PPC_IRQ_FIRST           PPC_IRQ_SYSTEM_RESET
481
482#if defined(ppc403)
483                                 
484#define PPC_IRQ_CRIT     PPC_IRQ_SYSTEM_RESET /*0x00100- Critical int. pin */
485#define PPC_IRQ_PIT      (PPC_STD_IRQ_LAST+1) /*0x01000- Pgm interval timer*/
486#define PPC_IRQ_FIT      (PPC_STD_IRQ_LAST+2) /*0x01010- Fixed int. timer  */
487#define PPC_IRQ_WATCHDOG (PPC_STD_IRQ_LAST+3) /*0x01020- Watchdog timer    */
488#define PPC_IRQ_DEBUG    (PPC_STD_IRQ_LAST+4) /*0x02000- Debug exceptions  */
489#define PPC_IRQ_LAST     PPC_IRQ_DEBUG
490
491#elif defined(mpc505) || defined(mpc509)
492#define PPC_IRQ_SOFTEMU   (PPC_STD_IRQ_LAST+1)    /* Software emulation. */
493#define PPC_IRQ_DATA_BP   (PPC_STD_IRQ_LAST+ 2)
494#define PPC_IRQ_INST_BP   (PPC_STD_IRQ_LAST+ 3)
495#define PPC_IRQ_MEXT_BP   (PPC_STD_IRQ_LAST+ 4)
496#define PPC_IRQ_NMEXT_BP  (PPC_STD_IRQ_LAST+ 5)
497
498#elif defined(ppc601)
499#define PPC_IRQ_TRACE    (PPC_STD_IRQ_LAST+1) /*0x02000-Run/Trace Exception*/
500#define PPC_IRQ_LAST     PPC_IRQ_TRACE       
501
502#elif defined(ppc602)
503#define PPC_IRQ_LAST     (PPC_STD_IRQ_LAST)
504
505#elif defined(ppc603)
506#define PPC_IRQ_TRANS_MISS (PPC_STD_IRQ_LAST+1) /*0x1000-Ins Translation Miss*/
507#define PPC_IRQ_DATA_LOAD  (PPC_STD_IRQ_LAST+2) /*0x1100-Data Load Trans Miss*/
508#define PPC_IRQ_DATA_STORE (PPC_STD_IRQ_LAST+3) /*0x1200-Data Store Miss     */
509#define PPC_IRQ_ADDR_BRK   (PPC_STD_IRQ_LAST+4) /*0x1300-Instruction Bkpoint */
510#define PPC_IRQ_SYS_MGT    (PPC_STD_IRQ_LAST+5) /*0x1400-System Management   */
511#define PPC_IRQ_LAST       PPC_IRQ_SYS_MGT   
512
513#elif defined(ppc603e)
514#define PPC_TLB_INST_MISS  (PPC_STD_IRQ_LAST+1) /*0x1000-Instruction TLB Miss*/
515#define PPC_TLB_LOAD_MISS  (PPC_STD_IRQ_LAST+2) /*0x1100-TLB miss on load  */
516#define PPC_TLB_STORE_MISS (PPC_STD_IRQ_LAST+3) /*0x1200-TLB Miss on store */
517#define PPC_IRQ_ADDRBRK    (PPC_STD_IRQ_LAST+4) /*0x1300-Instruct addr break */
518#define PPC_IRQ_SYS_MGT    (PPC_STD_IRQ_LAST+5) /*0x1400-System Management   */
519#define PPC_IRQ_LAST       PPC_IRQ_SYS_MGT   
520
521
522#elif defined(mpc604)
523#define PPC_IRQ_ADDR_BRK (PPC_STD_IRQ_LAST+1) /*0x1300- Inst. addr break  */
524#define PPC_IRQ_SYS_MGT  (PPC_STD_IRQ_LAST+2) /*0x1400- System Management */
525#define PPC_IRQ_LAST     PPC_IRQ_SYS_MGT 
526
527#elif defined(mpc860) || defined(mpc821)
528#define PPC_IRQ_EMULATE         (PPC_STD_IRQ_LAST+1) /*0x1000-Software emulation  */
529#define PPC_IRQ_INST_MISS       (PPC_STD_IRQ_LAST+2) /*0x1100-Instruction TLB miss*/
530#define PPC_IRQ_DATA_MISS       (PPC_STD_IRQ_LAST+3) /*0x1200-Data TLB miss */
531#define PPC_IRQ_INST_ERR        (PPC_STD_IRQ_LAST+4) /*0x1300-Instruction TLB err */
532#define PPC_IRQ_DATA_ERR        (PPC_STD_IRQ_LAST+5) /*0x1400-Data TLB error */
533#define PPC_IRQ_DATA_BPNT       (PPC_STD_IRQ_LAST+6) /*0x1C00-Data breakpoint */
534#define PPC_IRQ_INST_BPNT       (PPC_STD_IRQ_LAST+7) /*0x1D00-Inst breakpoint */
535#define PPC_IRQ_IO_BPNT         (PPC_STD_IRQ_LAST+8) /*0x1E00-Peripheral breakpnt */
536#define PPC_IRQ_DEV_PORT        (PPC_STD_IRQ_LAST+9) /*0x1F00-Development port */
537#define PPC_IRQ_IRQ0            (PPC_STD_IRQ_LAST + 10)
538#define PPC_IRQ_LVL0            (PPC_STD_IRQ_LAST + 11)
539#define PPC_IRQ_IRQ1            (PPC_STD_IRQ_LAST + 12)
540#define PPC_IRQ_LVL1            (PPC_STD_IRQ_LAST + 13)
541#define PPC_IRQ_IRQ2            (PPC_STD_IRQ_LAST + 14)
542#define PPC_IRQ_LVL2            (PPC_STD_IRQ_LAST + 15)
543#define PPC_IRQ_IRQ3            (PPC_STD_IRQ_LAST + 16)
544#define PPC_IRQ_LVL3            (PPC_STD_IRQ_LAST + 17)
545#define PPC_IRQ_IRQ4            (PPC_STD_IRQ_LAST + 18)
546#define PPC_IRQ_LVL4            (PPC_STD_IRQ_LAST + 19)
547#define PPC_IRQ_IRQ5            (PPC_STD_IRQ_LAST + 20)
548#define PPC_IRQ_LVL5            (PPC_STD_IRQ_LAST + 21)
549#define PPC_IRQ_IRQ6            (PPC_STD_IRQ_LAST + 22)
550#define PPC_IRQ_LVL6            (PPC_STD_IRQ_LAST + 23)
551#define PPC_IRQ_IRQ7            (PPC_STD_IRQ_LAST + 24)
552#define PPC_IRQ_LVL7            (PPC_STD_IRQ_LAST + 25)
553#define PPC_IRQ_CPM_RESERVED_0  (PPC_STD_IRQ_LAST + 26)
554#define PPC_IRQ_CPM_PC4         (PPC_STD_IRQ_LAST + 27)
555#define PPC_IRQ_CPM_PC5         (PPC_STD_IRQ_LAST + 28)
556#define PPC_IRQ_CPM_SMC2        (PPC_STD_IRQ_LAST + 29)
557#define PPC_IRQ_CPM_SMC1        (PPC_STD_IRQ_LAST + 30)
558#define PPC_IRQ_CPM_SPI         (PPC_STD_IRQ_LAST + 31)
559#define PPC_IRQ_CPM_PC6         (PPC_STD_IRQ_LAST + 32)
560#define PPC_IRQ_CPM_TIMER4      (PPC_STD_IRQ_LAST + 33)
561#define PPC_IRQ_CPM_RESERVED_8  (PPC_STD_IRQ_LAST + 34)
562#define PPC_IRQ_CPM_PC7         (PPC_STD_IRQ_LAST + 35)
563#define PPC_IRQ_CPM_PC8         (PPC_STD_IRQ_LAST + 36)
564#define PPC_IRQ_CPM_PC9         (PPC_STD_IRQ_LAST + 37)
565#define PPC_IRQ_CPM_TIMER3      (PPC_STD_IRQ_LAST + 38)
566#define PPC_IRQ_CPM_RESERVED_D  (PPC_STD_IRQ_LAST + 39)
567#define PPC_IRQ_CPM_PC10        (PPC_STD_IRQ_LAST + 40)
568#define PPC_IRQ_CPM_PC11        (PPC_STD_IRQ_LAST + 41)
569#define PPC_IRQ_CPM_I2C         (PPC_STD_IRQ_LAST + 42)
570#define PPC_IRQ_CPM_RISC_TIMER  (PPC_STD_IRQ_LAST + 43)
571#define PPC_IRQ_CPM_TIMER2      (PPC_STD_IRQ_LAST + 44)
572#define PPC_IRQ_CPM_RESERVED_13 (PPC_STD_IRQ_LAST + 45)
573#define PPC_IRQ_CPM_IDMA2       (PPC_STD_IRQ_LAST + 46)
574#define PPC_IRQ_CPM_IDMA1       (PPC_STD_IRQ_LAST + 47)
575#define PPC_IRQ_CPM_SDMA_ERROR  (PPC_STD_IRQ_LAST + 48)
576#define PPC_IRQ_CPM_PC12        (PPC_STD_IRQ_LAST + 49)
577#define PPC_IRQ_CPM_PC13        (PPC_STD_IRQ_LAST + 50)
578#define PPC_IRQ_CPM_TIMER1      (PPC_STD_IRQ_LAST + 51)
579#define PPC_IRQ_CPM_PC14        (PPC_STD_IRQ_LAST + 52)
580#define PPC_IRQ_CPM_SCC4        (PPC_STD_IRQ_LAST + 53)
581#define PPC_IRQ_CPM_SCC3        (PPC_STD_IRQ_LAST + 54)
582#define PPC_IRQ_CPM_SCC2        (PPC_STD_IRQ_LAST + 55)
583#define PPC_IRQ_CPM_SCC1        (PPC_STD_IRQ_LAST + 56)
584#define PPC_IRQ_CPM_PC15        (PPC_STD_IRQ_LAST + 57)
585
586#define PPC_IRQ_LAST             PPC_IRQ_CPM_PC15
587
588#endif
589
590/*
591 *  If the maximum number of exception sources is too low,
592 *  then fix it
593 */
594
595#if PPC_INTERRUPT_MAX <= PPC_IRQ_LAST
596#undef PPC_INTERRUPT_MAX
597#define PPC_INTERRUPT_MAX ((PPC_IRQ_LAST) + 1)
598#endif
599
600/*
601 *  Machine Status Register (MSR) Constants Used by RTEMS
602 */
603
604/*
605 *  Some PPC model manuals refer to the Exception Prefix (EP) bit as
606 *  IP for no apparent reason.
607 */
608
609#define PPC_MSR_RI       0x000000002 /* bit 30 - recoverable exception */
610#define PPC_MSR_DR       0x000000010 /* bit 27 - data address translation */
611#define PPC_MSR_IR       0x000000020 /* bit 26 - instruction addr translation*/
612
613#if (PPC_HAS_EXCEPTION_PREFIX)
614#define PPC_MSR_EP       0x000000040 /* bit 25 - exception prefix */
615#else
616#define PPC_MSR_EP       0x000000000 /* bit 25 - exception prefix */
617#endif
618
619#if (PPC_HAS_FPU)
620#define PPC_MSR_FP       0x000002000 /* bit 18 - floating point enable */
621#else
622#define PPC_MSR_FP       0x000000000 /* bit 18 - floating point enable */
623#endif
624
625#if (PPC_LOW_POWER_MODE == PPC_LOW_POWER_MODE_NONE)
626#define PPC_MSR_POW      0x000000000 /* bit 13 - power management enable */
627#else
628#define PPC_MSR_POW      0x000040000 /* bit 13 - power management enable */
629#endif
630
631/*
632 *  Interrupt/exception MSR bits set as defined on p. 2-20 in "The Programming
633 *  Environments" and the manuals for various PPC models.
634 */
635
636#if (PPC_DEBUG_MODEL == PPC_DEBUG_MODEL_STANDARD)
637#define PPC_MSR_DE       0x000000000 /* bit 22 - debug exception enable */
638#define PPC_MSR_BE       0x000000200 /* bit 22 - branch trace enable */
639#define PPC_MSR_SE       0x000000400 /* bit 21 - single step trace enable */
640#elif (PPC_DEBUG_MODEL == PPC_DEBUG_MODEL_SINGLE_STEP_ONLY)
641#define PPC_MSR_DE       0x000000000 /* bit 22 - debug exception enable */
642#define PPC_MSR_BE       0x000000200 /* bit 22 - branch trace enable */
643#define PPC_MSR_SE       0x000000000 /* bit 21 - single step trace enable */
644#elif (PPC_DEBUG_MODEL == PPC_DEBUG_MODEL_IBM4xx)
645#define PPC_MSR_DE       0x000000200 /* bit 22 - debug exception enable */
646#define PPC_MSR_BE       0x000000000 /* bit 22 - branch trace enable */
647#define PPC_MSR_SE       0x000000000 /* bit 21 - single step trace enable */
648#else
649#error "MSR constants -- unknown PPC_DEBUG_MODEL!!"
650#endif
651
652#define PPC_MSR_ME       0x000001000 /* bit 19 - machine check enable */
653#define PPC_MSR_EE       0x000008000 /* bit 16 - external interrupt enable */
654
655#if (PPC_HAS_RFCI)
656#define PPC_MSR_CE       0x000020000 /* bit 14 - critical interrupt enable */
657#else
658#define PPC_MSR_CE       0x000000000 /* bit 14 - critical interrupt enable */
659#endif
660
661#define PPC_MSR_DISABLE_MASK (PPC_MSR_ME|PPC_MSR_EE|PPC_MSR_CE)
662
663/*
664 *  Initial value for the FPSCR register
665 */
666
667#define PPC_INIT_FPSCR          0x000000f8
668
669#ifdef __cplusplus
670}
671#endif
672
673#endif /* ! _INCLUDE_PPC_h */
674/* end of include file */
675
676
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