1 | /* ppc.h |
---|
2 | * |
---|
3 | * This file contains definitions for the IBM/Motorola PowerPC |
---|
4 | * family members. |
---|
5 | * |
---|
6 | * Author: Andrew Bray <andy@i-cubed.co.uk> |
---|
7 | * |
---|
8 | * COPYRIGHT (c) 1995 by i-cubed ltd. |
---|
9 | * |
---|
10 | * MPC860 support code was added by Jay Monkman <jmonkman@frasca.com> |
---|
11 | * |
---|
12 | * To anyone who acknowledges that this file is provided "AS IS" |
---|
13 | * without any express or implied warranty: |
---|
14 | * permission to use, copy, modify, and distribute this file |
---|
15 | * for any purpose is hereby granted without fee, provided that |
---|
16 | * the above copyright notice and this notice appears in all |
---|
17 | * copies, and that the name of i-cubed limited not be used in |
---|
18 | * advertising or publicity pertaining to distribution of the |
---|
19 | * software without specific, written prior permission. |
---|
20 | * i-cubed limited makes no representations about the suitability |
---|
21 | * of this software for any purpose. |
---|
22 | * |
---|
23 | * Derived from c/src/exec/cpu/no_cpu/no_cpu.h: |
---|
24 | * |
---|
25 | * COPYRIGHT (c) 1989-1997. |
---|
26 | * On-Line Applications Research Corporation (OAR). |
---|
27 | * |
---|
28 | * The license and distribution terms for this file may in |
---|
29 | * the file LICENSE in this distribution or at |
---|
30 | * http://www.OARcorp.com/rtems/license.html. |
---|
31 | * |
---|
32 | * |
---|
33 | * Note: |
---|
34 | * This file is included by both C and assembler code ( -DASM ) |
---|
35 | * |
---|
36 | * $Id$ |
---|
37 | */ |
---|
38 | |
---|
39 | |
---|
40 | #ifndef _INCLUDE_PPC_h |
---|
41 | #define _INCLUDE_PPC_h |
---|
42 | |
---|
43 | #ifdef __cplusplus |
---|
44 | extern "C" { |
---|
45 | #endif |
---|
46 | |
---|
47 | #include <rtems/score/ppctypes.h> |
---|
48 | |
---|
49 | /* |
---|
50 | * Define the name of the CPU family. |
---|
51 | */ |
---|
52 | |
---|
53 | #define CPU_NAME "PowerPC" |
---|
54 | |
---|
55 | /* |
---|
56 | * This file contains the information required to build |
---|
57 | * RTEMS for a particular member of the PowerPC family. It does |
---|
58 | * this by setting variables to indicate which implementation |
---|
59 | * dependent features are present in a particular member |
---|
60 | * of the family. |
---|
61 | * |
---|
62 | * The following architectural feature definitions are defaulted |
---|
63 | * unless specifically set by the model definition: |
---|
64 | * |
---|
65 | * + PPC_DEBUG_MODEL - PPC_DEBUG_MODEL_STANDARD |
---|
66 | * + PPC_INTERRUPT_MAX - 16 |
---|
67 | * + PPC_CACHE_ALIGNMENT - 32 |
---|
68 | * + PPC_LOW_POWER_MODE - PPC_LOW_POWER_MODE_NONE |
---|
69 | * + PPC_HAS_EXCEPTION_PREFIX - 1 |
---|
70 | * + PPC_HAS_FPU - 1 |
---|
71 | * + PPC_HAS_DOUBLE - 1 if PPC_HAS_FPU, |
---|
72 | * - 0 otherwise |
---|
73 | * + PPC_USE_MULTIPLE - 0 |
---|
74 | */ |
---|
75 | |
---|
76 | /* |
---|
77 | * Define the debugging assistance models found in the PPC family. |
---|
78 | * |
---|
79 | * Standard: single step and branch trace |
---|
80 | * Single Step Only: single step only |
---|
81 | * IBM 4xx: debug exception |
---|
82 | */ |
---|
83 | |
---|
84 | #define PPC_DEBUG_MODEL_STANDARD 1 |
---|
85 | #define PPC_DEBUG_MODEL_SINGLE_STEP_ONLY 2 |
---|
86 | #define PPC_DEBUG_MODEL_IBM4xx 3 |
---|
87 | |
---|
88 | /* |
---|
89 | * Define the low power mode models |
---|
90 | * |
---|
91 | * Standard: as defined for 603e |
---|
92 | * Nap Mode: nap mode only (604) |
---|
93 | * XXX 403GB, 603, 603e, 604, 821 |
---|
94 | */ |
---|
95 | |
---|
96 | #define PPC_LOW_POWER_MODE_NONE 0 |
---|
97 | #define PPC_LOW_POWER_MODE_STANDARD 1 |
---|
98 | |
---|
99 | #if defined(rtems_multilib) |
---|
100 | /* |
---|
101 | * Figure out all CPU Model Feature Flags based upon compiler |
---|
102 | * predefines. |
---|
103 | */ |
---|
104 | |
---|
105 | #define CPU_MODEL_NAME "rtems_multilib" |
---|
106 | #define PPC_ALIGNMENT 4 |
---|
107 | #define PPC_CACHE_ALIGNMENT 16 |
---|
108 | #define PPC_HAS_RFCI 1 |
---|
109 | #define PPC_HAS_FPU 0 |
---|
110 | #define PPC_USE_MULTIPLE 1 |
---|
111 | #define PPC_I_CACHE 2048 |
---|
112 | #define PPC_D_CACHE 1024 |
---|
113 | #define PPC_DEBUG_MODEL PPC_DEBUG_MODEL_STANDARD |
---|
114 | #define PPC_HAS_EXCEPTION_PREFIX 0 |
---|
115 | #define PPC_HAS_EVPR 0 |
---|
116 | #define PPC_INTERRUPT_MAX 16 |
---|
117 | #define PPC_LOW_POWER_MODE PPC_LOW_POWER_MODE_STANDARD |
---|
118 | #define PPC_HAS_DOUBLE 0 |
---|
119 | |
---|
120 | #elif defined(ppc403) |
---|
121 | /* |
---|
122 | * IBM 403 |
---|
123 | * |
---|
124 | * Developed for 403GA. Book checked for 403GB. |
---|
125 | * |
---|
126 | * Does not have user mode. |
---|
127 | */ |
---|
128 | |
---|
129 | #define CPU_MODEL_NAME "PowerPC 403" |
---|
130 | #define PPC_ALIGNMENT 4 |
---|
131 | #define PPC_CACHE_ALIGNMENT 16 |
---|
132 | #define PPC_HAS_RFCI 1 |
---|
133 | #define PPC_HAS_FPU 0 |
---|
134 | #define PPC_USE_MULTIPLE 1 |
---|
135 | #define PPC_I_CACHE 2048 |
---|
136 | #define PPC_D_CACHE 1024 |
---|
137 | |
---|
138 | #define PPC_DEBUG_MODEL PPC_DEBUG_MODEL_IBM4xx |
---|
139 | #define PPC_HAS_EXCEPTION_PREFIX 0 |
---|
140 | #define PPC_HAS_EVPR 1 |
---|
141 | |
---|
142 | |
---|
143 | #elif defined(mpc505) || defined(mpc509) |
---|
144 | /* |
---|
145 | * Submitted by Sergei Organov <osv@Javad.RU> as a patch against |
---|
146 | * 3.6.0 long after 4.0 was released. This is just an attempt |
---|
147 | * to get the setting correct. |
---|
148 | */ |
---|
149 | |
---|
150 | #define CPU_MODEL_NAME "PowerPC 505/509" |
---|
151 | |
---|
152 | #define PPC_ALIGNMENT 4 |
---|
153 | #define PPC_CACHE_ALIGNMENT 16 |
---|
154 | #define PPC_I_CACHE 4096 |
---|
155 | #define PPC_D_CACHE 0 |
---|
156 | |
---|
157 | |
---|
158 | #elif defined(ppc601) |
---|
159 | |
---|
160 | /* |
---|
161 | * Submitted with original port -- book checked only. |
---|
162 | */ |
---|
163 | |
---|
164 | #define CPU_MODEL_NAME "PowerPC 601" |
---|
165 | |
---|
166 | #define PPC_ALIGNMENT 8 |
---|
167 | #define PPC_USE_MULTIPLE 1 |
---|
168 | #define PPC_I_CACHE 0 |
---|
169 | #define PPC_D_CACHE 32768 |
---|
170 | |
---|
171 | #define PPC_DEBUG_MODEL PPC_DEBUG_MODEL_SINGLE_STEP_ONLY |
---|
172 | |
---|
173 | #elif defined(ppc602) |
---|
174 | /* |
---|
175 | * Submitted with original port -- book checked only. |
---|
176 | */ |
---|
177 | |
---|
178 | #define CPU_MODEL_NAME "PowerPC 602" |
---|
179 | |
---|
180 | #define PPC_ALIGNMENT 4 |
---|
181 | #define PPC_HAS_DOUBLE 0 |
---|
182 | #define PPC_I_CACHE 4096 |
---|
183 | #define PPC_D_CACHE 4096 |
---|
184 | |
---|
185 | #elif defined(ppc603) |
---|
186 | /* |
---|
187 | * Submitted with original port -- book checked only. |
---|
188 | */ |
---|
189 | |
---|
190 | #define CPU_MODEL_NAME "PowerPC 603" |
---|
191 | |
---|
192 | #define PPC_ALIGNMENT 8 |
---|
193 | #define PPC_I_CACHE 8192 |
---|
194 | #define PPC_D_CACHE 8192 |
---|
195 | |
---|
196 | #elif defined(ppc603e) |
---|
197 | |
---|
198 | #define CPU_MODEL_NAME "PowerPC 603e" |
---|
199 | /* |
---|
200 | * Submitted with original port. |
---|
201 | * |
---|
202 | * Known to work on real hardware. |
---|
203 | */ |
---|
204 | |
---|
205 | #define PPC_ALIGNMENT 8 |
---|
206 | #define PPC_I_CACHE 16384 |
---|
207 | #define PPC_D_CACHE 16384 |
---|
208 | |
---|
209 | #define PPC_LOW_POWER_MODE PPC_LOW_POWER_MODE_STANDARD |
---|
210 | |
---|
211 | #elif defined(mpc604) |
---|
212 | /* |
---|
213 | * Submitted with original port -- book checked only. |
---|
214 | */ |
---|
215 | |
---|
216 | #define CPU_MODEL_NAME "PowerPC 604" |
---|
217 | |
---|
218 | #define PPC_ALIGNMENT 8 |
---|
219 | #define PPC_I_CACHE 16384 |
---|
220 | #define PPC_D_CACHE 16384 |
---|
221 | |
---|
222 | #elif defined(mpc860) |
---|
223 | /* |
---|
224 | * Added by Jay Monkman (jmonkman@frasca.com) 6/28/98 |
---|
225 | * with some changes by Darlene Stewart (Darlene.Stewart@iit.nrc.ca) |
---|
226 | */ |
---|
227 | #define CPU_MODEL_NAME "PowerPC MPC860" |
---|
228 | |
---|
229 | #define PPC_ALIGNMENT 4 |
---|
230 | #define PPC_I_CACHE 4096 |
---|
231 | #define PPC_D_CACHE 4096 |
---|
232 | #define PPC_CACHE_ALIGNMENT 16 |
---|
233 | #define PPC_INTERRUPT_MAX 71 |
---|
234 | #define PPC_HAS_FPU 0 |
---|
235 | #define PPC_HAS_DOUBLE 0 |
---|
236 | #define PPC_USE_MULTIPLE 1 |
---|
237 | |
---|
238 | #define PPC_MSR_0 0x00009000 |
---|
239 | #define PPC_MSR_1 0x00001000 |
---|
240 | #define PPC_MSR_2 0x00001000 |
---|
241 | #define PPC_MSR_3 0x00000000 |
---|
242 | |
---|
243 | #elif defined(mpc821) |
---|
244 | /* |
---|
245 | * Added by Andrew Bray <andy@chaos.org.uk> 6/April/1999 |
---|
246 | */ |
---|
247 | #define CPU_MODEL_NAME "PowerPC MPC821" |
---|
248 | |
---|
249 | #define PPC_ALIGNMENT 4 |
---|
250 | #define PPC_I_CACHE 4096 |
---|
251 | #define PPC_D_CACHE 4096 |
---|
252 | #define PPC_CACHE_ALIGNMENT 16 |
---|
253 | #define PPC_INTERRUPT_MAX 71 |
---|
254 | #define PPC_HAS_FPU 0 |
---|
255 | #define PPC_HAS_DOUBLE 0 |
---|
256 | |
---|
257 | #define PPC_MSR_0 0x00009000 |
---|
258 | #define PPC_MSR_1 0x00001000 |
---|
259 | #define PPC_MSR_2 0x00001000 |
---|
260 | #define PPC_MSR_3 0x00000000 |
---|
261 | |
---|
262 | #elif defined(mpc750) |
---|
263 | |
---|
264 | #define CPU_MODEL_NAME "PowerPC 750" |
---|
265 | |
---|
266 | #define PPC_ALIGNMENT 8 |
---|
267 | #define PPC_I_CACHE 16384 |
---|
268 | #define PPC_D_CACHE 16384 |
---|
269 | |
---|
270 | #else |
---|
271 | |
---|
272 | #error "Unsupported CPU Model" |
---|
273 | |
---|
274 | #endif |
---|
275 | |
---|
276 | /* |
---|
277 | * Application binary interfaces. |
---|
278 | * |
---|
279 | * PPC_ABI MUST be defined as one of these. |
---|
280 | * Only PPC_ABI_POWEROPEN is currently fully supported. |
---|
281 | * Only EABI will be supported in the end when |
---|
282 | * the tools are there. |
---|
283 | * Only big endian is currently supported. |
---|
284 | */ |
---|
285 | /* |
---|
286 | * PowerOpen ABI. This is Andy's hack of the |
---|
287 | * PowerOpen ABI to ELF. ELF rather than a |
---|
288 | * XCOFF assembler is used. This may work |
---|
289 | * if PPC_ASM == PPC_ASM_XCOFF is defined. |
---|
290 | */ |
---|
291 | #define PPC_ABI_POWEROPEN 0 |
---|
292 | /* |
---|
293 | * GCC 2.7.0 munched version of EABI, with |
---|
294 | * PowerOpen calling convention and stack frames, |
---|
295 | * but EABI style indirect function calls. |
---|
296 | */ |
---|
297 | #define PPC_ABI_GCC27 1 |
---|
298 | /* |
---|
299 | * SVR4 ABI |
---|
300 | */ |
---|
301 | #define PPC_ABI_SVR4 2 |
---|
302 | /* |
---|
303 | * Embedded ABI |
---|
304 | */ |
---|
305 | #define PPC_ABI_EABI 3 |
---|
306 | |
---|
307 | /* |
---|
308 | * Default to the EABI used by current GNU tools |
---|
309 | */ |
---|
310 | |
---|
311 | #ifndef PPC_ABI |
---|
312 | #define PPC_ABI PPC_ABI_EABI |
---|
313 | #endif |
---|
314 | |
---|
315 | #if (PPC_ABI == PPC_ABI_POWEROPEN) |
---|
316 | #define PPC_STACK_ALIGNMENT 8 |
---|
317 | #elif (PPC_ABI == PPC_ABI_GCC27) |
---|
318 | #define PPC_STACK_ALIGNMENT 8 |
---|
319 | #elif (PPC_ABI == PPC_ABI_SVR4) |
---|
320 | #define PPC_STACK_ALIGNMENT 16 |
---|
321 | #elif (PPC_ABI == PPC_ABI_EABI) |
---|
322 | #define PPC_STACK_ALIGNMENT 8 |
---|
323 | #else |
---|
324 | #error "PPC_ABI is not properly defined" |
---|
325 | #endif |
---|
326 | #ifndef PPC_ABI |
---|
327 | #error "PPC_ABI is not properly defined" |
---|
328 | #endif |
---|
329 | |
---|
330 | /* |
---|
331 | * Assemblers. |
---|
332 | * PPC_ASM MUST be defined as one of these. |
---|
333 | * |
---|
334 | * PPC_ASM_ELF: ELF assembler. Currently used for all ABIs. |
---|
335 | * PPC_ASM_XCOFF: XCOFF assembler. May be needed for PowerOpen ABI. |
---|
336 | * |
---|
337 | * NOTE: Only PPC_ABI_ELF is currently fully supported. |
---|
338 | */ |
---|
339 | |
---|
340 | #define PPC_ASM_ELF 0 |
---|
341 | #define PPC_ASM_XCOFF 1 |
---|
342 | |
---|
343 | /* |
---|
344 | * Default to the assembler format used by the current GNU tools. |
---|
345 | */ |
---|
346 | |
---|
347 | #ifndef PPC_ASM |
---|
348 | #define PPC_ASM PPC_ASM_ELF |
---|
349 | #endif |
---|
350 | |
---|
351 | /* |
---|
352 | * Use the default debug scheme defined in the architectural specification |
---|
353 | * if another model has not been specified. |
---|
354 | */ |
---|
355 | |
---|
356 | #ifndef PPC_DEBUG_MODEL |
---|
357 | #define PPC_DEBUG_MODEL PPC_DEBUG_MODEL_STANDARD |
---|
358 | #endif |
---|
359 | |
---|
360 | /* |
---|
361 | * If the maximum number of exception sources has not been defined, |
---|
362 | * then default it to 16. |
---|
363 | */ |
---|
364 | |
---|
365 | #ifndef PPC_INTERRUPT_MAX |
---|
366 | #define PPC_INTERRUPT_MAX 16 |
---|
367 | #endif |
---|
368 | |
---|
369 | /* |
---|
370 | * Unless specified otherwise, the cache line size is defaulted to 32. |
---|
371 | * |
---|
372 | * The derive the power of 2 the cache line is. |
---|
373 | */ |
---|
374 | |
---|
375 | #ifndef PPC_CACHE_ALIGNMENT |
---|
376 | #define PPC_CACHE_ALIGNMENT 32 |
---|
377 | #endif |
---|
378 | |
---|
379 | #if (PPC_CACHE_ALIGNMENT == 16) |
---|
380 | #define PPC_CACHE_ALIGN_POWER 4 |
---|
381 | #elif (PPC_CACHE_ALIGNMENT == 32) |
---|
382 | #define PPC_CACHE_ALIGN_POWER 5 |
---|
383 | #else |
---|
384 | #error "Undefined power of 2 for PPC_CACHE_ALIGNMENT" |
---|
385 | #endif |
---|
386 | |
---|
387 | /* |
---|
388 | * Unless otherwise specified, assume the model has an IP/EP bit to |
---|
389 | * set the exception address prefix. |
---|
390 | */ |
---|
391 | |
---|
392 | #ifndef PPC_HAS_EXCEPTION_PREFIX |
---|
393 | #define PPC_HAS_EXCEPTION_PREFIX 1 |
---|
394 | #endif |
---|
395 | |
---|
396 | /* |
---|
397 | * Unless otherwise specified, assume the model does NOT have |
---|
398 | * 403 style EVPR register to set the exception address prefix. |
---|
399 | */ |
---|
400 | |
---|
401 | #ifndef PPC_HAS_EVPR |
---|
402 | #define PPC_HAS_EVPR 0 |
---|
403 | #endif |
---|
404 | |
---|
405 | /* |
---|
406 | * If no low power mode model was specified, then assume there is none. |
---|
407 | */ |
---|
408 | |
---|
409 | #ifndef PPC_LOW_POWER_MODE |
---|
410 | #define PPC_LOW_POWER_MODE PPC_LOW_POWER_MODE_NONE |
---|
411 | #endif |
---|
412 | |
---|
413 | /* |
---|
414 | * Unless specified above, then assume the model has FP support. |
---|
415 | */ |
---|
416 | |
---|
417 | #ifndef PPC_HAS_FPU |
---|
418 | #define PPC_HAS_FPU 1 |
---|
419 | #endif |
---|
420 | |
---|
421 | /* |
---|
422 | * Unless specified above, If the model has FP support, it is assumed to |
---|
423 | * support doubles (8-byte floating point numbers). |
---|
424 | * |
---|
425 | * If the model does NOT have FP support, then the model does |
---|
426 | * NOT have double length FP registers. |
---|
427 | */ |
---|
428 | |
---|
429 | #ifndef PPC_HAS_DOUBLE |
---|
430 | #if (PPC_HAS_FPU) |
---|
431 | #define PPC_HAS_DOUBLE 1 |
---|
432 | #else |
---|
433 | #define PPC_HAS_DOUBLE 0 |
---|
434 | #endif |
---|
435 | #endif |
---|
436 | |
---|
437 | /* |
---|
438 | * Unless specified above, then assume the model does NOT have critical |
---|
439 | * interrupt support. |
---|
440 | */ |
---|
441 | |
---|
442 | #ifndef PPC_HAS_RFCI |
---|
443 | #define PPC_HAS_RFCI 0 |
---|
444 | #endif |
---|
445 | |
---|
446 | /* |
---|
447 | * Unless specified above, do not use the load/store multiple instructions |
---|
448 | * in a context switch. |
---|
449 | */ |
---|
450 | |
---|
451 | #ifndef PPC_USE_MULTIPLE |
---|
452 | #define PPC_USE_MULTIPLE 0 |
---|
453 | #endif |
---|
454 | |
---|
455 | /* |
---|
456 | * The following exceptions are not maskable, and are not |
---|
457 | * necessarily predictable, so cannot be offered to RTEMS: |
---|
458 | * Alignment exception - handled by the CPU module |
---|
459 | * Data exceptions. |
---|
460 | * Instruction exceptions. |
---|
461 | */ |
---|
462 | |
---|
463 | /* |
---|
464 | * Base Interrupt vectors supported on all models. |
---|
465 | */ |
---|
466 | #define PPC_IRQ_SYSTEM_RESET 0 /* 0x00100 - System reset. */ |
---|
467 | #define PPC_IRQ_MCHECK 1 /* 0x00200 - Machine check */ |
---|
468 | #define PPC_IRQ_PROTECT 2 /* 0x00300 - Protection violation */ |
---|
469 | #define PPC_IRQ_ISI 3 /* 0x00400 - Instruction Fetch error */ |
---|
470 | #define PPC_IRQ_EXTERNAL 4 /* 0x00500 - External interrupt */ |
---|
471 | #define PPC_IRQ_ALIGNMENT 5 /* 0X00600 - Alignment exception */ |
---|
472 | #define PPC_IRQ_PROGRAM 6 /* 0x00700 - Program exception */ |
---|
473 | #define PPC_IRQ_NOFP 7 /* 0x00800 - Floating point unavailable */ |
---|
474 | #define PPC_IRQ_DECREMENTER 8 /* 0x00900 - Decrementer interrupt */ |
---|
475 | #define PPC_IRQ_RESERVED_A 9 /* 0x00a00 - Implementation Reserved */ |
---|
476 | #define PPC_IRQ_RESERVED_B 10 /* 0x00a00 - Implementation Reserved */ |
---|
477 | #define PPC_IRQ_SCALL 11 /* 0x00c00 - System call */ |
---|
478 | #define PPC_IRQ_TRACE 12 /* 0x00d00 - Trace Exception */ |
---|
479 | #define PPC_IRQ_FP_ASST 13 /* ox00e00 - Floating point assist */ |
---|
480 | #define PPC_STD_IRQ_LAST PPC_IRQ_FP_ASST |
---|
481 | |
---|
482 | #define PPC_IRQ_FIRST PPC_IRQ_SYSTEM_RESET |
---|
483 | |
---|
484 | #if defined(ppc403) |
---|
485 | |
---|
486 | #define PPC_IRQ_CRIT PPC_IRQ_SYSTEM_RESET /*0x00100- Critical int. pin */ |
---|
487 | #define PPC_IRQ_PIT (PPC_STD_IRQ_LAST+1) /*0x01000- Pgm interval timer*/ |
---|
488 | #define PPC_IRQ_FIT (PPC_STD_IRQ_LAST+2) /*0x01010- Fixed int. timer */ |
---|
489 | #define PPC_IRQ_WATCHDOG (PPC_STD_IRQ_LAST+3) /*0x01020- Watchdog timer */ |
---|
490 | #define PPC_IRQ_DEBUG (PPC_STD_IRQ_LAST+4) /*0x02000- Debug exceptions */ |
---|
491 | #define PPC_IRQ_LAST PPC_IRQ_DEBUG |
---|
492 | |
---|
493 | #elif defined(mpc505) || defined(mpc509) |
---|
494 | #define PPC_IRQ_SOFTEMU (PPC_STD_IRQ_LAST+1) /* Software emulation. */ |
---|
495 | #define PPC_IRQ_DATA_BP (PPC_STD_IRQ_LAST+ 2) |
---|
496 | #define PPC_IRQ_INST_BP (PPC_STD_IRQ_LAST+ 3) |
---|
497 | #define PPC_IRQ_MEXT_BP (PPC_STD_IRQ_LAST+ 4) |
---|
498 | #define PPC_IRQ_NMEXT_BP (PPC_STD_IRQ_LAST+ 5) |
---|
499 | |
---|
500 | #elif defined(ppc601) |
---|
501 | #define PPC_IRQ_TRACE (PPC_STD_IRQ_LAST+1) /*0x02000-Run/Trace Exception*/ |
---|
502 | #define PPC_IRQ_LAST PPC_IRQ_TRACE |
---|
503 | |
---|
504 | #elif defined(ppc602) |
---|
505 | #define PPC_IRQ_LAST (PPC_STD_IRQ_LAST) |
---|
506 | |
---|
507 | #elif defined(ppc603) |
---|
508 | #define PPC_IRQ_TRANS_MISS (PPC_STD_IRQ_LAST+1) /*0x1000-Ins Translation Miss*/ |
---|
509 | #define PPC_IRQ_DATA_LOAD (PPC_STD_IRQ_LAST+2) /*0x1100-Data Load Trans Miss*/ |
---|
510 | #define PPC_IRQ_DATA_STORE (PPC_STD_IRQ_LAST+3) /*0x1200-Data Store Miss */ |
---|
511 | #define PPC_IRQ_ADDR_BRK (PPC_STD_IRQ_LAST+4) /*0x1300-Instruction Bkpoint */ |
---|
512 | #define PPC_IRQ_SYS_MGT (PPC_STD_IRQ_LAST+5) /*0x1400-System Management */ |
---|
513 | #define PPC_IRQ_LAST PPC_IRQ_SYS_MGT |
---|
514 | |
---|
515 | #elif defined(ppc603e) |
---|
516 | #define PPC_TLB_INST_MISS (PPC_STD_IRQ_LAST+1) /*0x1000-Instruction TLB Miss*/ |
---|
517 | #define PPC_TLB_LOAD_MISS (PPC_STD_IRQ_LAST+2) /*0x1100-TLB miss on load */ |
---|
518 | #define PPC_TLB_STORE_MISS (PPC_STD_IRQ_LAST+3) /*0x1200-TLB Miss on store */ |
---|
519 | #define PPC_IRQ_ADDRBRK (PPC_STD_IRQ_LAST+4) /*0x1300-Instruct addr break */ |
---|
520 | #define PPC_IRQ_SYS_MGT (PPC_STD_IRQ_LAST+5) /*0x1400-System Management */ |
---|
521 | #define PPC_IRQ_LAST PPC_IRQ_SYS_MGT |
---|
522 | |
---|
523 | |
---|
524 | #elif defined(mpc604) |
---|
525 | #define PPC_IRQ_ADDR_BRK (PPC_STD_IRQ_LAST+1) /*0x1300- Inst. addr break */ |
---|
526 | #define PPC_IRQ_SYS_MGT (PPC_STD_IRQ_LAST+2) /*0x1400- System Management */ |
---|
527 | #define PPC_IRQ_LAST PPC_IRQ_SYS_MGT |
---|
528 | |
---|
529 | #elif defined(mpc860) || defined(mpc821) |
---|
530 | #define PPC_IRQ_EMULATE (PPC_STD_IRQ_LAST+1) /*0x1000-Software emulation */ |
---|
531 | #define PPC_IRQ_INST_MISS (PPC_STD_IRQ_LAST+2) /*0x1100-Instruction TLB miss*/ |
---|
532 | #define PPC_IRQ_DATA_MISS (PPC_STD_IRQ_LAST+3) /*0x1200-Data TLB miss */ |
---|
533 | #define PPC_IRQ_INST_ERR (PPC_STD_IRQ_LAST+4) /*0x1300-Instruction TLB err */ |
---|
534 | #define PPC_IRQ_DATA_ERR (PPC_STD_IRQ_LAST+5) /*0x1400-Data TLB error */ |
---|
535 | #define PPC_IRQ_DATA_BPNT (PPC_STD_IRQ_LAST+6) /*0x1C00-Data breakpoint */ |
---|
536 | #define PPC_IRQ_INST_BPNT (PPC_STD_IRQ_LAST+7) /*0x1D00-Inst breakpoint */ |
---|
537 | #define PPC_IRQ_IO_BPNT (PPC_STD_IRQ_LAST+8) /*0x1E00-Peripheral breakpnt */ |
---|
538 | #define PPC_IRQ_DEV_PORT (PPC_STD_IRQ_LAST+9) /*0x1F00-Development port */ |
---|
539 | #define PPC_IRQ_IRQ0 (PPC_STD_IRQ_LAST + 10) |
---|
540 | #define PPC_IRQ_LVL0 (PPC_STD_IRQ_LAST + 11) |
---|
541 | #define PPC_IRQ_IRQ1 (PPC_STD_IRQ_LAST + 12) |
---|
542 | #define PPC_IRQ_LVL1 (PPC_STD_IRQ_LAST + 13) |
---|
543 | #define PPC_IRQ_IRQ2 (PPC_STD_IRQ_LAST + 14) |
---|
544 | #define PPC_IRQ_LVL2 (PPC_STD_IRQ_LAST + 15) |
---|
545 | #define PPC_IRQ_IRQ3 (PPC_STD_IRQ_LAST + 16) |
---|
546 | #define PPC_IRQ_LVL3 (PPC_STD_IRQ_LAST + 17) |
---|
547 | #define PPC_IRQ_IRQ4 (PPC_STD_IRQ_LAST + 18) |
---|
548 | #define PPC_IRQ_LVL4 (PPC_STD_IRQ_LAST + 19) |
---|
549 | #define PPC_IRQ_IRQ5 (PPC_STD_IRQ_LAST + 20) |
---|
550 | #define PPC_IRQ_LVL5 (PPC_STD_IRQ_LAST + 21) |
---|
551 | #define PPC_IRQ_IRQ6 (PPC_STD_IRQ_LAST + 22) |
---|
552 | #define PPC_IRQ_LVL6 (PPC_STD_IRQ_LAST + 23) |
---|
553 | #define PPC_IRQ_IRQ7 (PPC_STD_IRQ_LAST + 24) |
---|
554 | #define PPC_IRQ_LVL7 (PPC_STD_IRQ_LAST + 25) |
---|
555 | #define PPC_IRQ_CPM_ERROR (PPC_STD_IRQ_LAST + 26) |
---|
556 | #define PPC_IRQ_CPM_PC4 (PPC_STD_IRQ_LAST + 27) |
---|
557 | #define PPC_IRQ_CPM_PC5 (PPC_STD_IRQ_LAST + 28) |
---|
558 | #define PPC_IRQ_CPM_SMC2 (PPC_STD_IRQ_LAST + 29) |
---|
559 | #define PPC_IRQ_CPM_SMC1 (PPC_STD_IRQ_LAST + 30) |
---|
560 | #define PPC_IRQ_CPM_SPI (PPC_STD_IRQ_LAST + 31) |
---|
561 | #define PPC_IRQ_CPM_PC6 (PPC_STD_IRQ_LAST + 32) |
---|
562 | #define PPC_IRQ_CPM_TIMER4 (PPC_STD_IRQ_LAST + 33) |
---|
563 | #define PPC_IRQ_CPM_RESERVED_8 (PPC_STD_IRQ_LAST + 34) |
---|
564 | #define PPC_IRQ_CPM_PC7 (PPC_STD_IRQ_LAST + 35) |
---|
565 | #define PPC_IRQ_CPM_PC8 (PPC_STD_IRQ_LAST + 36) |
---|
566 | #define PPC_IRQ_CPM_PC9 (PPC_STD_IRQ_LAST + 37) |
---|
567 | #define PPC_IRQ_CPM_TIMER3 (PPC_STD_IRQ_LAST + 38) |
---|
568 | #define PPC_IRQ_CPM_RESERVED_D (PPC_STD_IRQ_LAST + 39) |
---|
569 | #define PPC_IRQ_CPM_PC10 (PPC_STD_IRQ_LAST + 40) |
---|
570 | #define PPC_IRQ_CPM_PC11 (PPC_STD_IRQ_LAST + 41) |
---|
571 | #define PPC_IRQ_CPM_I2C (PPC_STD_IRQ_LAST + 42) |
---|
572 | #define PPC_IRQ_CPM_RISC_TIMER (PPC_STD_IRQ_LAST + 43) |
---|
573 | #define PPC_IRQ_CPM_TIMER2 (PPC_STD_IRQ_LAST + 44) |
---|
574 | #define PPC_IRQ_CPM_RESERVED_13 (PPC_STD_IRQ_LAST + 45) |
---|
575 | #define PPC_IRQ_CPM_IDMA2 (PPC_STD_IRQ_LAST + 46) |
---|
576 | #define PPC_IRQ_CPM_IDMA1 (PPC_STD_IRQ_LAST + 47) |
---|
577 | #define PPC_IRQ_CPM_SDMA_ERROR (PPC_STD_IRQ_LAST + 48) |
---|
578 | #define PPC_IRQ_CPM_PC12 (PPC_STD_IRQ_LAST + 49) |
---|
579 | #define PPC_IRQ_CPM_PC13 (PPC_STD_IRQ_LAST + 50) |
---|
580 | #define PPC_IRQ_CPM_TIMER1 (PPC_STD_IRQ_LAST + 51) |
---|
581 | #define PPC_IRQ_CPM_PC14 (PPC_STD_IRQ_LAST + 52) |
---|
582 | #define PPC_IRQ_CPM_SCC4 (PPC_STD_IRQ_LAST + 53) |
---|
583 | #define PPC_IRQ_CPM_SCC3 (PPC_STD_IRQ_LAST + 54) |
---|
584 | #define PPC_IRQ_CPM_SCC2 (PPC_STD_IRQ_LAST + 55) |
---|
585 | #define PPC_IRQ_CPM_SCC1 (PPC_STD_IRQ_LAST + 56) |
---|
586 | #define PPC_IRQ_CPM_PC15 (PPC_STD_IRQ_LAST + 57) |
---|
587 | |
---|
588 | #define PPC_IRQ_LAST PPC_IRQ_CPM_PC15 |
---|
589 | |
---|
590 | #endif |
---|
591 | |
---|
592 | /* |
---|
593 | * If the maximum number of exception sources is too low, |
---|
594 | * then fix it |
---|
595 | */ |
---|
596 | |
---|
597 | #if PPC_INTERRUPT_MAX <= PPC_IRQ_LAST |
---|
598 | #undef PPC_INTERRUPT_MAX |
---|
599 | #define PPC_INTERRUPT_MAX ((PPC_IRQ_LAST) + 1) |
---|
600 | #endif |
---|
601 | |
---|
602 | /* |
---|
603 | * Machine Status Register (MSR) Constants Used by RTEMS |
---|
604 | */ |
---|
605 | |
---|
606 | /* |
---|
607 | * Some PPC model manuals refer to the Exception Prefix (EP) bit as |
---|
608 | * IP for no apparent reason. |
---|
609 | */ |
---|
610 | |
---|
611 | #define PPC_MSR_RI 0x000000002 /* bit 30 - recoverable exception */ |
---|
612 | #define PPC_MSR_DR 0x000000010 /* bit 27 - data address translation */ |
---|
613 | #define PPC_MSR_IR 0x000000020 /* bit 26 - instruction addr translation*/ |
---|
614 | |
---|
615 | #if (PPC_HAS_EXCEPTION_PREFIX) |
---|
616 | #define PPC_MSR_EP 0x000000040 /* bit 25 - exception prefix */ |
---|
617 | #else |
---|
618 | #define PPC_MSR_EP 0x000000000 /* bit 25 - exception prefix */ |
---|
619 | #endif |
---|
620 | |
---|
621 | #if (PPC_HAS_FPU) |
---|
622 | #define PPC_MSR_FP 0x000002000 /* bit 18 - floating point enable */ |
---|
623 | #else |
---|
624 | #define PPC_MSR_FP 0x000000000 /* bit 18 - floating point enable */ |
---|
625 | #endif |
---|
626 | |
---|
627 | #if (PPC_LOW_POWER_MODE == PPC_LOW_POWER_MODE_NONE) |
---|
628 | #define PPC_MSR_POW 0x000000000 /* bit 13 - power management enable */ |
---|
629 | #else |
---|
630 | #define PPC_MSR_POW 0x000040000 /* bit 13 - power management enable */ |
---|
631 | #endif |
---|
632 | |
---|
633 | /* |
---|
634 | * Interrupt/exception MSR bits set as defined on p. 2-20 in "The Programming |
---|
635 | * Environments" and the manuals for various PPC models. |
---|
636 | */ |
---|
637 | |
---|
638 | #if (PPC_DEBUG_MODEL == PPC_DEBUG_MODEL_STANDARD) |
---|
639 | #define PPC_MSR_DE 0x000000000 /* bit 22 - debug exception enable */ |
---|
640 | #define PPC_MSR_BE 0x000000200 /* bit 22 - branch trace enable */ |
---|
641 | #define PPC_MSR_SE 0x000000400 /* bit 21 - single step trace enable */ |
---|
642 | #elif (PPC_DEBUG_MODEL == PPC_DEBUG_MODEL_SINGLE_STEP_ONLY) |
---|
643 | #define PPC_MSR_DE 0x000000000 /* bit 22 - debug exception enable */ |
---|
644 | #define PPC_MSR_BE 0x000000200 /* bit 22 - branch trace enable */ |
---|
645 | #define PPC_MSR_SE 0x000000000 /* bit 21 - single step trace enable */ |
---|
646 | #elif (PPC_DEBUG_MODEL == PPC_DEBUG_MODEL_IBM4xx) |
---|
647 | #define PPC_MSR_DE 0x000000200 /* bit 22 - debug exception enable */ |
---|
648 | #define PPC_MSR_BE 0x000000000 /* bit 22 - branch trace enable */ |
---|
649 | #define PPC_MSR_SE 0x000000000 /* bit 21 - single step trace enable */ |
---|
650 | #else |
---|
651 | #error "MSR constants -- unknown PPC_DEBUG_MODEL!!" |
---|
652 | #endif |
---|
653 | |
---|
654 | #define PPC_MSR_ME 0x000001000 /* bit 19 - machine check enable */ |
---|
655 | #define PPC_MSR_EE 0x000008000 /* bit 16 - external interrupt enable */ |
---|
656 | |
---|
657 | #if (PPC_HAS_RFCI) |
---|
658 | #define PPC_MSR_CE 0x000020000 /* bit 14 - critical interrupt enable */ |
---|
659 | #else |
---|
660 | #define PPC_MSR_CE 0x000000000 /* bit 14 - critical interrupt enable */ |
---|
661 | #endif |
---|
662 | |
---|
663 | #define PPC_MSR_DISABLE_MASK (PPC_MSR_ME|PPC_MSR_EE|PPC_MSR_CE) |
---|
664 | |
---|
665 | /* |
---|
666 | * Initial value for the FPSCR register |
---|
667 | */ |
---|
668 | |
---|
669 | #define PPC_INIT_FPSCR 0x000000f8 |
---|
670 | |
---|
671 | #ifdef __cplusplus |
---|
672 | } |
---|
673 | #endif |
---|
674 | |
---|
675 | #endif /* ! _INCLUDE_PPC_h */ |
---|
676 | /* end of include file */ |
---|
677 | |
---|
678 | |
---|