source: rtems/c/src/exec/score/cpu/powerpc/rtems/score/ppc.h @ ffcb102

4.104.114.84.95
Last change on this file since ffcb102 was ffcb102, checked in by Joel Sherrill <joel.sherrill@…>, on Nov 14, 2001 at 8:45:36 PM

2001-11-14 Joel Sherrill <joel@…>

  • shared/ppc.h: The mpc8260 uses the new exception processing model and thus does not need to define PPC_USE_SPRG.
  • Property mode set to 100644
File size: 24.2 KB
Line 
1/*  ppc.h
2 *
3 *  This file contains definitions for the IBM/Motorola PowerPC
4 *  family members.
5 *
6 *  Author:     Andrew Bray <andy@i-cubed.co.uk>
7 *
8 *  COPYRIGHT (c) 1995 by i-cubed ltd.
9 *
10 *  MPC860 support code was added by Jay Monkman <jmonkman@frasca.com>
11 *  MPC8260 support added by Andy Dachs <a.dachs@sstl.co.uk>
12 *  Surrey Satellite Technology Limited
13 *
14 *  To anyone who acknowledges that this file is provided "AS IS"
15 *  without any express or implied warranty:
16 *      permission to use, copy, modify, and distribute this file
17 *      for any purpose is hereby granted without fee, provided that
18 *      the above copyright notice and this notice appears in all
19 *      copies, and that the name of i-cubed limited not be used in
20 *      advertising or publicity pertaining to distribution of the
21 *      software without specific, written prior permission.
22 *      i-cubed limited makes no representations about the suitability
23 *      of this software for any purpose.
24 *
25 *  Derived from c/src/exec/cpu/no_cpu/no_cpu.h:
26 *
27 *  COPYRIGHT (c) 1989-1997.
28 *  On-Line Applications Research Corporation (OAR).
29 *
30 *  The license and distribution terms for this file may in
31 *  the file LICENSE in this distribution or at
32 *  http://www.OARcorp.com/rtems/license.html.
33 *
34 *
35 * Note:
36 *      This file is included by both C and assembler code ( -DASM )
37 *
38 *  $Id$
39 */
40
41
42#ifndef _INCLUDE_PPC_h
43#define _INCLUDE_PPC_h
44
45#ifdef __cplusplus
46extern "C" {
47#endif
48
49#include <rtems/score/ppctypes.h>
50
51/*
52 *  Define the name of the CPU family.
53 */
54
55#define CPU_NAME "PowerPC"
56
57/*
58 *  This file contains the information required to build
59 *  RTEMS for a particular member of the PowerPC family.  It does
60 *  this by setting variables to indicate which implementation
61 *  dependent features are present in a particular member
62 *  of the family.
63 *
64 *  The following architectural feature definitions are defaulted
65 *  unless specifically set by the model definition:
66 *
67 *    + PPC_DEBUG_MODEL          - PPC_DEBUG_MODEL_STANDARD
68 *    + PPC_INTERRUPT_MAX        - 16
69 *    + PPC_CACHE_ALIGNMENT      - 32
70 *    + PPC_LOW_POWER_MODE       - PPC_LOW_POWER_MODE_NONE
71 *    + PPC_HAS_EXCEPTION_PREFIX - 1
72 *    + PPC_HAS_FPU              - 1
73 *    + PPC_HAS_DOUBLE           - 1 if PPC_HAS_FPU,
74 *                               - 0 otherwise
75 *    + PPC_USE_MULTIPLE         - 0
76 */
77 
78/*
79 *  Define the debugging assistance models found in the PPC family.
80 *
81 *  Standard:         single step and branch trace
82 *  Single Step Only: single step only
83 *  IBM 4xx:          debug exception
84 */
85
86#define PPC_DEBUG_MODEL_STANDARD         1
87#define PPC_DEBUG_MODEL_SINGLE_STEP_ONLY 2
88#define PPC_DEBUG_MODEL_IBM4xx           3
89
90/*
91 *  Define the low power mode models
92 *
93 *  Standard:   as defined for 603e
94 *  Nap Mode:   nap mode only (604)
95 *  XXX 403GB, 603, 603e, 604, 821
96 */
97
98#define PPC_LOW_POWER_MODE_NONE      0
99#define PPC_LOW_POWER_MODE_STANDARD  1
100
101#if defined(rtems_multilib)
102/*
103 *  Figure out all CPU Model Feature Flags based upon compiler
104 *  predefines.
105 */
106
107#define CPU_MODEL_NAME           "rtems_multilib"
108#define PPC_ALIGNMENT            4 
109#define PPC_CACHE_ALIGNMENT      16
110#define PPC_HAS_RFCI             1
111#if defined(_SOFT_FLOAT)
112#define PPC_HAS_FPU              0
113#else
114#define PPC_HAS_FPU              1
115#endif
116
117#define PPC_USE_MULTIPLE         1
118#define PPC_I_CACHE              2048
119#define PPC_D_CACHE              1024
120#define PPC_DEBUG_MODEL          PPC_DEBUG_MODEL_STANDARD
121#define PPC_HAS_EXCEPTION_PREFIX 0
122#define PPC_HAS_EVPR             0
123#define PPC_INTERRUPT_MAX        16
124#define PPC_LOW_POWER_MODE       PPC_LOW_POWER_MODE_STANDARD
125#define PPC_HAS_DOUBLE           0
126
127#elif defined(ppc403) || defined(ppc405)
128/*
129 *  IBM 403
130 *
131 *  Developed for 403GA.  Book checked for 403GB.
132 *
133 *  Does not have user mode.
134 */
135 
136#if defined(ppc403)
137#define CPU_MODEL_NAME "PowerPC 403"
138#elif defined (ppc405)
139#define CPU_MODEL_NAME "PowerPC 405"
140#endif
141#define PPC_ALIGNMENT           4 
142#define PPC_CACHE_ALIGNMENT     16
143#define PPC_HAS_RFCI            1
144#define PPC_HAS_FPU             0
145#define PPC_USE_MULTIPLE        1
146#define PPC_I_CACHE             2048
147#define PPC_D_CACHE             1024
148
149#define PPC_DEBUG_MODEL          PPC_DEBUG_MODEL_IBM4xx
150#define PPC_HAS_EXCEPTION_PREFIX 0
151#define PPC_HAS_EVPR             1
152
153
154#elif defined(mpc505) || defined(mpc509)
155/*
156 *  Submitted by Sergei Organov <osv@Javad.RU> as a patch against
157 *  3.6.0 long after 4.0 was released.   This is just an attempt
158 *  to get the setting correct.
159 */
160
161#define CPU_MODEL_NAME  "PowerPC 505/509"
162
163#define PPC_ALIGNMENT           4
164#define PPC_CACHE_ALIGNMENT     16
165#define PPC_I_CACHE             4096
166#define PPC_D_CACHE             0
167
168
169#elif defined(ppc601)
170
171/*
172 *  Submitted with original port -- book checked only.
173 */
174 
175#define CPU_MODEL_NAME  "PowerPC 601"
176
177#define PPC_ALIGNMENT           8
178#define PPC_USE_MULTIPLE        1
179#define PPC_I_CACHE             0
180#define PPC_D_CACHE             32768
181
182#define PPC_DEBUG_MODEL PPC_DEBUG_MODEL_SINGLE_STEP_ONLY
183
184#elif defined(ppc602)
185/*
186 *  Submitted with original port -- book checked only.
187 */
188 
189#define CPU_MODEL_NAME  "PowerPC 602"
190
191#define PPC_ALIGNMENT           4
192#define PPC_HAS_DOUBLE          0
193#define PPC_I_CACHE             4096
194#define PPC_D_CACHE             4096
195
196#elif defined(ppc603)
197/*
198 *  Submitted with original port -- book checked only.
199 */
200 
201#define CPU_MODEL_NAME  "PowerPC 603"
202
203#define PPC_ALIGNMENT           8
204#define PPC_I_CACHE             8192
205#define PPC_D_CACHE             8192
206
207#elif defined(ppc603e)
208 
209#define CPU_MODEL_NAME  "PowerPC 603e"
210/*
211 *  Submitted with original port.
212 *
213 *  Known to work on real hardware.
214 */
215
216#define PPC_ALIGNMENT           8
217#define PPC_I_CACHE             16384
218#define PPC_D_CACHE             16384
219
220#define PPC_LOW_POWER_MODE PPC_LOW_POWER_MODE_STANDARD
221
222#elif defined(mpc604)
223/*
224 *  Submitted with original port -- book checked only.
225 */
226 
227#define CPU_MODEL_NAME  "PowerPC 604"
228
229#define PPC_ALIGNMENT           8
230#define PPC_I_CACHE             16384
231#define PPC_D_CACHE             16384
232 
233#elif defined(mpc860)
234/*
235 *  Added by Jay Monkman (jmonkman@frasca.com) 6/28/98
236 *  with some changes by Darlene Stewart (Darlene.Stewart@iit.nrc.ca)
237 */ 
238#define CPU_MODEL_NAME  "PowerPC MPC860"
239
240#define PPC_ALIGNMENT           4
241#define PPC_I_CACHE             4096
242#define PPC_D_CACHE             4096
243#define PPC_CACHE_ALIGNMENT     16
244#define PPC_INTERRUPT_MAX       71
245#define PPC_HAS_FPU             0
246#define PPC_HAS_DOUBLE          0
247#define PPC_USE_MULTIPLE        1
248
249#define PPC_MSR_0               0x00009000
250#define PPC_MSR_1               0x00001000
251#define PPC_MSR_2               0x00001000
252#define PPC_MSR_3               0x00000000
253
254#elif defined(mpc821)
255/*
256 *  Added by Andrew Bray <andy@chaos.org.uk> 6/April/1999
257 */ 
258#define CPU_MODEL_NAME  "PowerPC MPC821"
259
260#define PPC_ALIGNMENT           4
261#define PPC_I_CACHE             4096
262#define PPC_D_CACHE             4096
263#define PPC_CACHE_ALIGNMENT     16
264#define PPC_INTERRUPT_MAX       71
265#define PPC_HAS_FPU             0
266#define PPC_HAS_DOUBLE          0
267
268#define PPC_MSR_0               0x00009000
269#define PPC_MSR_1               0x00001000
270#define PPC_MSR_2               0x00001000
271#define PPC_MSR_3               0x00000000
272
273#elif defined(mpc750)
274
275#define CPU_MODEL_NAME  "PowerPC 750"
276
277#define PPC_ALIGNMENT           8
278#define PPC_I_CACHE             16384
279#define PPC_D_CACHE             16384
280
281#elif defined(mpc8260)
282/*
283 *  Added by Andy Dachs <a.dachs@sstl.co.uk> 23/11/2000
284 */
285#define CPU_MODEL_NAME  "PowerPC MPC8260"
286
287#define PPC_ALIGNMENT           4
288#define PPC_I_CACHE             16384
289#define PPC_D_CACHE             16384
290#define PPC_CACHE_ALIGNMENT     32
291#define PPC_INTERRUPT_MAX       125
292/*#define PPC_HAS_FPU           0 */    /* my 8260 is one the few with no FPU */
293#define PPC_HAS_FPU             1       /* the rest do have one */
294#define PPC_HAS_DOUBLE          1
295#define PPC_USE_MULTIPLE        1
296#else
297 
298#error "Unsupported CPU Model"
299 
300#endif
301
302/*
303 *  Application binary interfaces.
304 *
305 *  PPC_ABI MUST be defined as one of these.
306 *  Only PPC_ABI_POWEROPEN is currently fully supported.
307 *  Only EABI will be supported in the end when
308 *  the tools are there.
309 *  Only big endian is currently supported.
310 */
311/*
312 *  PowerOpen ABI.  This is Andy's hack of the
313 *  PowerOpen ABI to ELF.  ELF rather than a
314 *  XCOFF assembler is used.  This may work
315 *  if PPC_ASM == PPC_ASM_XCOFF is defined.
316 */
317#define PPC_ABI_POWEROPEN       0
318/*
319 *  GCC 2.7.0 munched version of EABI, with
320 *  PowerOpen calling convention and stack frames,
321 *  but EABI style indirect function calls.
322 */
323#define PPC_ABI_GCC27           1
324/*
325 *  SVR4 ABI
326 */
327#define PPC_ABI_SVR4            2
328/*
329 *  Embedded ABI
330 */
331#define PPC_ABI_EABI            3
332
333/*
334 *  Default to the EABI used by current GNU tools
335 */
336
337#ifndef PPC_ABI
338#define PPC_ABI PPC_ABI_EABI
339#endif
340
341#if (PPC_ABI == PPC_ABI_POWEROPEN)
342#define PPC_STACK_ALIGNMENT     8
343#elif (PPC_ABI == PPC_ABI_GCC27)
344#define PPC_STACK_ALIGNMENT     8
345#elif (PPC_ABI == PPC_ABI_SVR4)
346#define PPC_STACK_ALIGNMENT     16
347#elif (PPC_ABI == PPC_ABI_EABI)
348#define PPC_STACK_ALIGNMENT     8
349#else
350#error  "PPC_ABI is not properly defined"
351#endif
352#ifndef PPC_ABI
353#error  "PPC_ABI is not properly defined"
354#endif
355
356/*
357 *  Assemblers.
358 *  PPC_ASM MUST be defined as one of these.
359 *
360 *  PPC_ASM_ELF:   ELF assembler. Currently used for all ABIs.
361 *  PPC_ASM_XCOFF: XCOFF assembler. May be needed for PowerOpen ABI.
362 *
363 *  NOTE: Only PPC_ABI_ELF is currently fully supported.
364 */
365
366#define PPC_ASM_ELF   0
367#define PPC_ASM_XCOFF 1
368
369/*
370 *  Default to the assembler format used by the current GNU tools.
371 */
372
373#ifndef PPC_ASM
374#define PPC_ASM PPC_ASM_ELF
375#endif
376
377/*
378 *  Use the default debug scheme defined in the architectural specification
379 *  if another model has not been specified.
380 */
381
382#ifndef PPC_DEBUG_MODEL
383#define PPC_DEBUG_MODEL PPC_DEBUG_MODEL_STANDARD
384#endif
385
386/*
387 *  If the maximum number of exception sources has not been defined,
388 *  then default it to 16.
389 */
390
391#ifndef PPC_INTERRUPT_MAX
392#define PPC_INTERRUPT_MAX       16
393#endif
394
395/*
396 *  Unless specified otherwise, the cache line size is defaulted to 32.
397 *
398 *  The derive the power of 2 the cache line is.
399 */
400
401#ifndef PPC_CACHE_ALIGNMENT
402#define PPC_CACHE_ALIGNMENT 32
403#endif
404
405#if (PPC_CACHE_ALIGNMENT == 16)
406#define PPC_CACHE_ALIGN_POWER 4
407#elif (PPC_CACHE_ALIGNMENT == 32)
408#define PPC_CACHE_ALIGN_POWER 5
409#else
410#error "Undefined power of 2 for PPC_CACHE_ALIGNMENT"
411#endif
412
413/*
414 *  Unless otherwise specified, assume the model has an IP/EP bit to
415 *  set the exception address prefix.
416 */
417
418#ifndef PPC_HAS_EXCEPTION_PREFIX
419#define PPC_HAS_EXCEPTION_PREFIX 1
420#endif
421
422/*
423 *  Unless otherwise specified, assume the model does NOT have
424 *  403 style EVPR register to set the exception address prefix.
425 */
426
427#ifndef PPC_HAS_EVPR
428#define PPC_HAS_EVPR 0
429#endif
430
431/*
432 *  If no low power mode model was specified, then assume there is none.
433 */
434
435#ifndef PPC_LOW_POWER_MODE
436#define PPC_LOW_POWER_MODE PPC_LOW_POWER_MODE_NONE
437#endif
438
439/*
440 *  Unless specified above, then assume the model has FP support.
441 */
442
443#ifndef PPC_HAS_FPU
444#define PPC_HAS_FPU 1
445#endif
446
447/*
448 *  Unless specified above, If the model has FP support, it is assumed to
449 *  support doubles (8-byte floating point numbers).
450 *
451 *  If the model does NOT have FP support, then the model does
452 *  NOT have double length FP registers.
453 */
454
455#ifndef PPC_HAS_DOUBLE
456#if (PPC_HAS_FPU)
457#define PPC_HAS_DOUBLE 1
458#else
459#define PPC_HAS_DOUBLE 0
460#endif
461#endif
462
463/*
464 *  Unless specified above, then assume the model does NOT have critical
465 *  interrupt support.
466 */
467
468#ifndef PPC_HAS_RFCI
469#define PPC_HAS_RFCI 0
470#endif
471
472/*
473 *  Unless specified above, do not use the load/store multiple instructions
474 *  in a context switch.
475 */
476
477#ifndef PPC_USE_MULTIPLE
478#define PPC_USE_MULTIPLE 0
479#endif
480
481/*
482 *  The following exceptions are not maskable, and are not
483 *  necessarily predictable, so cannot be offered to RTEMS:
484 *    Alignment exception - handled by the CPU module
485 *    Data exceptions.
486 *    Instruction exceptions.
487 */
488
489/*
490 *  Base Interrupt vectors supported on all models.
491 */
492#define PPC_IRQ_SYSTEM_RESET     0 /* 0x00100 - System reset.              */
493#define PPC_IRQ_MCHECK           1 /* 0x00200 - Machine check              */
494#define PPC_IRQ_PROTECT          2 /* 0x00300 - Protection violation       */
495#define PPC_IRQ_ISI              3 /* 0x00400 - Instruction Fetch error    */
496#define PPC_IRQ_EXTERNAL         4 /* 0x00500 - External interrupt         */
497#define PPC_IRQ_ALIGNMENT        5 /* 0X00600 - Alignment exception        */
498#define PPC_IRQ_PROGRAM          6 /* 0x00700 - Program exception          */
499#define PPC_IRQ_NOFP             7 /* 0x00800 - Floating point unavailable */
500#define PPC_IRQ_DECREMENTER      8 /* 0x00900 - Decrementer interrupt      */
501#define PPC_IRQ_RESERVED_A       9 /* 0x00a00 - Implementation Reserved    */
502#define PPC_IRQ_RESERVED_B      10 /* 0x00b00 - Implementation Reserved    */
503#define PPC_IRQ_SCALL           11 /* 0x00c00 - System call                */
504#define PPC_IRQ_TRACE           12 /* 0x00d00 - Trace Exception            */
505#define PPC_IRQ_FP_ASST         13 /* ox00e00 - Floating point assist      */
506#define PPC_STD_IRQ_LAST        PPC_IRQ_FP_ASST
507
508#define PPC_IRQ_FIRST           PPC_IRQ_SYSTEM_RESET
509
510#if defined(ppc403) || defined(ppc405)
511                                 
512#define PPC_IRQ_CRIT     PPC_IRQ_SYSTEM_RESET /*0x00100- Critical int. pin */
513#define PPC_IRQ_PIT      (PPC_STD_IRQ_LAST+1) /*0x01000- Pgm interval timer*/
514#define PPC_IRQ_FIT      (PPC_STD_IRQ_LAST+2) /*0x01010- Fixed int. timer  */
515#define PPC_IRQ_WATCHDOG (PPC_STD_IRQ_LAST+3) /*0x01020- Watchdog timer    */
516#define PPC_IRQ_DEBUG    (PPC_STD_IRQ_LAST+4) /*0x02000- Debug exceptions  */
517#define PPC_IRQ_LAST     PPC_IRQ_DEBUG
518
519#elif defined(mpc505) || defined(mpc509)
520#define PPC_IRQ_SOFTEMU   (PPC_STD_IRQ_LAST+1)    /* Software emulation. */
521#define PPC_IRQ_DATA_BP   (PPC_STD_IRQ_LAST+ 2)
522#define PPC_IRQ_INST_BP   (PPC_STD_IRQ_LAST+ 3)
523#define PPC_IRQ_MEXT_BP   (PPC_STD_IRQ_LAST+ 4)
524#define PPC_IRQ_NMEXT_BP  (PPC_STD_IRQ_LAST+ 5)
525
526#elif defined(ppc601)
527#define PPC_IRQ_TRACE    (PPC_STD_IRQ_LAST+1) /*0x02000-Run/Trace Exception*/
528#define PPC_IRQ_LAST     PPC_IRQ_TRACE       
529
530#elif defined(ppc602)
531#define PPC_IRQ_LAST     (PPC_STD_IRQ_LAST)
532
533#elif defined(ppc603)
534#define PPC_IRQ_TRANS_MISS (PPC_STD_IRQ_LAST+1) /*0x1000-Ins Translation Miss*/
535#define PPC_IRQ_DATA_LOAD  (PPC_STD_IRQ_LAST+2) /*0x1100-Data Load Trans Miss*/
536#define PPC_IRQ_DATA_STORE (PPC_STD_IRQ_LAST+3) /*0x1200-Data Store Miss     */
537#define PPC_IRQ_ADDR_BRK   (PPC_STD_IRQ_LAST+4) /*0x1300-Instruction Bkpoint */
538#define PPC_IRQ_SYS_MGT    (PPC_STD_IRQ_LAST+5) /*0x1400-System Management   */
539#define PPC_IRQ_LAST       PPC_IRQ_SYS_MGT   
540
541#elif defined(ppc603e)
542#define PPC_TLB_INST_MISS  (PPC_STD_IRQ_LAST+1) /*0x1000-Instruction TLB Miss*/
543#define PPC_TLB_LOAD_MISS  (PPC_STD_IRQ_LAST+2) /*0x1100-TLB miss on load  */
544#define PPC_TLB_STORE_MISS (PPC_STD_IRQ_LAST+3) /*0x1200-TLB Miss on store */
545#define PPC_IRQ_ADDRBRK    (PPC_STD_IRQ_LAST+4) /*0x1300-Instruct addr break */
546#define PPC_IRQ_SYS_MGT    (PPC_STD_IRQ_LAST+5) /*0x1400-System Management   */
547#define PPC_IRQ_LAST       PPC_IRQ_SYS_MGT   
548
549
550#elif defined(mpc604)
551#define PPC_IRQ_ADDR_BRK (PPC_STD_IRQ_LAST+1) /*0x1300- Inst. addr break  */
552#define PPC_IRQ_SYS_MGT  (PPC_STD_IRQ_LAST+2) /*0x1400- System Management */
553#define PPC_IRQ_LAST     PPC_IRQ_SYS_MGT 
554
555#elif defined(mpc860) || defined(mpc821)
556#define PPC_IRQ_EMULATE         (PPC_STD_IRQ_LAST+1) /*0x1000-Software emulation  */
557#define PPC_IRQ_INST_MISS       (PPC_STD_IRQ_LAST+2) /*0x1100-Instruction TLB miss*/
558#define PPC_IRQ_DATA_MISS       (PPC_STD_IRQ_LAST+3) /*0x1200-Data TLB miss */
559#define PPC_IRQ_INST_ERR        (PPC_STD_IRQ_LAST+4) /*0x1300-Instruction TLB err */
560#define PPC_IRQ_DATA_ERR        (PPC_STD_IRQ_LAST+5) /*0x1400-Data TLB error */
561#define PPC_IRQ_DATA_BPNT       (PPC_STD_IRQ_LAST+6) /*0x1C00-Data breakpoint */
562#define PPC_IRQ_INST_BPNT       (PPC_STD_IRQ_LAST+7) /*0x1D00-Inst breakpoint */
563#define PPC_IRQ_IO_BPNT         (PPC_STD_IRQ_LAST+8) /*0x1E00-Peripheral breakpnt */
564#define PPC_IRQ_DEV_PORT        (PPC_STD_IRQ_LAST+9) /*0x1F00-Development port */
565#define PPC_IRQ_IRQ0            (PPC_STD_IRQ_LAST + 10)
566#define PPC_IRQ_LVL0            (PPC_STD_IRQ_LAST + 11)
567#define PPC_IRQ_IRQ1            (PPC_STD_IRQ_LAST + 12)
568#define PPC_IRQ_LVL1            (PPC_STD_IRQ_LAST + 13)
569#define PPC_IRQ_IRQ2            (PPC_STD_IRQ_LAST + 14)
570#define PPC_IRQ_LVL2            (PPC_STD_IRQ_LAST + 15)
571#define PPC_IRQ_IRQ3            (PPC_STD_IRQ_LAST + 16)
572#define PPC_IRQ_LVL3            (PPC_STD_IRQ_LAST + 17)
573#define PPC_IRQ_IRQ4            (PPC_STD_IRQ_LAST + 18)
574#define PPC_IRQ_LVL4            (PPC_STD_IRQ_LAST + 19)
575#define PPC_IRQ_IRQ5            (PPC_STD_IRQ_LAST + 20)
576#define PPC_IRQ_LVL5            (PPC_STD_IRQ_LAST + 21)
577#define PPC_IRQ_IRQ6            (PPC_STD_IRQ_LAST + 22)
578#define PPC_IRQ_LVL6            (PPC_STD_IRQ_LAST + 23)
579#define PPC_IRQ_IRQ7            (PPC_STD_IRQ_LAST + 24)
580#define PPC_IRQ_LVL7            (PPC_STD_IRQ_LAST + 25)
581#define PPC_IRQ_CPM_ERROR       (PPC_STD_IRQ_LAST + 26)
582#define PPC_IRQ_CPM_PC4         (PPC_STD_IRQ_LAST + 27)
583#define PPC_IRQ_CPM_PC5         (PPC_STD_IRQ_LAST + 28)
584#define PPC_IRQ_CPM_SMC2        (PPC_STD_IRQ_LAST + 29)
585#define PPC_IRQ_CPM_SMC1        (PPC_STD_IRQ_LAST + 30)
586#define PPC_IRQ_CPM_SPI         (PPC_STD_IRQ_LAST + 31)
587#define PPC_IRQ_CPM_PC6         (PPC_STD_IRQ_LAST + 32)
588#define PPC_IRQ_CPM_TIMER4      (PPC_STD_IRQ_LAST + 33)
589#define PPC_IRQ_CPM_RESERVED_8  (PPC_STD_IRQ_LAST + 34)
590#define PPC_IRQ_CPM_PC7         (PPC_STD_IRQ_LAST + 35)
591#define PPC_IRQ_CPM_PC8         (PPC_STD_IRQ_LAST + 36)
592#define PPC_IRQ_CPM_PC9         (PPC_STD_IRQ_LAST + 37)
593#define PPC_IRQ_CPM_TIMER3      (PPC_STD_IRQ_LAST + 38)
594#define PPC_IRQ_CPM_RESERVED_D  (PPC_STD_IRQ_LAST + 39)
595#define PPC_IRQ_CPM_PC10        (PPC_STD_IRQ_LAST + 40)
596#define PPC_IRQ_CPM_PC11        (PPC_STD_IRQ_LAST + 41)
597#define PPC_IRQ_CPM_I2C         (PPC_STD_IRQ_LAST + 42)
598#define PPC_IRQ_CPM_RISC_TIMER  (PPC_STD_IRQ_LAST + 43)
599#define PPC_IRQ_CPM_TIMER2      (PPC_STD_IRQ_LAST + 44)
600#define PPC_IRQ_CPM_RESERVED_13 (PPC_STD_IRQ_LAST + 45)
601#define PPC_IRQ_CPM_IDMA2       (PPC_STD_IRQ_LAST + 46)
602#define PPC_IRQ_CPM_IDMA1       (PPC_STD_IRQ_LAST + 47)
603#define PPC_IRQ_CPM_SDMA_ERROR  (PPC_STD_IRQ_LAST + 48)
604#define PPC_IRQ_CPM_PC12        (PPC_STD_IRQ_LAST + 49)
605#define PPC_IRQ_CPM_PC13        (PPC_STD_IRQ_LAST + 50)
606#define PPC_IRQ_CPM_TIMER1      (PPC_STD_IRQ_LAST + 51)
607#define PPC_IRQ_CPM_PC14        (PPC_STD_IRQ_LAST + 52)
608#define PPC_IRQ_CPM_SCC4        (PPC_STD_IRQ_LAST + 53)
609#define PPC_IRQ_CPM_SCC3        (PPC_STD_IRQ_LAST + 54)
610#define PPC_IRQ_CPM_SCC2        (PPC_STD_IRQ_LAST + 55)
611#define PPC_IRQ_CPM_SCC1        (PPC_STD_IRQ_LAST + 56)
612#define PPC_IRQ_CPM_PC15        (PPC_STD_IRQ_LAST + 57)
613
614#define PPC_IRQ_LAST             PPC_IRQ_CPM_PC15
615
616#elif defined(mpc8260)
617
618#define PPC_IRQ_INST_MISS       (PPC_STD_IRQ_LAST+1) /*0x1000-Instruction TLB miss*/
619#define PPC_IRQ_DATA_MISS       (PPC_STD_IRQ_LAST+2) /*0x1100-Data TLB miss */
620#define PPC_IRQ_DATA_L_MISS     (PPC_STD_IRQ_LAST+3) /*0x1200-Data TLB load miss */
621#define PPC_IRQ_DATA_S_MISS     (PPC_STD_IRQ_LAST+4) /*0x1300-Data TLB store miss */
622#define PPC_IRQ_INST_BPNT       (PPC_STD_IRQ_LAST+5) /*0x1400-Inst address breakpoint */
623#define PPC_IRQ_SYS_MGT         (PPC_STD_IRQ_LAST+6) /*0x1500-System Management */
624/* 0x1600 - 0x2F00 reserved */
625#define PPC_IRQ_CPM_NONE        (PPC_STD_IRQ_LAST + 50)
626#define PPC_IRQ_CPM_I2C         (PPC_STD_IRQ_LAST + 51)
627#define PPC_IRQ_CPM_SPI         (PPC_STD_IRQ_LAST + 52)
628#define PPC_IRQ_CPM_RISC_TIMER  (PPC_STD_IRQ_LAST + 53)
629#define PPC_IRQ_CPM_SMC1        (PPC_STD_IRQ_LAST + 54)
630#define PPC_IRQ_CPM_SMC2        (PPC_STD_IRQ_LAST + 55)
631#define PPC_IRQ_CPM_IDMA1       (PPC_STD_IRQ_LAST + 56)
632#define PPC_IRQ_CPM_IDMA2       (PPC_STD_IRQ_LAST + 57)
633#define PPC_IRQ_CPM_IDMA3       (PPC_STD_IRQ_LAST + 58)
634#define PPC_IRQ_CPM_IDMA4       (PPC_STD_IRQ_LAST + 59)
635#define PPC_IRQ_CPM_SDMA        (PPC_STD_IRQ_LAST + 60)
636#define PPC_IRQ_CPM_RES_A       (PPC_STD_IRQ_LAST + 61)
637#define PPC_IRQ_CPM_TIMER1      (PPC_STD_IRQ_LAST + 62)
638#define PPC_IRQ_CPM_TIMER2      (PPC_STD_IRQ_LAST + 63)
639#define PPC_IRQ_CPM_TIMER3      (PPC_STD_IRQ_LAST + 64)
640#define PPC_IRQ_CPM_TIMER4      (PPC_STD_IRQ_LAST + 65)
641#define PPC_IRQ_CPM_TMCNT       (PPC_STD_IRQ_LAST + 66)
642#define PPC_IRQ_CPM_PIT         (PPC_STD_IRQ_LAST + 67)
643#define PPC_IRQ_CPM_RES_B       (PPC_STD_IRQ_LAST + 68)
644#define PPC_IRQ_CPM_IRQ1        (PPC_STD_IRQ_LAST + 69)
645#define PPC_IRQ_CPM_IRQ2        (PPC_STD_IRQ_LAST + 70)
646#define PPC_IRQ_CPM_IRQ3        (PPC_STD_IRQ_LAST + 71)
647#define PPC_IRQ_CPM_IRQ4        (PPC_STD_IRQ_LAST + 72)
648#define PPC_IRQ_CPM_IRQ5        (PPC_STD_IRQ_LAST + 73)
649#define PPC_IRQ_CPM_IRQ6        (PPC_STD_IRQ_LAST + 74)
650#define PPC_IRQ_CPM_IRQ7        (PPC_STD_IRQ_LAST + 75)
651#define PPC_IRQ_CPM_RES_C       (PPC_STD_IRQ_LAST + 76)
652#define PPC_IRQ_CPM_RES_D       (PPC_STD_IRQ_LAST + 77)
653#define PPC_IRQ_CPM_RES_E       (PPC_STD_IRQ_LAST + 78)
654#define PPC_IRQ_CPM_RES_F       (PPC_STD_IRQ_LAST + 79)
655#define PPC_IRQ_CPM_RES_G       (PPC_STD_IRQ_LAST + 80)
656#define PPC_IRQ_CPM_RES_H       (PPC_STD_IRQ_LAST + 81)
657#define PPC_IRQ_CPM_FCC1        (PPC_STD_IRQ_LAST + 82)
658#define PPC_IRQ_CPM_FCC2        (PPC_STD_IRQ_LAST + 83)
659#define PPC_IRQ_CPM_FCC3        (PPC_STD_IRQ_LAST + 84)
660#define PPC_IRQ_CPM_RES_I       (PPC_STD_IRQ_LAST + 85)
661#define PPC_IRQ_CPM_MCC1        (PPC_STD_IRQ_LAST + 86)
662#define PPC_IRQ_CPM_MCC2        (PPC_STD_IRQ_LAST + 87)
663#define PPC_IRQ_CPM_RES_J       (PPC_STD_IRQ_LAST + 88)
664#define PPC_IRQ_CPM_RES_K       (PPC_STD_IRQ_LAST + 89)
665#define PPC_IRQ_CPM_SCC1        (PPC_STD_IRQ_LAST + 90)
666#define PPC_IRQ_CPM_SCC2        (PPC_STD_IRQ_LAST + 91)
667#define PPC_IRQ_CPM_SCC3        (PPC_STD_IRQ_LAST + 92)
668#define PPC_IRQ_CPM_SCC4        (PPC_STD_IRQ_LAST + 93)
669#define PPC_IRQ_CPM_RES_L       (PPC_STD_IRQ_LAST + 94)
670#define PPC_IRQ_CPM_RES_M       (PPC_STD_IRQ_LAST + 95)
671#define PPC_IRQ_CPM_RES_N       (PPC_STD_IRQ_LAST + 96)
672#define PPC_IRQ_CPM_RES_O       (PPC_STD_IRQ_LAST + 97)
673#define PPC_IRQ_CPM_PC15        (PPC_STD_IRQ_LAST + 98)
674#define PPC_IRQ_CPM_PC14        (PPC_STD_IRQ_LAST + 99)
675#define PPC_IRQ_CPM_PC13        (PPC_STD_IRQ_LAST + 100)
676#define PPC_IRQ_CPM_PC12        (PPC_STD_IRQ_LAST + 101)
677#define PPC_IRQ_CPM_PC11        (PPC_STD_IRQ_LAST + 102)
678#define PPC_IRQ_CPM_PC10        (PPC_STD_IRQ_LAST + 103)
679#define PPC_IRQ_CPM_PC9         (PPC_STD_IRQ_LAST + 104)
680#define PPC_IRQ_CPM_PC8         (PPC_STD_IRQ_LAST + 105)
681#define PPC_IRQ_CPM_PC7         (PPC_STD_IRQ_LAST + 106)
682#define PPC_IRQ_CPM_PC6         (PPC_STD_IRQ_LAST + 107)
683#define PPC_IRQ_CPM_PC5         (PPC_STD_IRQ_LAST + 108)
684#define PPC_IRQ_CPM_PC4         (PPC_STD_IRQ_LAST + 109)
685#define PPC_IRQ_CPM_PC3         (PPC_STD_IRQ_LAST + 110)
686#define PPC_IRQ_CPM_PC2         (PPC_STD_IRQ_LAST + 111)
687#define PPC_IRQ_CPM_PC1         (PPC_STD_IRQ_LAST + 112)
688#define PPC_IRQ_CPM_PC0         (PPC_STD_IRQ_LAST + 113)
689
690#define PPC_IRQ_LAST             PPC_IRQ_CPM_PC0
691
692#endif
693
694
695/*
696 *  If the maximum number of exception sources is too low,
697 *  then fix it
698 */
699
700#if PPC_INTERRUPT_MAX <= PPC_IRQ_LAST
701#undef PPC_INTERRUPT_MAX
702#define PPC_INTERRUPT_MAX ((PPC_IRQ_LAST) + 1)
703#endif
704
705/*
706 *  Machine Status Register (MSR) Constants Used by RTEMS
707 */
708
709/*
710 *  Some PPC model manuals refer to the Exception Prefix (EP) bit as
711 *  IP for no apparent reason.
712 */
713
714#define PPC_MSR_RI       0x000000002 /* bit 30 - recoverable exception */
715#define PPC_MSR_DR       0x000000010 /* bit 27 - data address translation */
716#define PPC_MSR_IR       0x000000020 /* bit 26 - instruction addr translation*/
717
718#if (PPC_HAS_EXCEPTION_PREFIX)
719#define PPC_MSR_EP       0x000000040 /* bit 25 - exception prefix */
720#else
721#define PPC_MSR_EP       0x000000000 /* bit 25 - exception prefix */
722#endif
723
724#if (PPC_HAS_FPU)
725#define PPC_MSR_FP       0x000002000 /* bit 18 - floating point enable */
726#else
727#define PPC_MSR_FP       0x000000000 /* bit 18 - floating point enable */
728#endif
729
730#if (PPC_LOW_POWER_MODE == PPC_LOW_POWER_MODE_NONE)
731#define PPC_MSR_POW      0x000000000 /* bit 13 - power management enable */
732#else
733#define PPC_MSR_POW      0x000040000 /* bit 13 - power management enable */
734#endif
735
736/*
737 *  Interrupt/exception MSR bits set as defined on p. 2-20 in "The Programming
738 *  Environments" and the manuals for various PPC models.
739 */
740
741#if (PPC_DEBUG_MODEL == PPC_DEBUG_MODEL_STANDARD)
742#define PPC_MSR_DE       0x000000000 /* bit 22 - debug exception enable */
743#define PPC_MSR_BE       0x000000200 /* bit 22 - branch trace enable */
744#define PPC_MSR_SE       0x000000400 /* bit 21 - single step trace enable */
745#elif (PPC_DEBUG_MODEL == PPC_DEBUG_MODEL_SINGLE_STEP_ONLY)
746#define PPC_MSR_DE       0x000000000 /* bit 22 - debug exception enable */
747#define PPC_MSR_BE       0x000000200 /* bit 22 - branch trace enable */
748#define PPC_MSR_SE       0x000000000 /* bit 21 - single step trace enable */
749#elif (PPC_DEBUG_MODEL == PPC_DEBUG_MODEL_IBM4xx)
750#define PPC_MSR_DE       0x000000200 /* bit 22 - debug exception enable */
751#define PPC_MSR_BE       0x000000000 /* bit 22 - branch trace enable */
752#define PPC_MSR_SE       0x000000000 /* bit 21 - single step trace enable */
753#else
754#error "MSR constants -- unknown PPC_DEBUG_MODEL!!"
755#endif
756
757#define PPC_MSR_ME       0x000001000 /* bit 19 - machine check enable */
758#define PPC_MSR_EE       0x000008000 /* bit 16 - external interrupt enable */
759
760#if (PPC_HAS_RFCI)
761#define PPC_MSR_CE       0x000020000 /* bit 14 - critical interrupt enable */
762#else
763#define PPC_MSR_CE       0x000000000 /* bit 14 - critical interrupt enable */
764#endif
765
766#define PPC_MSR_DISABLE_MASK (PPC_MSR_ME|PPC_MSR_EE|PPC_MSR_CE)
767
768/*
769 *  Initial value for the FPSCR register
770 */
771
772#define PPC_INIT_FPSCR          0x000000f8
773
774#ifdef __cplusplus
775}
776#endif
777
778#endif /* ! _INCLUDE_PPC_h */
779/* end of include file */
780
781
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