source: rtems/c/src/exec/score/cpu/powerpc/rtems/score/ppc.h @ ba46ffa6

4.104.114.84.95
Last change on this file since ba46ffa6 was ba46ffa6, checked in by Joel Sherrill <joel.sherrill@…>, on Jun 14, 1999 at 4:51:13 PM

This is a large patch from Eric Valette <valette@…> that was
described in the message following this paragraph. This patch also includes
a mcp750 BSP.

From valette@… Mon Jun 14 10:03:08 1999
Date: Tue, 18 May 1999 01:30:14 +0200 (CEST)
From: VALETTE Eric <valette@…>
To: joel@…
Cc: raguet@…, rtems-snapshots@…, valette@…
Subject: Questions/Suggestion? regarding RTEMS PowerPC code (long)

Dear knowledgeable RTEMS powerpc users,

As some of you may know, I'm currently finalizing a port
of RTEMS on a MCP750 Motorola board. I have done most
of it but have some questions to ask before submitting
the port.

In order to understand some of the changes I have made
or would like to make, maybe it is worth describing the
MCP750 Motorola board.

the MCP750 is a COMPACT PCI powerpc board with :

1) a MPC750 233 MHz processor,
2) a raven bus bridge/PCI controller that
implement an OPENPIC compliant interrupt controller,
3) a VIA 82C586 PCI/ISA bridge that offers a PC
compliant IO for keyboard, serial line, IDE, and
the well known PC 8259 cascaded PIC interrupt
architecture model,
4) a DEC 21140 Ethernet controller,
5) the PPCBUG Motorola firmware in flash,
6) A DEC PCI bridge,

This architecture is common to most Motorola 60x/7xx
board except that :

1) on VME board, the DEC PCI bridge is replaced by
a VME chipset,
2) the VIA 82C586 PCI/ISA bridge is replaced by
another bridge that is almost fully compatible
with the via bridge...

So the port should be a rather close basis for many
60x/7xx motorola board...

On this board, I already have ported Linux 2.2.3 and
use it both as a development and target board.

Now the questions/suggestions I have :

1) EXCEPTION CODE


As far as I know exceptions on PPC are handled like
interrupts. I dislike this very much as :

a) Except for the decrementer exception (and
maybe some other on mpc8xx), exceptions are
not recoverable and the handler just need to print
the full context and go to the firmware or debugger...
b) The interrupt switch is only necessary for the
decrementer and external interrupt (at least on
6xx,7xx).
c) The full context for exception is never saved and
thus cannot be used by debugger... I do understand
the most important for interrupts low level code
is to save the minimal context enabling to call C
code for performance reasons. On non recoverable
exception on the other hand, the most important is
to save the maximum information concerning proc status
in order to analyze the reason of the fault. At
least we will need this in order to implement the
port of RGDB on PPC

==> I wrote an API for connecting raw exceptions (and thus
raw interrupts) for mpc750. It should be valid for most
powerpc processors... I hope to find a way to make this coexist
with actual code layout. The code is actually located
in lib/libcpu/powerpc/mpc750 and is thus optional
(provided I write my own version of exec/score/cpu/powerpc/cpu.c ...)

See remark about files/directory layout organization in 4)

2) Current Implementation of ISR low level code


I do not understand why the MSR EE flags is cleared
again in exec/score/cpu/powerpc/irq_stubs.S

#if (PPC_USE_SPRG)

mfmsr r5
mfspr r6, sprg2

#else

lwz r6,msr_initial(r11)
lis r5,~PPC_MSR_DISABLE_MASK@ha
ori r5,r5,~PPC_MSR_DISABLE_MASK@l
and r6,r6,r5
mfmsr r5

#endif

Reading the doc, when a decrementer interrupt or an
external interrupt is active, the MSR EE flag is already
cleared. BTW if exception/interrupt could occur, it would
trash SRR0 and SRR1. In fact the code may be useful to set
MSR[RI] that re-enables exception processing. BTW I will need
to set other value in MSR to handle interrupts :

a) I want the MSR[IR] and MSR[DR] to be set for
performance reasons and also because I need DBAT
support to have access to PCI memory space as the
interrupt controller is in the PCI space.

Reading the code, I see others have the same kind of request :

/* SCE 980217

*

  • We need address translation ON when we call our ISR routine

mtmsr r5

*/

This is just another prof that even the lowest level
IRQ code is fundamentally board dependent and
not simply processor dependent especially when
the processor use external interrupt controller
because it has a single interrupt request line...

Note that if you look at the PPC code high level interrupt
handling code, as the "set_vector" routine that really connects
the interrupt is in the BSP/startup/genpvec.c,
the fact that IRQ handling is BSP specific is DE-FACTO
acknowledged.

I know I have already expressed this and understand that this
would require some heavy change in the code but believe
me you will reach a point where you will not be able
to find a compatible while optimum implementation for low level
interrupt handling code...) In my case this is already true...

So please consider removing low level IRQ handling from
exec/score/cpu/* and only let there exception handling code...
Exceptions are usually only processor dependent and do
not depend on external hardware mechanism to be masked or
acknowledged or re-enabled (there are probably exception but ...)

I have already done this for pc386 bsp but need to make it again.
This time I will even propose an API.

3) R2/R13 manipulation for EABI implementation


I do not understand the handling of r2 and r13 in the
EABI case. The specification for r2 says pointer to sdata2,
sbss2 section => constant. However I do not see -ffixed-r2
passed to any compilation system in make/custom/*
(for info linux does this on PPC).

So either this is a default compiler option when choosing
powerpc-rtems and thus we do not need to do anything with
this register as all the code is compiled with this compiler
and linked together OR this register may be used by rtems code
and then we do not need any special initialization or
handling.

The specification for r13 says pointer to the small data
area. r13 argumentation is the same except that as far
as I know the usage of the small data area requires
specific compiler support so that access to variables is
compiled via loading the LSB in a register and then
using r13 to get full address... It is like a small
memory model and it was present in IBM C compilers.

=> I propose to suppress any specific code for r2 and
r13 in the EABI case.

4) Code layout organization (yes again :-))


I think there are a number of design flaws in the way
the code is for ppc organized and I will try to point them out.
I have been beaten by this again on this new port, and
was beaten last year while modifying code for pc386.

a) exec/score/cpu/* vs lib/libcpu/cpu/*.

I think that too many things are put in exec/score/cpu that
have nothing to do with RTEMS internals but are rather
related to CPU feature.

This include at least :

a) registers access routine (e.g GET_MSR_Value),
b) interrupt masking/unmasking routines,
c) cache_mngt_routine,
d) mmu_mngt_routine,
e) Routines to connect the raw_exception, raw_interrupt
handler,

b) lib/libcpu/cpu/powerpc/*

With a processor family as exuberant as the powerpc family,
and their well known subtle differences (604 vs 750) or
unfortunately majors (8xx vs 60x) the directory structure
is fine (except maybe the names that are not homogeneous)

powerpc

ppc421 mpc821 ...

I only needed to add mpc750. But the fact that libcpu.a was not
produced was a pain and the fact that this organization may
duplicates code is also problematic.

So, except if the support of automake provides a better solution
I would like to propose something like this :

powerpc

mpc421 mpc821 ... mpc750 shared wrapup

with the following rules :

a) "shared" would act as a source container for sources that may
be shared among processors. Needed files would be compiled inside
the processor specific directory using the vpath Makefile
mechanism. "shared" may also contain compilation code
for routine that are really shared and not worth to inline...
(did not found many things so far as registers access routine
ARE WORTH INLINING)... In the case something is compiled there,
it should create libcpushared.a

b) layout under processor specific directory is free provided
that

1)the result of the compilation process exports :

libcpu/powerpc/"PROC"/*.h in $(PROJECT_INCLUDE)/libcpu

2) each processor specific directory creates
a library called libcpuspecific.a

Note that this organization enables to have a file that
is nearly the same than in shared but that must differ
because of processor differences...

c) "wrapup" should create libcpu.a using libcpushared.a
libcpuspecific.a and export it $(PROJECT_INCLUDE)/libcpu

The only thing I have no ideal solution is the way to put shared
definitions in "shared" and only processor specific definition
in "proc". To give a concrete example, most MSR bit definition
are shared among PPC processors and only some differs. if we create
a single msr.h in shared it will have ifdef. If in msr.h we
include libcpu/msr_c.h we will need to have it in each prowerpc
specific directory (even empty). Opinions are welcomed ...

Note that a similar mechanism exist in libbsp/i386 that also
contains a shared directory that is used by several bsp
like pc386 and i386ex and a similar wrapup mechanism...

NB: I have done this for mpc750 and other processors could just use
similar Makefiles...

c) The exec/score/cpu/powerpc directory layout.

I think the directory layout should be the same than the
libcpu/powerpc. As it is not, there are a lot of ifdefs
inside the code... And of course low level interrupt handling
code should be removed...

Besides that I do not understand why

1) things are compiled in the wrap directory,
2) some includes are moved to rtems/score,

I think the "preinstall" mechanism enables to put
everything in the current directory (or better in a per processor
directory),

5) Interrupt handling API


Again :-). But I think that using all the features the PIC
offers is a MUST for RT system. I already explained in the
prologue of this (long and probably boring) mail that the MCP750
boards offers an OPENPIC compliant architecture and that
the VIA 82586 PCI/ISA bridge offers a PC compatible IO and
PIC mapping. Here is a logical view of the RAVEN/VIA 82586
interrupt mapping :


| OPEN | <-----|8259|
| PIC | | | 2 ------
|(RAVEN)| | | <-----|8259|
| | | | | | 11
| | | | | | <----
| | | | | |
| | | | | |


------
| VIA PCI/ISA bridge
| x
-------- PCI interrupts

OPENPIC offers interrupt priorities among PCI interrupts
and interrupt selective masking. The 8259 offers the same kind
of feature. With actual powerpc interrupt code :

1) there is no way to specify priorities among
interrupts handler. This is REALLY a bad thing.
For me it is as importnat as having priorities
for threads...
2) for my implementation, each ISR should
contain the code that acknowledge the RAVEN
and 8259 cascade, modify interrupt mask on both
chips, and reenable interrupt at processor level,
..., restore then on interrupt return,.... This code
is actually similar to code located in some
genpvec.c powerpc files,
3) I must update _ISR_Nesting_level because
irq.inl use it...
4) the libchip code connects the ISR via set_vector
but the libchip handler code does not contain any code to
manipulate external interrupt controller hardware
in order to acknoledge the interrupt or re-enable
them (except for the target hardware of course)
So this code is broken unless set_vector adds an
additionnal prologue/epilogue before calling/returning
from in order to acknoledge/mask the raven and the
8259 PICS... => Anyway already EACH BSP MUST REWRITE
PART OF INTERRUPT HANDLING CODE TO CORRECTLY IMPLEMENT
SET_VECTOR.

I would rather offer an API similar to the one provided
in libbsp/i386/shared/irq/irq.h so that :

1) Once the driver supplied methods is called the
only things the ISR has to do is to worry about the
external hardware that triggered the interrupt.
Everything on openpic/VIA/processor would have been
done by the low levels (same things as set-vector)
2) The caller will need to supply the on/off/isOn
routine that are fundamental to correctly implements
debuggers/performance monitoring is a portable way
3) A globally configurable interrupt priorities
mechanism...

I have nothing against providing a compatible
set_vector just to make libchip happy but
as I have already explained in other
mails (months ago), I really think that the ISR
connection should be handled by the BSP and that no
code containing irq connection should exist the
rtems generic layers... Thus I really dislike
libchip on this aspect because in a long term
it will force to adopt the less reach API
for interrupt handling that exists (set_vector).

Additional note : I think the _ISR_Is_in_progress()
inline routine should be :

1) Put in a processor specific section,
2) Should not rely on a global variable,

As :

a) on symmetric MP, there is one interrupt level
per CPU,
b) On processor that have an ISP (e,g 68040),
this variable is useless (MSR bit testing could
be used)
c) On PPC, instead of using the address of the
variable via CPU_IRQ_info.Nest_level a dedicated
SPR could be used.

NOTE: most of this is also true for _Thread_Dispatch_disable_level

END NOTE


Please do not take what I said in the mail as a criticism for
anyone who submitted ppc code. Any code present helped me
a lot understanding PPC behavior. I just wanted by this
mail to :

1) try to better understand the actual code,
2) propose concrete ways of enhancing current code
by providing an alternative implementation for MCP750. I
will make my best effort to try to brake nothing but this
is actually hard due to the file layout organisation.
3) make understandable some changes I will probably make
if joel let me do them :-)

Any comments/objections are welcomed as usual.

--


/ ` Eric Valette

/-- o _. Canon CRF

(_, / (_(_( Rue de la touche lambert

35517 Cesson-Sevigne Cedex
FRANCE

Tel: +33 (0)2 99 87 68 91 Fax: +33 (0)2 99 84 11 30
E-mail: valette@…

  • Property mode set to 100644
File size: 18.2 KB
Line 
1/*  ppc.h
2 *
3 *  This file contains definitions for the IBM/Motorola PowerPC
4 *  family members.
5 *
6 *  Author:     Andrew Bray <andy@i-cubed.co.uk>
7 *
8 *  COPYRIGHT (c) 1995 by i-cubed ltd.
9 *
10 *  MPC860 support code was added by Jay Monkman <jmonkman@frasca.com>
11 *
12 *  To anyone who acknowledges that this file is provided "AS IS"
13 *  without any express or implied warranty:
14 *      permission to use, copy, modify, and distribute this file
15 *      for any purpose is hereby granted without fee, provided that
16 *      the above copyright notice and this notice appears in all
17 *      copies, and that the name of i-cubed limited not be used in
18 *      advertising or publicity pertaining to distribution of the
19 *      software without specific, written prior permission.
20 *      i-cubed limited makes no representations about the suitability
21 *      of this software for any purpose.
22 *
23 *  Derived from c/src/exec/cpu/no_cpu/no_cpu.h:
24 *
25 *  COPYRIGHT (c) 1989-1997.
26 *  On-Line Applications Research Corporation (OAR).
27 *
28 *  The license and distribution terms for this file may in
29 *  the file LICENSE in this distribution or at
30 *  http://www.OARcorp.com/rtems/license.html.
31 *
32 *
33 * Note:
34 *      This file is included by both C and assembler code ( -DASM )
35 *
36 *  $Id$
37 */
38
39
40#ifndef _INCLUDE_PPC_h
41#define _INCLUDE_PPC_h
42
43#ifdef __cplusplus
44extern "C" {
45#endif
46
47/*
48 *  Define the name of the CPU family.
49 */
50
51#define CPU_NAME "PowerPC"
52
53/*
54 *  This file contains the information required to build
55 *  RTEMS for a particular member of the PowerPC family.  It does
56 *  this by setting variables to indicate which implementation
57 *  dependent features are present in a particular member
58 *  of the family.
59 *
60 *  The following architectural feature definitions are defaulted
61 *  unless specifically set by the model definition:
62 *
63 *    + PPC_DEBUG_MODEL          - PPC_DEBUG_MODEL_STANDARD
64 *    + PPC_INTERRUPT_MAX        - 16
65 *    + PPC_CACHE_ALIGNMENT      - 32
66 *    + PPC_LOW_POWER_MODE       - PPC_LOW_POWER_MODE_NONE
67 *    + PPC_HAS_EXCEPTION_PREFIX - 1
68 *    + PPC_HAS_FPU              - 1
69 *    + PPC_HAS_DOUBLE           - 1 if PPC_HAS_FPU,
70 *                               - 0 otherwise
71 *    + PPC_USE_MULTIPLE         - 0
72 */
73 
74/*
75 *  Define the debugging assistance models found in the PPC family.
76 *
77 *  Standard:         single step and branch trace
78 *  Single Step Only: single step only
79 *  IBM 4xx:          debug exception
80 */
81
82#define PPC_DEBUG_MODEL_STANDARD         1
83#define PPC_DEBUG_MODEL_SINGLE_STEP_ONLY 2
84#define PPC_DEBUG_MODEL_IBM4xx           3
85
86/*
87 *  Define the low power mode models
88 *
89 *  Standard:   as defined for 603e
90 *  Nap Mode:   nap mode only (604)
91 *  XXX 403GB, 603, 603e, 604, 821
92 */
93
94#define PPC_LOW_POWER_MODE_NONE      0
95#define PPC_LOW_POWER_MODE_STANDARD  1
96
97#if defined(ppc403)
98/*
99 *  IBM 403
100 *
101 *  Developed for 403GA.  Book checked for 403GB.
102 *
103 *  Does not have user mode.
104 */
105 
106#define CPU_MODEL_NAME "PowerPC 403"
107#define PPC_ALIGNMENT           4 
108#define PPC_CACHE_ALIGNMENT     16
109#define PPC_HAS_RFCI            1
110#define PPC_HAS_FPU             0
111#define PPC_USE_MULTIPLE        1
112#define PPC_I_CACHE             2048
113#define PPC_D_CACHE             1024
114
115#define PPC_DEBUG_MODEL          PPC_DEBUG_MODEL_IBM4xx
116#define PPC_HAS_EXCEPTION_PREFIX 0
117#define PPC_HAS_EVPR             1
118
119#elif defined(ppc601)
120/*
121 *  Submitted with original port -- book checked only.
122 */
123 
124#define CPU_MODEL_NAME  "PowerPC 601"
125
126#define PPC_ALIGNMENT           8
127#define PPC_USE_MULTIPLE        1
128#define PPC_I_CACHE             0
129#define PPC_D_CACHE             32768
130
131#define PPC_DEBUG_MODEL PPC_DEBUG_MODEL_SINGLE_STEP_ONLY
132
133#elif defined(ppc602)
134/*
135 *  Submitted with original port -- book checked only.
136 */
137 
138#define CPU_MODEL_NAME  "PowerPC 602"
139
140#define PPC_ALIGNMENT           4
141#define PPC_HAS_DOUBLE          0
142#define PPC_I_CACHE             4096
143#define PPC_D_CACHE             4096
144
145#elif defined(ppc603)
146/*
147 *  Submitted with original port -- book checked only.
148 */
149 
150#define CPU_MODEL_NAME  "PowerPC 603"
151
152#define PPC_ALIGNMENT           8
153#define PPC_I_CACHE             8192
154#define PPC_D_CACHE             8192
155
156#elif defined(ppc603e)
157 
158#define CPU_MODEL_NAME  "PowerPC 603e"
159/*
160 *  Submitted with original port.
161 *
162 *  Known to work on real hardware.
163 */
164
165#define PPC_ALIGNMENT           8
166#define PPC_I_CACHE             16384
167#define PPC_D_CACHE             16384
168
169#define PPC_LOW_POWER_MODE PPC_LOW_POWER_MODE_STANDARD
170
171#elif defined(ppc604)
172/*
173 *  Submitted with original port -- book checked only.
174 */
175 
176#define CPU_MODEL_NAME  "PowerPC 604"
177
178#define PPC_ALIGNMENT           8
179#define PPC_I_CACHE             16384
180#define PPC_D_CACHE             16384
181 
182#elif defined(mpc860)
183/*
184 *  Added by Jay Monkman (jmonkman@frasca.com) 6/28/98
185 */ 
186#define CPU_MODEL_NAME  "PowerPC MPC860"
187
188#define PPC_ALIGNMENT           4
189#define PPC_I_CACHE             4096
190#define PPC_D_CACHE             4096
191#define PPC_CACHE_ALIGNMENT     16
192#define PPC_INTERRUPT_MAX       71
193#define PPC_HAS_FPU             0
194#define PPC_HAS_DOUBLE          0
195#define PPC_USE_MULTIPLE        1
196#define PPC_USE_SPRG            1
197
198#define PPC_MSR_0               0x00009000
199#define PPC_MSR_1               0x00001000
200#define PPC_MSR_2               0x00001000
201#define PPC_MSR_3               0x00000000
202
203#elif defined(mpc821)
204/*
205 *  Added by Andrew Bray <andy@chaos.org.uk> 6/April/1999
206 */ 
207#define CPU_MODEL_NAME  "PowerPC MPC821"
208
209#define PPC_ALIGNMENT           4
210#define PPC_I_CACHE             4096
211#define PPC_D_CACHE             4096
212#define PPC_CACHE_ALIGNMENT     16
213#define PPC_INTERRUPT_MAX       71
214#define PPC_HAS_FPU             0
215#define PPC_HAS_DOUBLE          0
216
217#define PPC_MSR_0               0x00009000
218#define PPC_MSR_1               0x00001000
219#define PPC_MSR_2               0x00001000
220#define PPC_MSR_3               0x00000000
221
222#elif defined(mpc750)
223
224#define CPU_MODEL_NAME  "PowerPC 750"
225
226#define PPC_ALIGNMENT           8
227#define PPC_I_CACHE             16384
228#define PPC_D_CACHE             16384
229 
230#else
231 
232#error "Unsupported CPU Model"
233 
234#endif
235
236/*
237 *  Application binary interfaces.
238 *
239 *  PPC_ABI MUST be defined as one of these.
240 *  Only PPC_ABI_POWEROPEN is currently fully supported.
241 *  Only EABI will be supported in the end when
242 *  the tools are there.
243 *  Only big endian is currently supported.
244 */
245/*
246 *  PowerOpen ABI.  This is Andy's hack of the
247 *  PowerOpen ABI to ELF.  ELF rather than a
248 *  XCOFF assembler is used.  This may work
249 *  if PPC_ASM == PPC_ASM_XCOFF is defined.
250 */
251#define PPC_ABI_POWEROPEN       0
252/*
253 *  GCC 2.7.0 munched version of EABI, with
254 *  PowerOpen calling convention and stack frames,
255 *  but EABI style indirect function calls.
256 */
257#define PPC_ABI_GCC27           1
258/*
259 *  SVR4 ABI
260 */
261#define PPC_ABI_SVR4            2
262/*
263 *  Embedded ABI
264 */
265#define PPC_ABI_EABI            3
266
267#if (PPC_ABI == PPC_ABI_POWEROPEN)
268#define PPC_STACK_ALIGNMENT     8
269#elif (PPC_ABI == PPC_ABI_GCC27)
270#define PPC_STACK_ALIGNMENT     8
271#elif (PPC_ABI == PPC_ABI_SVR4)
272#define PPC_STACK_ALIGNMENT     16
273#elif (PPC_ABI == PPC_ABI_EABI)
274#define PPC_STACK_ALIGNMENT     8
275#else
276#error  "PPC_ABI is not properly defined"
277#endif
278#ifndef PPC_ABI
279#error  "PPC_ABI is not properly defined"
280#endif
281
282/*
283 *  Assemblers.
284 *  PPC_ASM MUST be defined as one of these.
285 *
286 *  PPC_ASM_ELF:   ELF assembler. Currently used for all ABIs.
287 *  PPC_ASM_XCOFF: XCOFF assembler. May be needed for PowerOpen ABI.
288 *
289 *  NOTE: Only PPC_ABI_ELF is currently fully supported.
290 */
291
292#define PPC_ASM_ELF   0
293#define PPC_ASM_XCOFF 1
294
295/*
296 *  Use the default debug scheme defined in the architectural specification
297 *  if another model has not been specified.
298 */
299
300#ifndef PPC_DEBUG_MODEL
301#define PPC_DEBUG_MODEL PPC_DEBUG_MODEL_STANDARD
302#endif
303
304/*
305 *  If the maximum number of exception sources has not been defined,
306 *  then default it to 16.
307 */
308
309#ifndef PPC_INTERRUPT_MAX
310#define PPC_INTERRUPT_MAX       16
311#endif
312
313/*
314 *  Unless specified otherwise, the cache line size is defaulted to 32.
315 *
316 *  The derive the power of 2 the cache line is.
317 */
318
319#ifndef PPC_CACHE_ALIGNMENT
320#define PPC_CACHE_ALIGNMENT 32
321#endif
322
323#if (PPC_CACHE_ALIGNMENT == 16)
324#define PPC_CACHE_ALIGN_POWER 4
325#elif (PPC_CACHE_ALIGNMENT == 32)
326#define PPC_CACHE_ALIGN_POWER 5
327#else
328#error "Undefined power of 2 for PPC_CACHE_ALIGNMENT"
329#endif
330
331/*
332 *  Unless otherwise specified, assume the model has an IP/EP bit to
333 *  set the exception address prefix.
334 */
335
336#ifndef PPC_HAS_EXCEPTION_PREFIX
337#define PPC_HAS_EXCEPTION_PREFIX 1
338#endif
339
340/*
341 *  Unless otherwise specified, assume the model does NOT have
342 *  403 style EVPR register to set the exception address prefix.
343 */
344
345#ifndef PPC_HAS_EVPR
346#define PPC_HAS_EVPR 0
347#endif
348
349/*
350 *  If no low power mode model was specified, then assume there is none.
351 */
352
353#ifndef PPC_LOW_POWER_MODE
354#define PPC_LOW_POWER_MODE PPC_LOW_POWER_MODE_NONE
355#endif
356
357/*
358 *  Unless specified above, then assume the model has FP support.
359 */
360
361#ifndef PPC_HAS_FPU
362#define PPC_HAS_FPU 1
363#endif
364
365/*
366 *  Unless specified above, If the model has FP support, it is assumed to
367 *  support doubles (8-byte floating point numbers).
368 *
369 *  If the model does NOT have FP support, then the model does
370 *  NOT have double length FP registers.
371 */
372
373#ifndef PPC_HAS_DOUBLE
374#if (PPC_HAS_FPU)
375#define PPC_HAS_DOUBLE 1
376#else
377#define PPC_HAS_DOUBLE 0
378#endif
379#endif
380
381/*
382 *  Unless specified above, then assume the model does NOT have critical
383 *  interrupt support.
384 */
385
386#ifndef PPC_HAS_RFCI
387#define PPC_HAS_RFCI 0
388#endif
389
390/*
391 *  Unless specified above, do not use the load/store multiple instructions
392 *  in a context switch.
393 */
394
395#ifndef PPC_USE_MULTIPLE
396#define PPC_USE_MULTIPLE 0
397#endif
398
399/*
400 *  The following exceptions are not maskable, and are not
401 *  necessarily predictable, so cannot be offered to RTEMS:
402 *    Alignment exception - handled by the CPU module
403 *    Data exceptions.
404 *    Instruction exceptions.
405 */
406
407/*
408 *  Base Interrupt vectors supported on all models.
409 */
410#define PPC_IRQ_SYSTEM_RESET     0 /* 0x00100 - System reset.              */
411#define PPC_IRQ_MCHECK           1 /* 0x00200 - Machine check              */
412#define PPC_IRQ_PROTECT          2 /* 0x00300 - Protection violation       */
413#define PPC_IRQ_ISI              3 /* 0x00400 - Instruction Fetch error    */
414#define PPC_IRQ_EXTERNAL         4 /* 0x00500 - External interrupt         */
415#define PPC_IRQ_ALIGNMENT        5 /* 0X00600 - Alignment exception        */
416#define PPC_IRQ_PROGRAM          6 /* 0x00700 - Program exception          */
417#define PPC_IRQ_NOFP             7 /* 0x00800 - Floating point unavailable */
418#define PPC_IRQ_DECREMENTER      8 /* 0x00900 - Decrementer interrupt      */
419#define PPC_IRQ_RESERVED_A       9 /* 0x00a00 - Implementation Reserved    */
420#define PPC_IRQ_RESERVED_B      10 /* 0x00a00 - Implementation Reserved    */
421#define PPC_IRQ_SCALL           11 /* 0x00c00 - System call                */
422#define PPC_IRQ_TRACE           12 /* 0x00d00 - Trace Exception            */
423#define PPC_IRQ_FP_ASST         13 /* ox00e00 - Floating point assist      */
424#define PPC_STD_IRQ_LAST        PPC_IRQ_FP_ASST
425
426#define PPC_IRQ_FIRST           PPC_IRQ_SYSTEM_RESET
427
428#if defined(ppc403)
429                                 
430#define PPC_IRQ_CRIT     PPC_IRQ_SYSTEM_RESET /*0x00100- Critical int. pin */
431#define PPC_IRQ_PIT      (PPC_STD_IRQ_LAST+1) /*0x01000- Pgm interval timer*/
432#define PPC_IRQ_FIT      (PPC_STD_IRQ_LAST+2) /*0x01010- Fixed int. timer  */
433#define PPC_IRQ_WATCHDOG (PPC_STD_IRQ_LAST+3) /*0x01020- Watchdog timer    */
434#define PPC_IRQ_DEBUG    (PPC_STD_IRQ_LAST+4) /*0x02000- Debug exceptions  */
435#define PPC_IRQ_LAST     PPC_IRQ_DEBUG   
436
437#elif defined(ppc601)
438#define PPC_IRQ_TRACE    (PPC_STD_IRQ_LAST+1) /*0x02000-Run/Trace Exception*/
439#define PPC_IRQ_LAST     PPC_IRQ_TRACE       
440
441#elif defined(ppc602)
442#define PPC_IRQ_LAST     (PPC_STD_IRQ_LAST)
443
444#elif defined(ppc603)
445#define PPC_IRQ_TRANS_MISS (PPC_STD_IRQ_LAST+1) /*0x1000-Ins Translation Miss*/
446#define PPC_IRQ_DATA_LOAD  (PPC_STD_IRQ_LAST+2) /*0x1100-Data Load Trans Miss*/
447#define PPC_IRQ_DATA_STORE (PPC_STD_IRQ_LAST+3) /*0x1200-Data Store Miss     */
448#define PPC_IRQ_ADDR_BRK   (PPC_STD_IRQ_LAST+4) /*0x1300-Instruction Bkpoint */
449#define PPC_IRQ_SYS_MGT    (PPC_STD_IRQ_LAST+5) /*0x1400-System Management   */
450#define PPC_IRQ_LAST       PPC_IRQ_SYS_MGT   
451
452#elif defined(ppc603e)
453#define PPC_TLB_INST_MISS  (PPC_STD_IRQ_LAST+1) /*0x1000-Instruction TLB Miss*/
454#define PPC_TLB_LOAD_MISS  (PPC_STD_IRQ_LAST+2) /*0x1100-TLB miss on load  */
455#define PPC_TLB_STORE_MISS (PPC_STD_IRQ_LAST+3) /*0x1200-TLB Miss on store */
456#define PPC_IRQ_ADDRBRK    (PPC_STD_IRQ_LAST+4) /*0x1300-Instruct addr break */
457#define PPC_IRQ_SYS_MGT    (PPC_STD_IRQ_LAST+5) /*0x1400-System Management   */
458#define PPC_IRQ_LAST       PPC_IRQ_SYS_MGT   
459
460
461#elif defined(ppc604)
462#define PPC_IRQ_ADDR_BRK (PPC_STD_IRQ_LAST+1) /*0x1300- Inst. addr break  */
463#define PPC_IRQ_SYS_MGT  (PPC_STD_IRQ_LAST+2) /*0x1400- System Management */
464#define PPC_IRQ_LAST     PPC_IRQ_SYS_MGT 
465
466#elif defined(mpc860) || defined(mpc821)
467#define PPC_IRQ_EMULATE         (PPC_STD_IRQ_LAST+1) /*0x1000-Software emulation  */
468#define PPC_IRQ_INST_MISS       (PPC_STD_IRQ_LAST+2) /*0x1100-Instruction TLB miss*/
469#define PPC_IRQ_DATA_MISS       (PPC_STD_IRQ_LAST+3) /*0x1200-Data TLB miss */
470#define PPC_IRQ_INST_ERR        (PPC_STD_IRQ_LAST+4) /*0x1300-Instruction TLB err */
471#define PPC_IRQ_DATA_ERR        (PPC_STD_IRQ_LAST+5) /*0x1400-Data TLB error */
472#define PPC_IRQ_DATA_BPNT       (PPC_STD_IRQ_LAST+6) /*0x1C00-Data breakpoint */
473#define PPC_IRQ_INST_BPNT       (PPC_STD_IRQ_LAST+7) /*0x1D00-Inst breakpoint */
474#define PPC_IRQ_IO_BPNT         (PPC_STD_IRQ_LAST+8) /*0x1E00-Peripheral breakpnt */
475#define PPC_IRQ_DEV_PORT        (PPC_STD_IRQ_LAST+9) /*0x1F00-Development port */
476#define PPC_IRQ_IRQ0            (PPC_STD_IRQ_LAST + 10)
477#define PPC_IRQ_LVL0            (PPC_STD_IRQ_LAST + 11)
478#define PPC_IRQ_IRQ1            (PPC_STD_IRQ_LAST + 12)
479#define PPC_IRQ_LVL1            (PPC_STD_IRQ_LAST + 13)
480#define PPC_IRQ_IRQ2            (PPC_STD_IRQ_LAST + 14)
481#define PPC_IRQ_LVL2            (PPC_STD_IRQ_LAST + 15)
482#define PPC_IRQ_IRQ3            (PPC_STD_IRQ_LAST + 16)
483#define PPC_IRQ_LVL3            (PPC_STD_IRQ_LAST + 17)
484#define PPC_IRQ_IRQ4            (PPC_STD_IRQ_LAST + 18)
485#define PPC_IRQ_LVL4            (PPC_STD_IRQ_LAST + 19)
486#define PPC_IRQ_IRQ5            (PPC_STD_IRQ_LAST + 20)
487#define PPC_IRQ_LVL5            (PPC_STD_IRQ_LAST + 21)
488#define PPC_IRQ_IRQ6            (PPC_STD_IRQ_LAST + 22)
489#define PPC_IRQ_LVL6            (PPC_STD_IRQ_LAST + 23)
490#define PPC_IRQ_IRQ7            (PPC_STD_IRQ_LAST + 24)
491#define PPC_IRQ_LVL7            (PPC_STD_IRQ_LAST + 25)
492#define PPC_IRQ_CPM_RESERVED_0  (PPC_STD_IRQ_LAST + 26)
493#define PPC_IRQ_CPM_PC4         (PPC_STD_IRQ_LAST + 27)
494#define PPC_IRQ_CPM_PC5         (PPC_STD_IRQ_LAST + 28)
495#define PPC_IRQ_CPM_SMC2        (PPC_STD_IRQ_LAST + 29)
496#define PPC_IRQ_CPM_SMC1        (PPC_STD_IRQ_LAST + 30)
497#define PPC_IRQ_CPM_SPI         (PPC_STD_IRQ_LAST + 31)
498#define PPC_IRQ_CPM_PC6         (PPC_STD_IRQ_LAST + 32)
499#define PPC_IRQ_CPM_TIMER4      (PPC_STD_IRQ_LAST + 33)
500#define PPC_IRQ_CPM_RESERVED_8  (PPC_STD_IRQ_LAST + 34)
501#define PPC_IRQ_CPM_PC7         (PPC_STD_IRQ_LAST + 35)
502#define PPC_IRQ_CPM_PC8         (PPC_STD_IRQ_LAST + 36)
503#define PPC_IRQ_CPM_PC9         (PPC_STD_IRQ_LAST + 37)
504#define PPC_IRQ_CPM_TIMER3      (PPC_STD_IRQ_LAST + 38)
505#define PPC_IRQ_CPM_RESERVED_D  (PPC_STD_IRQ_LAST + 39)
506#define PPC_IRQ_CPM_PC10        (PPC_STD_IRQ_LAST + 40)
507#define PPC_IRQ_CPM_PC11        (PPC_STD_IRQ_LAST + 41)
508#define PPC_IRQ_CPM_I2C         (PPC_STD_IRQ_LAST + 42)
509#define PPC_IRQ_CPM_RISC_TIMER  (PPC_STD_IRQ_LAST + 43)
510#define PPC_IRQ_CPM_TIMER2      (PPC_STD_IRQ_LAST + 44)
511#define PPC_IRQ_CPM_RESERVED_13 (PPC_STD_IRQ_LAST + 45)
512#define PPC_IRQ_CPM_IDMA2       (PPC_STD_IRQ_LAST + 46)
513#define PPC_IRQ_CPM_IDMA1       (PPC_STD_IRQ_LAST + 47)
514#define PPC_IRQ_CPM_SDMA_ERROR  (PPC_STD_IRQ_LAST + 48)
515#define PPC_IRQ_CPM_PC12        (PPC_STD_IRQ_LAST + 49)
516#define PPC_IRQ_CPM_PC13        (PPC_STD_IRQ_LAST + 50)
517#define PPC_IRQ_CPM_TIMER1      (PPC_STD_IRQ_LAST + 51)
518#define PPC_IRQ_CPM_PC14        (PPC_STD_IRQ_LAST + 52)
519#define PPC_IRQ_CPM_SCC4        (PPC_STD_IRQ_LAST + 53)
520#define PPC_IRQ_CPM_SCC3        (PPC_STD_IRQ_LAST + 54)
521#define PPC_IRQ_CPM_SCC2        (PPC_STD_IRQ_LAST + 55)
522#define PPC_IRQ_CPM_SCC1        (PPC_STD_IRQ_LAST + 56)
523#define PPC_IRQ_CPM_PC15        (PPC_STD_IRQ_LAST + 57)
524
525#define PPC_IRQ_LAST             PPC_IRQ_CPM_PC15
526
527#endif
528
529/*
530 *  If the maximum number of exception sources is too low,
531 *  then fix it
532 */
533
534#if PPC_INTERRUPT_MAX <= PPC_IRQ_LAST
535#undef PPC_INTERRUPT_MAX
536#define PPC_INTERRUPT_MAX ((PPC_IRQ_LAST) + 1)
537#endif
538
539/*
540 *  Machine Status Register (MSR) Constants Used by RTEMS
541 */
542
543/*
544 *  Some PPC model manuals refer to the Exception Prefix (EP) bit as
545 *  IP for no apparent reason.
546 */
547
548#define PPC_MSR_RI       0x000000002 /* bit 30 - recoverable exception */
549#define PPC_MSR_DR       0x000000010 /* bit 27 - data address translation */
550#define PPC_MSR_IR       0x000000020 /* bit 26 - instruction addr translation*/
551
552#if (PPC_HAS_EXCEPTION_PREFIX)
553#define PPC_MSR_EP       0x000000040 /* bit 25 - exception prefix */
554#else
555#define PPC_MSR_EP       0x000000000 /* bit 25 - exception prefix */
556#endif
557
558#if (PPC_HAS_FPU)
559#define PPC_MSR_FP       0x000002000 /* bit 18 - floating point enable */
560#else
561#define PPC_MSR_FP       0x000000000 /* bit 18 - floating point enable */
562#endif
563
564#if (PPC_LOW_POWER_MODE == PPC_LOW_POWER_MODE_NONE)
565#define PPC_MSR_POW      0x000000000 /* bit 13 - power management enable */
566#else
567#define PPC_MSR_POW      0x000040000 /* bit 13 - power management enable */
568#endif
569
570/*
571 *  Interrupt/exception MSR bits set as defined on p. 2-20 in "The Programming
572 *  Environments" and the manuals for various PPC models.
573 */
574
575#if (PPC_DEBUG_MODEL == PPC_DEBUG_MODEL_STANDARD)
576#define PPC_MSR_DE       0x000000000 /* bit 22 - debug exception enable */
577#define PPC_MSR_BE       0x000000200 /* bit 22 - branch trace enable */
578#define PPC_MSR_SE       0x000000400 /* bit 21 - single step trace enable */
579#elif (PPC_DEBUG_MODEL == PPC_DEBUG_MODEL_SINGLE_STEP_ONLY)
580#define PPC_MSR_DE       0x000000000 /* bit 22 - debug exception enable */
581#define PPC_MSR_BE       0x000000200 /* bit 22 - branch trace enable */
582#define PPC_MSR_SE       0x000000000 /* bit 21 - single step trace enable */
583#elif (PPC_DEBUG_MODEL == PPC_DEBUG_MODEL_IBM4xx)
584#define PPC_MSR_DE       0x000000200 /* bit 22 - debug exception enable */
585#define PPC_MSR_BE       0x000000000 /* bit 22 - branch trace enable */
586#define PPC_MSR_SE       0x000000000 /* bit 21 - single step trace enable */
587#else
588#error "MSR constants -- unknown PPC_DEBUG_MODEL!!"
589#endif
590
591#define PPC_MSR_ME       0x000001000 /* bit 19 - machine check enable */
592#define PPC_MSR_EE       0x000008000 /* bit 16 - external interrupt enable */
593
594#if (PPC_HAS_RFCI)
595#define PPC_MSR_CE       0x000020000 /* bit 14 - critical interrupt enable */
596#else
597#define PPC_MSR_CE       0x000000000 /* bit 14 - critical interrupt enable */
598#endif
599
600#define PPC_MSR_DISABLE_MASK (PPC_MSR_ME|PPC_MSR_EE|PPC_MSR_CE)
601
602/*
603 *  Initial value for the FPSCR register
604 */
605
606#define PPC_INIT_FPSCR          0x000000f8
607
608#ifdef __cplusplus
609}
610#endif
611
612#endif /* ! _INCLUDE_PPC_h */
613/* end of include file */
614
615
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