source: rtems/c/src/exec/score/cpu/powerpc/rtems/score/ppc.h @ 78f8c91

4.104.114.84.95
Last change on this file since 78f8c91 was 78f8c91, checked in by Joel Sherrill <joel.sherrill@…>, on 05/14/02 at 16:53:01

2001-05-14 Till Straumann <strauman@…>

  • rtems/powerpc/registers.h, rtems/score/ppc.h: Per PR213, add support for the MPC74000 (AKA G4); there is no AltiVec? support yet, however.
  • Property mode set to 100644
File size: 24.0 KB
Line 
1/*  ppc.h
2 *
3 *  This file contains definitions for the IBM/Motorola PowerPC
4 *  family members.
5 *
6 *  Author:     Andrew Bray <andy@i-cubed.co.uk>
7 *
8 *  COPYRIGHT (c) 1995 by i-cubed ltd.
9 *
10 *  MPC860 support code was added by Jay Monkman <jmonkman@frasca.com>
11 *  MPC8260 support added by Andy Dachs <a.dachs@sstl.co.uk>
12 *  Surrey Satellite Technology Limited
13 *
14 *  To anyone who acknowledges that this file is provided "AS IS"
15 *  without any express or implied warranty:
16 *      permission to use, copy, modify, and distribute this file
17 *      for any purpose is hereby granted without fee, provided that
18 *      the above copyright notice and this notice appears in all
19 *      copies, and that the name of i-cubed limited not be used in
20 *      advertising or publicity pertaining to distribution of the
21 *      software without specific, written prior permission.
22 *      i-cubed limited makes no representations about the suitability
23 *      of this software for any purpose.
24 *
25 *  Derived from c/src/exec/cpu/no_cpu/no_cpu.h:
26 *
27 *  COPYRIGHT (c) 1989-1997.
28 *  On-Line Applications Research Corporation (OAR).
29 *
30 *  The license and distribution terms for this file may in
31 *  the file LICENSE in this distribution or at
32 *  http://www.OARcorp.com/rtems/license.html.
33 *
34 *
35 * Note:
36 *      This file is included by both C and assembler code ( -DASM )
37 *
38 *  $Id$
39 */
40
41
42#ifndef _INCLUDE_PPC_h
43#define _INCLUDE_PPC_h
44
45#ifdef __cplusplus
46extern "C" {
47#endif
48
49#include <rtems/score/types.h>
50
51/*
52 *  Define the name of the CPU family.
53 */
54
55#define CPU_NAME "PowerPC"
56
57/*
58 *  This file contains the information required to build
59 *  RTEMS for a particular member of the PowerPC family.  It does
60 *  this by setting variables to indicate which implementation
61 *  dependent features are present in a particular member
62 *  of the family.
63 *
64 *  The following architectural feature definitions are defaulted
65 *  unless specifically set by the model definition:
66 *
67 *    + PPC_DEBUG_MODEL          - PPC_DEBUG_MODEL_STANDARD
68 *    + PPC_INTERRUPT_MAX        - 16
69 *    + PPC_CACHE_ALIGNMENT      - 32
70 *    + PPC_LOW_POWER_MODE       - PPC_LOW_POWER_MODE_NONE
71 *    + PPC_HAS_EXCEPTION_PREFIX - 1
72 *    + PPC_HAS_FPU              - 1
73 *    + PPC_HAS_DOUBLE           - 1 if PPC_HAS_FPU,
74 *                               - 0 otherwise
75 *    + PPC_USE_MULTIPLE         - 0
76 */
77 
78/*
79 *  Define the debugging assistance models found in the PPC family.
80 *
81 *  Standard:         single step and branch trace
82 *  Single Step Only: single step only
83 *  IBM 4xx:          debug exception
84 */
85
86#define PPC_DEBUG_MODEL_STANDARD         1
87#define PPC_DEBUG_MODEL_SINGLE_STEP_ONLY 2
88#define PPC_DEBUG_MODEL_IBM4xx           3
89
90/*
91 *  Define the low power mode models
92 *
93 *  Standard:   as defined for 603e
94 *  Nap Mode:   nap mode only (604)
95 *  XXX 403GB, 603, 603e, 604, 821
96 */
97
98#define PPC_LOW_POWER_MODE_NONE      0
99#define PPC_LOW_POWER_MODE_STANDARD  1
100
101/*
102 *  Figure out all CPU Model Feature Flags based upon compiler
103 *  predefines.
104 */
105
106#if defined(ppc403) || defined(ppc405)
107/*
108 *  IBM 403
109 *
110 *  Developed for 403GA.  Book checked for 403GB.
111 *
112 *  Does not have user mode.
113 */
114 
115#if defined(ppc403)
116#define CPU_MODEL_NAME "PowerPC 403"
117#elif defined (ppc405)
118#define CPU_MODEL_NAME "PowerPC 405"
119#endif
120#define PPC_ALIGNMENT           4 
121#define PPC_CACHE_ALIGNMENT     16
122#define PPC_HAS_RFCI            1
123#define PPC_HAS_FPU             0
124#define PPC_USE_MULTIPLE        1
125#define PPC_I_CACHE             2048
126#define PPC_D_CACHE             1024
127
128#define PPC_DEBUG_MODEL          PPC_DEBUG_MODEL_IBM4xx
129#define PPC_HAS_EXCEPTION_PREFIX 0
130#define PPC_HAS_EVPR             1
131
132#elif defined(mpc555)
133
134#define CPU_MODEL_NAME  "PowerPC 555"
135
136/* Copied from mpc505 */
137#define PPC_ALIGNMENT           4
138#define PPC_CACHE_ALIGNMENT     16
139
140/* Based on comments by Sergei Organov <osv@Javad.RU> */
141#define PPC_I_CACHE             0
142#define PPC_D_CACHE             0
143
144#elif defined(mpc505) || defined(mpc509)
145/*
146 *  Submitted by Sergei Organov <osv@Javad.RU> as a patch against
147 *  3.6.0 long after 4.0 was released.   This is just an attempt
148 *  to get the setting correct.
149 */
150
151#define CPU_MODEL_NAME  "PowerPC 505/509"
152
153#define PPC_ALIGNMENT           4
154#define PPC_CACHE_ALIGNMENT     16
155#define PPC_I_CACHE             4096
156#define PPC_D_CACHE             0
157
158
159#elif defined(ppc601)
160
161/*
162 *  Submitted with original port -- book checked only.
163 */
164 
165#define CPU_MODEL_NAME  "PowerPC 601"
166
167#define PPC_ALIGNMENT           8
168#define PPC_USE_MULTIPLE        1
169#define PPC_I_CACHE             0
170#define PPC_D_CACHE             32768
171
172#define PPC_DEBUG_MODEL PPC_DEBUG_MODEL_SINGLE_STEP_ONLY
173
174#elif defined(ppc602)
175/*
176 *  Submitted with original port -- book checked only.
177 */
178 
179#define CPU_MODEL_NAME  "PowerPC 602"
180
181#define PPC_ALIGNMENT           4
182#define PPC_HAS_DOUBLE          0
183#define PPC_I_CACHE             4096
184#define PPC_D_CACHE             4096
185
186#elif defined(ppc603)
187/*
188 *  Submitted with original port -- book checked only.
189 */
190 
191#define CPU_MODEL_NAME  "PowerPC 603"
192
193#define PPC_ALIGNMENT           8
194#define PPC_I_CACHE             8192
195#define PPC_D_CACHE             8192
196
197#elif defined(ppc603e)
198 
199#define CPU_MODEL_NAME  "PowerPC 603e"
200/*
201 *  Submitted with original port.
202 *
203 *  Known to work on real hardware.
204 */
205
206#define PPC_ALIGNMENT           8
207#define PPC_I_CACHE             16384
208#define PPC_D_CACHE             16384
209
210#define PPC_LOW_POWER_MODE PPC_LOW_POWER_MODE_STANDARD
211
212#elif defined(mpc604)
213/*
214 *  Submitted with original port -- book checked only.
215 */
216 
217#define CPU_MODEL_NAME  "PowerPC 604"
218
219#define PPC_ALIGNMENT           8
220#define PPC_I_CACHE             16384
221#define PPC_D_CACHE             16384
222 
223#elif defined(mpc860)
224/*
225 *  Added by Jay Monkman (jmonkman@frasca.com) 6/28/98
226 *  with some changes by Darlene Stewart (Darlene.Stewart@iit.nrc.ca)
227 */
228#define CPU_MODEL_NAME  "PowerPC MPC860"
229
230#define PPC_ALIGNMENT           4
231#define PPC_I_CACHE             4096
232#define PPC_D_CACHE             4096
233#define PPC_CACHE_ALIGNMENT     16
234#define PPC_INTERRUPT_MAX       71
235#define PPC_HAS_FPU             0
236#define PPC_HAS_DOUBLE          0
237#define PPC_USE_MULTIPLE        1
238
239#define PPC_MSR_0               0x00009000
240#define PPC_MSR_1               0x00001000
241#define PPC_MSR_2               0x00001000
242#define PPC_MSR_3               0x00000000
243
244#elif defined(mpc821)
245/*
246 *  Added by Andrew Bray <andy@chaos.org.uk> 6/April/1999
247 */
248#define CPU_MODEL_NAME  "PowerPC MPC821"
249
250#define PPC_ALIGNMENT           4
251#define PPC_I_CACHE             4096
252#define PPC_D_CACHE             4096
253#define PPC_CACHE_ALIGNMENT     16
254#define PPC_INTERRUPT_MAX       71
255#define PPC_HAS_FPU             0
256#define PPC_HAS_DOUBLE          0
257
258#define PPC_MSR_0               0x00009000
259#define PPC_MSR_1               0x00001000
260#define PPC_MSR_2               0x00001000
261#define PPC_MSR_3               0x00000000
262
263#elif defined(mpc750)
264
265#define CPU_MODEL_NAME  "PowerPC 750"
266
267#define PPC_ALIGNMENT           8
268#define PPC_I_CACHE             16384
269#define PPC_D_CACHE             16384
270
271#elif defined(mpc7400)
272
273#define CPU_MODEL_NAME  "PowerPC 7400"
274
275#define PPC_ALIGNMENT           8
276#define PPC_I_CACHE             32768
277#define PPC_D_CACHE             32768
278
279#elif defined(mpc8260)
280/*
281 *  Added by Andy Dachs <a.dachs@sstl.co.uk> 23/11/2000
282 */
283#define CPU_MODEL_NAME  "PowerPC MPC8260"
284
285#define PPC_ALIGNMENT           4
286#define PPC_I_CACHE             16384
287#define PPC_D_CACHE             16384
288#define PPC_CACHE_ALIGNMENT     32
289#define PPC_INTERRUPT_MAX       125
290/*#define PPC_HAS_FPU           0 */    /* my 8260 is one the few with no FPU */
291#define PPC_HAS_FPU             1       /* the rest do have one */
292#define PPC_HAS_DOUBLE          1
293#define PPC_USE_MULTIPLE        1
294#else
295 
296#error "Unsupported CPU Model"
297 
298#endif
299
300/*
301 *  Application binary interfaces.
302 *
303 *  PPC_ABI MUST be defined as one of these.
304 *  Only PPC_ABI_POWEROPEN is currently fully supported.
305 *  Only EABI will be supported in the end when
306 *  the tools are there.
307 *  Only big endian is currently supported.
308 */
309/*
310 *  PowerOpen ABI.  This is Andy's hack of the
311 *  PowerOpen ABI to ELF.  ELF rather than a
312 *  XCOFF assembler is used.  This may work
313 *  if PPC_ASM == PPC_ASM_XCOFF is defined.
314 */
315#define PPC_ABI_POWEROPEN       0
316/*
317 *  GCC 2.7.0 munched version of EABI, with
318 *  PowerOpen calling convention and stack frames,
319 *  but EABI style indirect function calls.
320 */
321#define PPC_ABI_GCC27           1
322/*
323 *  SVR4 ABI
324 */
325#define PPC_ABI_SVR4            2
326/*
327 *  Embedded ABI
328 */
329#define PPC_ABI_EABI            3
330
331/*
332 *  Default to the EABI used by current GNU tools
333 */
334
335#ifndef PPC_ABI
336#define PPC_ABI PPC_ABI_EABI
337#endif
338
339#if (PPC_ABI == PPC_ABI_POWEROPEN)
340#define PPC_STACK_ALIGNMENT     8
341#elif (PPC_ABI == PPC_ABI_GCC27)
342#define PPC_STACK_ALIGNMENT     8
343#elif (PPC_ABI == PPC_ABI_SVR4)
344#define PPC_STACK_ALIGNMENT     16
345#elif (PPC_ABI == PPC_ABI_EABI)
346#define PPC_STACK_ALIGNMENT     8
347#else
348#error  "PPC_ABI is not properly defined"
349#endif
350#ifndef PPC_ABI
351#error  "PPC_ABI is not properly defined"
352#endif
353
354/*
355 *  Assemblers.
356 *  PPC_ASM MUST be defined as one of these.
357 *
358 *  PPC_ASM_ELF:   ELF assembler. Currently used for all ABIs.
359 *  PPC_ASM_XCOFF: XCOFF assembler. May be needed for PowerOpen ABI.
360 *
361 *  NOTE: Only PPC_ABI_ELF is currently fully supported.
362 */
363
364#define PPC_ASM_ELF   0
365#define PPC_ASM_XCOFF 1
366
367/*
368 *  Default to the assembler format used by the current GNU tools.
369 */
370
371#ifndef PPC_ASM
372#define PPC_ASM PPC_ASM_ELF
373#endif
374
375/*
376 *  Use the default debug scheme defined in the architectural specification
377 *  if another model has not been specified.
378 */
379
380#ifndef PPC_DEBUG_MODEL
381#define PPC_DEBUG_MODEL PPC_DEBUG_MODEL_STANDARD
382#endif
383
384/*
385 *  If the maximum number of exception sources has not been defined,
386 *  then default it to 16.
387 */
388
389#ifndef PPC_INTERRUPT_MAX
390#define PPC_INTERRUPT_MAX       16
391#endif
392
393/*
394 *  Unless specified otherwise, the cache line size is defaulted to 32.
395 *
396 *  The derive the power of 2 the cache line is.
397 */
398
399#ifndef PPC_CACHE_ALIGNMENT
400#define PPC_CACHE_ALIGNMENT 32
401#endif
402
403#if (PPC_CACHE_ALIGNMENT == 16)
404#define PPC_CACHE_ALIGN_POWER 4
405#elif (PPC_CACHE_ALIGNMENT == 32)
406#define PPC_CACHE_ALIGN_POWER 5
407#else
408#error "Undefined power of 2 for PPC_CACHE_ALIGNMENT"
409#endif
410
411/*
412 *  Unless otherwise specified, assume the model has an IP/EP bit to
413 *  set the exception address prefix.
414 */
415
416#ifndef PPC_HAS_EXCEPTION_PREFIX
417#define PPC_HAS_EXCEPTION_PREFIX 1
418#endif
419
420/*
421 *  Unless otherwise specified, assume the model does NOT have
422 *  403 style EVPR register to set the exception address prefix.
423 */
424
425#ifndef PPC_HAS_EVPR
426#define PPC_HAS_EVPR 0
427#endif
428
429/*
430 *  If no low power mode model was specified, then assume there is none.
431 */
432
433#ifndef PPC_LOW_POWER_MODE
434#define PPC_LOW_POWER_MODE PPC_LOW_POWER_MODE_NONE
435#endif
436
437/*
438 *  Unless specified above, then assume the model has FP support.
439 */
440
441#ifndef PPC_HAS_FPU
442#define PPC_HAS_FPU 1
443#endif
444
445/*
446 *  Unless specified above, If the model has FP support, it is assumed to
447 *  support doubles (8-byte floating point numbers).
448 *
449 *  If the model does NOT have FP support, then the model does
450 *  NOT have double length FP registers.
451 */
452
453#ifndef PPC_HAS_DOUBLE
454#if (PPC_HAS_FPU)
455#define PPC_HAS_DOUBLE 1
456#else
457#define PPC_HAS_DOUBLE 0
458#endif
459#endif
460
461/*
462 *  Unless specified above, then assume the model does NOT have critical
463 *  interrupt support.
464 */
465
466#ifndef PPC_HAS_RFCI
467#define PPC_HAS_RFCI 0
468#endif
469
470/*
471 *  Unless specified above, do not use the load/store multiple instructions
472 *  in a context switch.
473 */
474
475#ifndef PPC_USE_MULTIPLE
476#define PPC_USE_MULTIPLE 0
477#endif
478
479/*
480 *  The following exceptions are not maskable, and are not
481 *  necessarily predictable, so cannot be offered to RTEMS:
482 *    Alignment exception - handled by the CPU module
483 *    Data exceptions.
484 *    Instruction exceptions.
485 */
486
487/*
488 *  Base Interrupt vectors supported on all models.
489 */
490#define PPC_IRQ_SYSTEM_RESET     0 /* 0x00100 - System reset.              */
491#define PPC_IRQ_MCHECK           1 /* 0x00200 - Machine check              */
492#define PPC_IRQ_PROTECT          2 /* 0x00300 - Protection violation       */
493#define PPC_IRQ_ISI              3 /* 0x00400 - Instruction Fetch error    */
494#define PPC_IRQ_EXTERNAL         4 /* 0x00500 - External interrupt         */
495#define PPC_IRQ_ALIGNMENT        5 /* 0X00600 - Alignment exception        */
496#define PPC_IRQ_PROGRAM          6 /* 0x00700 - Program exception          */
497#define PPC_IRQ_NOFP             7 /* 0x00800 - Floating point unavailable */
498#define PPC_IRQ_DECREMENTER      8 /* 0x00900 - Decrementer interrupt      */
499#define PPC_IRQ_RESERVED_A       9 /* 0x00a00 - Implementation Reserved    */
500#define PPC_IRQ_RESERVED_B      10 /* 0x00b00 - Implementation Reserved    */
501#define PPC_IRQ_SCALL           11 /* 0x00c00 - System call                */
502#define PPC_IRQ_TRACE           12 /* 0x00d00 - Trace Exception            */
503#define PPC_IRQ_FP_ASST         13 /* ox00e00 - Floating point assist      */
504#define PPC_STD_IRQ_LAST        PPC_IRQ_FP_ASST
505
506#define PPC_IRQ_FIRST           PPC_IRQ_SYSTEM_RESET
507
508#if defined(ppc403) || defined(ppc405)
509                                 
510#define PPC_IRQ_CRIT     PPC_IRQ_SYSTEM_RESET /*0x00100- Critical int. pin */
511#define PPC_IRQ_PIT      (PPC_STD_IRQ_LAST+1) /*0x01000- Pgm interval timer*/
512#define PPC_IRQ_FIT      (PPC_STD_IRQ_LAST+2) /*0x01010- Fixed int. timer  */
513#define PPC_IRQ_WATCHDOG (PPC_STD_IRQ_LAST+3) /*0x01020- Watchdog timer    */
514#define PPC_IRQ_DEBUG    (PPC_STD_IRQ_LAST+4) /*0x02000- Debug exceptions  */
515#define PPC_IRQ_LAST     PPC_IRQ_DEBUG
516
517#elif defined(mpc505) || defined(mpc509)
518#define PPC_IRQ_SOFTEMU   (PPC_STD_IRQ_LAST+1)    /* Software emulation. */
519#define PPC_IRQ_DATA_BP   (PPC_STD_IRQ_LAST+ 2)
520#define PPC_IRQ_INST_BP   (PPC_STD_IRQ_LAST+ 3)
521#define PPC_IRQ_MEXT_BP   (PPC_STD_IRQ_LAST+ 4)
522#define PPC_IRQ_NMEXT_BP  (PPC_STD_IRQ_LAST+ 5)
523
524#elif defined(ppc601)
525#define PPC_IRQ_TRACE    (PPC_STD_IRQ_LAST+1) /*0x02000-Run/Trace Exception*/
526#define PPC_IRQ_LAST     PPC_IRQ_TRACE       
527
528#elif defined(ppc602)
529#define PPC_IRQ_LAST     (PPC_STD_IRQ_LAST)
530
531#elif defined(ppc603)
532#define PPC_IRQ_TRANS_MISS (PPC_STD_IRQ_LAST+1) /*0x1000-Ins Translation Miss*/
533#define PPC_IRQ_DATA_LOAD  (PPC_STD_IRQ_LAST+2) /*0x1100-Data Load Trans Miss*/
534#define PPC_IRQ_DATA_STORE (PPC_STD_IRQ_LAST+3) /*0x1200-Data Store Miss     */
535#define PPC_IRQ_ADDR_BRK   (PPC_STD_IRQ_LAST+4) /*0x1300-Instruction Bkpoint */
536#define PPC_IRQ_SYS_MGT    (PPC_STD_IRQ_LAST+5) /*0x1400-System Management   */
537#define PPC_IRQ_LAST       PPC_IRQ_SYS_MGT   
538
539#elif defined(ppc603e)
540#define PPC_TLB_INST_MISS  (PPC_STD_IRQ_LAST+1) /*0x1000-Instruction TLB Miss*/
541#define PPC_TLB_LOAD_MISS  (PPC_STD_IRQ_LAST+2) /*0x1100-TLB miss on load  */
542#define PPC_TLB_STORE_MISS (PPC_STD_IRQ_LAST+3) /*0x1200-TLB Miss on store */
543#define PPC_IRQ_ADDRBRK    (PPC_STD_IRQ_LAST+4) /*0x1300-Instruct addr break */
544#define PPC_IRQ_SYS_MGT    (PPC_STD_IRQ_LAST+5) /*0x1400-System Management   */
545#define PPC_IRQ_LAST       PPC_IRQ_SYS_MGT   
546
547
548#elif defined(mpc604)
549#define PPC_IRQ_ADDR_BRK (PPC_STD_IRQ_LAST+1) /*0x1300- Inst. addr break  */
550#define PPC_IRQ_SYS_MGT  (PPC_STD_IRQ_LAST+2) /*0x1400- System Management */
551#define PPC_IRQ_LAST     PPC_IRQ_SYS_MGT 
552
553#elif defined(mpc860) || defined(mpc821)
554#define PPC_IRQ_EMULATE         (PPC_STD_IRQ_LAST+1) /*0x1000-Software emulation  */
555#define PPC_IRQ_INST_MISS       (PPC_STD_IRQ_LAST+2) /*0x1100-Instruction TLB miss*/
556#define PPC_IRQ_DATA_MISS       (PPC_STD_IRQ_LAST+3) /*0x1200-Data TLB miss */
557#define PPC_IRQ_INST_ERR        (PPC_STD_IRQ_LAST+4) /*0x1300-Instruction TLB err */
558#define PPC_IRQ_DATA_ERR        (PPC_STD_IRQ_LAST+5) /*0x1400-Data TLB error */
559#define PPC_IRQ_DATA_BPNT       (PPC_STD_IRQ_LAST+6) /*0x1C00-Data breakpoint */
560#define PPC_IRQ_INST_BPNT       (PPC_STD_IRQ_LAST+7) /*0x1D00-Inst breakpoint */
561#define PPC_IRQ_IO_BPNT         (PPC_STD_IRQ_LAST+8) /*0x1E00-Peripheral breakpnt */
562#define PPC_IRQ_DEV_PORT        (PPC_STD_IRQ_LAST+9) /*0x1F00-Development port */
563#define PPC_IRQ_IRQ0            (PPC_STD_IRQ_LAST + 10)
564#define PPC_IRQ_LVL0            (PPC_STD_IRQ_LAST + 11)
565#define PPC_IRQ_IRQ1            (PPC_STD_IRQ_LAST + 12)
566#define PPC_IRQ_LVL1            (PPC_STD_IRQ_LAST + 13)
567#define PPC_IRQ_IRQ2            (PPC_STD_IRQ_LAST + 14)
568#define PPC_IRQ_LVL2            (PPC_STD_IRQ_LAST + 15)
569#define PPC_IRQ_IRQ3            (PPC_STD_IRQ_LAST + 16)
570#define PPC_IRQ_LVL3            (PPC_STD_IRQ_LAST + 17)
571#define PPC_IRQ_IRQ4            (PPC_STD_IRQ_LAST + 18)
572#define PPC_IRQ_LVL4            (PPC_STD_IRQ_LAST + 19)
573#define PPC_IRQ_IRQ5            (PPC_STD_IRQ_LAST + 20)
574#define PPC_IRQ_LVL5            (PPC_STD_IRQ_LAST + 21)
575#define PPC_IRQ_IRQ6            (PPC_STD_IRQ_LAST + 22)
576#define PPC_IRQ_LVL6            (PPC_STD_IRQ_LAST + 23)
577#define PPC_IRQ_IRQ7            (PPC_STD_IRQ_LAST + 24)
578#define PPC_IRQ_LVL7            (PPC_STD_IRQ_LAST + 25)
579#define PPC_IRQ_CPM_ERROR       (PPC_STD_IRQ_LAST + 26)
580#define PPC_IRQ_CPM_PC4         (PPC_STD_IRQ_LAST + 27)
581#define PPC_IRQ_CPM_PC5         (PPC_STD_IRQ_LAST + 28)
582#define PPC_IRQ_CPM_SMC2        (PPC_STD_IRQ_LAST + 29)
583#define PPC_IRQ_CPM_SMC1        (PPC_STD_IRQ_LAST + 30)
584#define PPC_IRQ_CPM_SPI         (PPC_STD_IRQ_LAST + 31)
585#define PPC_IRQ_CPM_PC6         (PPC_STD_IRQ_LAST + 32)
586#define PPC_IRQ_CPM_TIMER4      (PPC_STD_IRQ_LAST + 33)
587#define PPC_IRQ_CPM_RESERVED_8  (PPC_STD_IRQ_LAST + 34)
588#define PPC_IRQ_CPM_PC7         (PPC_STD_IRQ_LAST + 35)
589#define PPC_IRQ_CPM_PC8         (PPC_STD_IRQ_LAST + 36)
590#define PPC_IRQ_CPM_PC9         (PPC_STD_IRQ_LAST + 37)
591#define PPC_IRQ_CPM_TIMER3      (PPC_STD_IRQ_LAST + 38)
592#define PPC_IRQ_CPM_RESERVED_D  (PPC_STD_IRQ_LAST + 39)
593#define PPC_IRQ_CPM_PC10        (PPC_STD_IRQ_LAST + 40)
594#define PPC_IRQ_CPM_PC11        (PPC_STD_IRQ_LAST + 41)
595#define PPC_IRQ_CPM_I2C         (PPC_STD_IRQ_LAST + 42)
596#define PPC_IRQ_CPM_RISC_TIMER  (PPC_STD_IRQ_LAST + 43)
597#define PPC_IRQ_CPM_TIMER2      (PPC_STD_IRQ_LAST + 44)
598#define PPC_IRQ_CPM_RESERVED_13 (PPC_STD_IRQ_LAST + 45)
599#define PPC_IRQ_CPM_IDMA2       (PPC_STD_IRQ_LAST + 46)
600#define PPC_IRQ_CPM_IDMA1       (PPC_STD_IRQ_LAST + 47)
601#define PPC_IRQ_CPM_SDMA_ERROR  (PPC_STD_IRQ_LAST + 48)
602#define PPC_IRQ_CPM_PC12        (PPC_STD_IRQ_LAST + 49)
603#define PPC_IRQ_CPM_PC13        (PPC_STD_IRQ_LAST + 50)
604#define PPC_IRQ_CPM_TIMER1      (PPC_STD_IRQ_LAST + 51)
605#define PPC_IRQ_CPM_PC14        (PPC_STD_IRQ_LAST + 52)
606#define PPC_IRQ_CPM_SCC4        (PPC_STD_IRQ_LAST + 53)
607#define PPC_IRQ_CPM_SCC3        (PPC_STD_IRQ_LAST + 54)
608#define PPC_IRQ_CPM_SCC2        (PPC_STD_IRQ_LAST + 55)
609#define PPC_IRQ_CPM_SCC1        (PPC_STD_IRQ_LAST + 56)
610#define PPC_IRQ_CPM_PC15        (PPC_STD_IRQ_LAST + 57)
611
612#define PPC_IRQ_LAST             PPC_IRQ_CPM_PC15
613
614#elif defined(mpc8260)
615
616#define PPC_IRQ_INST_MISS       (PPC_STD_IRQ_LAST+1) /*0x1000-Instruction TLB miss*/
617#define PPC_IRQ_DATA_MISS       (PPC_STD_IRQ_LAST+2) /*0x1100-Data TLB miss */
618#define PPC_IRQ_DATA_L_MISS     (PPC_STD_IRQ_LAST+3) /*0x1200-Data TLB load miss */
619#define PPC_IRQ_DATA_S_MISS     (PPC_STD_IRQ_LAST+4) /*0x1300-Data TLB store miss */
620#define PPC_IRQ_INST_BPNT       (PPC_STD_IRQ_LAST+5) /*0x1400-Inst address breakpoint */
621#define PPC_IRQ_SYS_MGT         (PPC_STD_IRQ_LAST+6) /*0x1500-System Management */
622/* 0x1600 - 0x2F00 reserved */
623#define PPC_IRQ_CPM_NONE        (PPC_STD_IRQ_LAST + 50)
624#define PPC_IRQ_CPM_I2C         (PPC_STD_IRQ_LAST + 51)
625#define PPC_IRQ_CPM_SPI         (PPC_STD_IRQ_LAST + 52)
626#define PPC_IRQ_CPM_RISC_TIMER  (PPC_STD_IRQ_LAST + 53)
627#define PPC_IRQ_CPM_SMC1        (PPC_STD_IRQ_LAST + 54)
628#define PPC_IRQ_CPM_SMC2        (PPC_STD_IRQ_LAST + 55)
629#define PPC_IRQ_CPM_IDMA1       (PPC_STD_IRQ_LAST + 56)
630#define PPC_IRQ_CPM_IDMA2       (PPC_STD_IRQ_LAST + 57)
631#define PPC_IRQ_CPM_IDMA3       (PPC_STD_IRQ_LAST + 58)
632#define PPC_IRQ_CPM_IDMA4       (PPC_STD_IRQ_LAST + 59)
633#define PPC_IRQ_CPM_SDMA        (PPC_STD_IRQ_LAST + 60)
634#define PPC_IRQ_CPM_RES_A       (PPC_STD_IRQ_LAST + 61)
635#define PPC_IRQ_CPM_TIMER1      (PPC_STD_IRQ_LAST + 62)
636#define PPC_IRQ_CPM_TIMER2      (PPC_STD_IRQ_LAST + 63)
637#define PPC_IRQ_CPM_TIMER3      (PPC_STD_IRQ_LAST + 64)
638#define PPC_IRQ_CPM_TIMER4      (PPC_STD_IRQ_LAST + 65)
639#define PPC_IRQ_CPM_TMCNT       (PPC_STD_IRQ_LAST + 66)
640#define PPC_IRQ_CPM_PIT         (PPC_STD_IRQ_LAST + 67)
641#define PPC_IRQ_CPM_RES_B       (PPC_STD_IRQ_LAST + 68)
642#define PPC_IRQ_CPM_IRQ1        (PPC_STD_IRQ_LAST + 69)
643#define PPC_IRQ_CPM_IRQ2        (PPC_STD_IRQ_LAST + 70)
644#define PPC_IRQ_CPM_IRQ3        (PPC_STD_IRQ_LAST + 71)
645#define PPC_IRQ_CPM_IRQ4        (PPC_STD_IRQ_LAST + 72)
646#define PPC_IRQ_CPM_IRQ5        (PPC_STD_IRQ_LAST + 73)
647#define PPC_IRQ_CPM_IRQ6        (PPC_STD_IRQ_LAST + 74)
648#define PPC_IRQ_CPM_IRQ7        (PPC_STD_IRQ_LAST + 75)
649#define PPC_IRQ_CPM_RES_C       (PPC_STD_IRQ_LAST + 76)
650#define PPC_IRQ_CPM_RES_D       (PPC_STD_IRQ_LAST + 77)
651#define PPC_IRQ_CPM_RES_E       (PPC_STD_IRQ_LAST + 78)
652#define PPC_IRQ_CPM_RES_F       (PPC_STD_IRQ_LAST + 79)
653#define PPC_IRQ_CPM_RES_G       (PPC_STD_IRQ_LAST + 80)
654#define PPC_IRQ_CPM_RES_H       (PPC_STD_IRQ_LAST + 81)
655#define PPC_IRQ_CPM_FCC1        (PPC_STD_IRQ_LAST + 82)
656#define PPC_IRQ_CPM_FCC2        (PPC_STD_IRQ_LAST + 83)
657#define PPC_IRQ_CPM_FCC3        (PPC_STD_IRQ_LAST + 84)
658#define PPC_IRQ_CPM_RES_I       (PPC_STD_IRQ_LAST + 85)
659#define PPC_IRQ_CPM_MCC1        (PPC_STD_IRQ_LAST + 86)
660#define PPC_IRQ_CPM_MCC2        (PPC_STD_IRQ_LAST + 87)
661#define PPC_IRQ_CPM_RES_J       (PPC_STD_IRQ_LAST + 88)
662#define PPC_IRQ_CPM_RES_K       (PPC_STD_IRQ_LAST + 89)
663#define PPC_IRQ_CPM_SCC1        (PPC_STD_IRQ_LAST + 90)
664#define PPC_IRQ_CPM_SCC2        (PPC_STD_IRQ_LAST + 91)
665#define PPC_IRQ_CPM_SCC3        (PPC_STD_IRQ_LAST + 92)
666#define PPC_IRQ_CPM_SCC4        (PPC_STD_IRQ_LAST + 93)
667#define PPC_IRQ_CPM_RES_L       (PPC_STD_IRQ_LAST + 94)
668#define PPC_IRQ_CPM_RES_M       (PPC_STD_IRQ_LAST + 95)
669#define PPC_IRQ_CPM_RES_N       (PPC_STD_IRQ_LAST + 96)
670#define PPC_IRQ_CPM_RES_O       (PPC_STD_IRQ_LAST + 97)
671#define PPC_IRQ_CPM_PC15        (PPC_STD_IRQ_LAST + 98)
672#define PPC_IRQ_CPM_PC14        (PPC_STD_IRQ_LAST + 99)
673#define PPC_IRQ_CPM_PC13        (PPC_STD_IRQ_LAST + 100)
674#define PPC_IRQ_CPM_PC12        (PPC_STD_IRQ_LAST + 101)
675#define PPC_IRQ_CPM_PC11        (PPC_STD_IRQ_LAST + 102)
676#define PPC_IRQ_CPM_PC10        (PPC_STD_IRQ_LAST + 103)
677#define PPC_IRQ_CPM_PC9         (PPC_STD_IRQ_LAST + 104)
678#define PPC_IRQ_CPM_PC8         (PPC_STD_IRQ_LAST + 105)
679#define PPC_IRQ_CPM_PC7         (PPC_STD_IRQ_LAST + 106)
680#define PPC_IRQ_CPM_PC6         (PPC_STD_IRQ_LAST + 107)
681#define PPC_IRQ_CPM_PC5         (PPC_STD_IRQ_LAST + 108)
682#define PPC_IRQ_CPM_PC4         (PPC_STD_IRQ_LAST + 109)
683#define PPC_IRQ_CPM_PC3         (PPC_STD_IRQ_LAST + 110)
684#define PPC_IRQ_CPM_PC2         (PPC_STD_IRQ_LAST + 111)
685#define PPC_IRQ_CPM_PC1         (PPC_STD_IRQ_LAST + 112)
686#define PPC_IRQ_CPM_PC0         (PPC_STD_IRQ_LAST + 113)
687
688#define PPC_IRQ_LAST             PPC_IRQ_CPM_PC0
689
690#endif
691
692
693/*
694 *  If the maximum number of exception sources is too low,
695 *  then fix it
696 */
697
698#if PPC_INTERRUPT_MAX <= PPC_IRQ_LAST
699#undef PPC_INTERRUPT_MAX
700#define PPC_INTERRUPT_MAX ((PPC_IRQ_LAST) + 1)
701#endif
702
703/*
704 *  Machine Status Register (MSR) Constants Used by RTEMS
705 */
706
707/*
708 *  Some PPC model manuals refer to the Exception Prefix (EP) bit as
709 *  IP for no apparent reason.
710 */
711
712#define PPC_MSR_RI       0x000000002 /* bit 30 - recoverable exception */
713#define PPC_MSR_DR       0x000000010 /* bit 27 - data address translation */
714#define PPC_MSR_IR       0x000000020 /* bit 26 - instruction addr translation*/
715
716#if (PPC_HAS_EXCEPTION_PREFIX)
717#define PPC_MSR_EP       0x000000040 /* bit 25 - exception prefix */
718#else
719#define PPC_MSR_EP       0x000000000 /* bit 25 - exception prefix */
720#endif
721
722#if (PPC_HAS_FPU)
723#define PPC_MSR_FP       0x000002000 /* bit 18 - floating point enable */
724#else
725#define PPC_MSR_FP       0x000000000 /* bit 18 - floating point enable */
726#endif
727
728#if (PPC_LOW_POWER_MODE == PPC_LOW_POWER_MODE_NONE)
729#define PPC_MSR_POW      0x000000000 /* bit 13 - power management enable */
730#else
731#define PPC_MSR_POW      0x000040000 /* bit 13 - power management enable */
732#endif
733
734/*
735 *  Interrupt/exception MSR bits set as defined on p. 2-20 in "The Programming
736 *  Environments" and the manuals for various PPC models.
737 */
738
739#if (PPC_DEBUG_MODEL == PPC_DEBUG_MODEL_STANDARD)
740#define PPC_MSR_DE       0x000000000 /* bit 22 - debug exception enable */
741#define PPC_MSR_BE       0x000000200 /* bit 22 - branch trace enable */
742#define PPC_MSR_SE       0x000000400 /* bit 21 - single step trace enable */
743#elif (PPC_DEBUG_MODEL == PPC_DEBUG_MODEL_SINGLE_STEP_ONLY)
744#define PPC_MSR_DE       0x000000000 /* bit 22 - debug exception enable */
745#define PPC_MSR_BE       0x000000200 /* bit 22 - branch trace enable */
746#define PPC_MSR_SE       0x000000000 /* bit 21 - single step trace enable */
747#elif (PPC_DEBUG_MODEL == PPC_DEBUG_MODEL_IBM4xx)
748#define PPC_MSR_DE       0x000000200 /* bit 22 - debug exception enable */
749#define PPC_MSR_BE       0x000000000 /* bit 22 - branch trace enable */
750#define PPC_MSR_SE       0x000000000 /* bit 21 - single step trace enable */
751#else
752#error "MSR constants -- unknown PPC_DEBUG_MODEL!!"
753#endif
754
755#define PPC_MSR_ME       0x000001000 /* bit 19 - machine check enable */
756#define PPC_MSR_EE       0x000008000 /* bit 16 - external interrupt enable */
757
758#if (PPC_HAS_RFCI)
759#define PPC_MSR_CE       0x000020000 /* bit 14 - critical interrupt enable */
760#else
761#define PPC_MSR_CE       0x000000000 /* bit 14 - critical interrupt enable */
762#endif
763
764#define PPC_MSR_DISABLE_MASK (PPC_MSR_ME|PPC_MSR_EE|PPC_MSR_CE)
765
766/*
767 *  Initial value for the FPSCR register
768 */
769
770#define PPC_INIT_FPSCR          0x000000f8
771
772#ifdef __cplusplus
773}
774#endif
775
776#endif /* ! _INCLUDE_PPC_h */
777/* end of include file */
778
779
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