source: rtems/c/src/exec/score/cpu/powerpc/rtems/score/ppc.h @ 0fe89f6

4.104.114.84.95
Last change on this file since 0fe89f6 was 0fe89f6, checked in by Joel Sherrill <joel.sherrill@…>, on 05/14/02 at 18:31:37

2002-05-01 Ralf Corsepius <corsepiu@…>

  • rtems/score/ppc.h: Remove PPC_DEBUG_MODEL.
  • Property mode set to 100644
File size: 22.3 KB
Line 
1/*  ppc.h
2 *
3 *  This file contains definitions for the IBM/Motorola PowerPC
4 *  family members.
5 *
6 *  Author:     Andrew Bray <andy@i-cubed.co.uk>
7 *
8 *  COPYRIGHT (c) 1995 by i-cubed ltd.
9 *
10 *  MPC860 support code was added by Jay Monkman <jmonkman@frasca.com>
11 *  MPC8260 support added by Andy Dachs <a.dachs@sstl.co.uk>
12 *  Surrey Satellite Technology Limited
13 *
14 *  To anyone who acknowledges that this file is provided "AS IS"
15 *  without any express or implied warranty:
16 *      permission to use, copy, modify, and distribute this file
17 *      for any purpose is hereby granted without fee, provided that
18 *      the above copyright notice and this notice appears in all
19 *      copies, and that the name of i-cubed limited not be used in
20 *      advertising or publicity pertaining to distribution of the
21 *      software without specific, written prior permission.
22 *      i-cubed limited makes no representations about the suitability
23 *      of this software for any purpose.
24 *
25 *  Derived from c/src/exec/cpu/no_cpu/no_cpu.h:
26 *
27 *  COPYRIGHT (c) 1989-1997.
28 *  On-Line Applications Research Corporation (OAR).
29 *
30 *  The license and distribution terms for this file may in
31 *  the file LICENSE in this distribution or at
32 *  http://www.OARcorp.com/rtems/license.html.
33 *
34 *
35 * Note:
36 *      This file is included by both C and assembler code ( -DASM )
37 *
38 *  $Id$
39 */
40
41
42#ifndef _INCLUDE_PPC_h
43#define _INCLUDE_PPC_h
44
45#ifdef __cplusplus
46extern "C" {
47#endif
48
49#include <rtems/score/types.h>
50
51/*
52 *  Define the name of the CPU family.
53 */
54
55#define CPU_NAME "PowerPC"
56
57/*
58 *  This file contains the information required to build
59 *  RTEMS for a particular member of the PowerPC family.  It does
60 *  this by setting variables to indicate which implementation
61 *  dependent features are present in a particular member
62 *  of the family.
63 *
64 *  The following architectural feature definitions are defaulted
65 *  unless specifically set by the model definition:
66 *
67 *    + PPC_INTERRUPT_MAX        - 16
68 *    + PPC_CACHE_ALIGNMENT      - 32
69 *    + PPC_LOW_POWER_MODE       - PPC_LOW_POWER_MODE_NONE
70 *    + PPC_HAS_EXCEPTION_PREFIX - 1
71 *    + PPC_HAS_FPU              - 1
72 *    + PPC_HAS_DOUBLE           - 1 if PPC_HAS_FPU,
73 *                               - 0 otherwise
74 *    + PPC_USE_MULTIPLE         - 0
75 */
76 
77/*
78 *  Define the low power mode models
79 *
80 *  Standard:   as defined for 603e
81 *  Nap Mode:   nap mode only (604)
82 *  XXX 403GB, 603, 603e, 604, 821
83 */
84
85#define PPC_LOW_POWER_MODE_NONE      0
86#define PPC_LOW_POWER_MODE_STANDARD  1
87
88/*
89 *  Figure out all CPU Model Feature Flags based upon compiler
90 *  predefines.
91 */
92
93#if defined(ppc403) || defined(ppc405)
94/*
95 *  IBM 403
96 *
97 *  Developed for 403GA.  Book checked for 403GB.
98 *
99 *  Does not have user mode.
100 */
101 
102#if defined(ppc403)
103#define CPU_MODEL_NAME "PowerPC 403"
104#elif defined (ppc405)
105#define CPU_MODEL_NAME "PowerPC 405"
106#endif
107#define PPC_ALIGNMENT           4 
108#define PPC_CACHE_ALIGNMENT     16
109#define PPC_HAS_RFCI            1
110#define PPC_HAS_FPU             0
111#define PPC_USE_MULTIPLE        1
112#define PPC_I_CACHE             2048
113#define PPC_D_CACHE             1024
114
115#define PPC_HAS_EXCEPTION_PREFIX 0
116#define PPC_HAS_EVPR             1
117
118#elif defined(mpc555)
119
120#define CPU_MODEL_NAME  "PowerPC 555"
121
122/* Copied from mpc505 */
123#define PPC_ALIGNMENT           4
124#define PPC_CACHE_ALIGNMENT     16
125
126/* Based on comments by Sergei Organov <osv@Javad.RU> */
127#define PPC_I_CACHE             0
128#define PPC_D_CACHE             0
129
130#elif defined(mpc505) || defined(mpc509)
131/*
132 *  Submitted by Sergei Organov <osv@Javad.RU> as a patch against
133 *  3.6.0 long after 4.0 was released.   This is just an attempt
134 *  to get the setting correct.
135 */
136
137#define CPU_MODEL_NAME  "PowerPC 505/509"
138
139#define PPC_ALIGNMENT           4
140#define PPC_CACHE_ALIGNMENT     16
141#define PPC_I_CACHE             4096
142#define PPC_D_CACHE             0
143
144
145#elif defined(ppc601)
146
147/*
148 *  Submitted with original port -- book checked only.
149 */
150 
151#define CPU_MODEL_NAME  "PowerPC 601"
152
153#define PPC_ALIGNMENT           8
154#define PPC_USE_MULTIPLE        1
155#define PPC_I_CACHE             0
156#define PPC_D_CACHE             32768
157
158#elif defined(ppc602)
159/*
160 *  Submitted with original port -- book checked only.
161 */
162 
163#define CPU_MODEL_NAME  "PowerPC 602"
164
165#define PPC_ALIGNMENT           4
166#define PPC_HAS_DOUBLE          0
167#define PPC_I_CACHE             4096
168#define PPC_D_CACHE             4096
169
170#elif defined(ppc603)
171/*
172 *  Submitted with original port -- book checked only.
173 */
174 
175#define CPU_MODEL_NAME  "PowerPC 603"
176
177#define PPC_ALIGNMENT           8
178#define PPC_I_CACHE             8192
179#define PPC_D_CACHE             8192
180
181#elif defined(ppc603e)
182 
183#define CPU_MODEL_NAME  "PowerPC 603e"
184/*
185 *  Submitted with original port.
186 *
187 *  Known to work on real hardware.
188 */
189
190#define PPC_ALIGNMENT           8
191#define PPC_I_CACHE             16384
192#define PPC_D_CACHE             16384
193
194#define PPC_LOW_POWER_MODE PPC_LOW_POWER_MODE_STANDARD
195
196#elif defined(mpc604)
197/*
198 *  Submitted with original port -- book checked only.
199 */
200 
201#define CPU_MODEL_NAME  "PowerPC 604"
202
203#define PPC_ALIGNMENT           8
204#define PPC_I_CACHE             16384
205#define PPC_D_CACHE             16384
206 
207#elif defined(mpc860)
208/*
209 *  Added by Jay Monkman (jmonkman@frasca.com) 6/28/98
210 *  with some changes by Darlene Stewart (Darlene.Stewart@iit.nrc.ca)
211 */
212#define CPU_MODEL_NAME  "PowerPC MPC860"
213
214#define PPC_ALIGNMENT           4
215#define PPC_I_CACHE             4096
216#define PPC_D_CACHE             4096
217#define PPC_CACHE_ALIGNMENT     16
218#define PPC_INTERRUPT_MAX       71
219#define PPC_HAS_FPU             0
220#define PPC_HAS_DOUBLE          0
221#define PPC_USE_MULTIPLE        1
222
223#define PPC_MSR_0               0x00009000
224#define PPC_MSR_1               0x00001000
225#define PPC_MSR_2               0x00001000
226#define PPC_MSR_3               0x00000000
227
228#elif defined(mpc821)
229/*
230 *  Added by Andrew Bray <andy@chaos.org.uk> 6/April/1999
231 */
232#define CPU_MODEL_NAME  "PowerPC MPC821"
233
234#define PPC_ALIGNMENT           4
235#define PPC_I_CACHE             4096
236#define PPC_D_CACHE             4096
237#define PPC_CACHE_ALIGNMENT     16
238#define PPC_INTERRUPT_MAX       71
239#define PPC_HAS_FPU             0
240#define PPC_HAS_DOUBLE          0
241
242#define PPC_MSR_0               0x00009000
243#define PPC_MSR_1               0x00001000
244#define PPC_MSR_2               0x00001000
245#define PPC_MSR_3               0x00000000
246
247#elif defined(mpc750)
248
249#define CPU_MODEL_NAME  "PowerPC 750"
250
251#define PPC_ALIGNMENT           8
252#define PPC_I_CACHE             16384
253#define PPC_D_CACHE             16384
254
255#elif defined(mpc7400)
256
257#define CPU_MODEL_NAME  "PowerPC 7400"
258
259#define PPC_ALIGNMENT           8
260#define PPC_I_CACHE             32768
261#define PPC_D_CACHE             32768
262
263#elif defined(mpc8260)
264/*
265 *  Added by Andy Dachs <a.dachs@sstl.co.uk> 23/11/2000
266 */
267#define CPU_MODEL_NAME  "PowerPC MPC8260"
268
269#define PPC_ALIGNMENT           4
270#define PPC_I_CACHE             16384
271#define PPC_D_CACHE             16384
272#define PPC_CACHE_ALIGNMENT     32
273#define PPC_INTERRUPT_MAX       125
274/*#define PPC_HAS_FPU           0 */    /* my 8260 is one the few with no FPU */
275#define PPC_HAS_FPU             1       /* the rest do have one */
276#define PPC_HAS_DOUBLE          1
277#define PPC_USE_MULTIPLE        1
278#else
279 
280#error "Unsupported CPU Model"
281 
282#endif
283
284/*
285 *  Application binary interfaces.
286 *
287 *  PPC_ABI MUST be defined as one of these.
288 *  Only PPC_ABI_POWEROPEN is currently fully supported.
289 *  Only EABI will be supported in the end when
290 *  the tools are there.
291 *  Only big endian is currently supported.
292 */
293/*
294 *  PowerOpen ABI.  This is Andy's hack of the
295 *  PowerOpen ABI to ELF.  ELF rather than a
296 *  XCOFF assembler is used.  This may work
297 *  if PPC_ASM == PPC_ASM_XCOFF is defined.
298 */
299#define PPC_ABI_POWEROPEN       0
300/*
301 *  GCC 2.7.0 munched version of EABI, with
302 *  PowerOpen calling convention and stack frames,
303 *  but EABI style indirect function calls.
304 */
305#define PPC_ABI_GCC27           1
306/*
307 *  SVR4 ABI
308 */
309#define PPC_ABI_SVR4            2
310/*
311 *  Embedded ABI
312 */
313#define PPC_ABI_EABI            3
314
315/*
316 *  Default to the EABI used by current GNU tools
317 */
318
319#ifndef PPC_ABI
320#define PPC_ABI PPC_ABI_EABI
321#endif
322
323#if (PPC_ABI == PPC_ABI_POWEROPEN)
324#define PPC_STACK_ALIGNMENT     8
325#elif (PPC_ABI == PPC_ABI_GCC27)
326#define PPC_STACK_ALIGNMENT     8
327#elif (PPC_ABI == PPC_ABI_SVR4)
328#define PPC_STACK_ALIGNMENT     16
329#elif (PPC_ABI == PPC_ABI_EABI)
330#define PPC_STACK_ALIGNMENT     8
331#else
332#error  "PPC_ABI is not properly defined"
333#endif
334#ifndef PPC_ABI
335#error  "PPC_ABI is not properly defined"
336#endif
337
338/*
339 *  Assemblers.
340 *  PPC_ASM MUST be defined as one of these.
341 *
342 *  PPC_ASM_ELF:   ELF assembler. Currently used for all ABIs.
343 *  PPC_ASM_XCOFF: XCOFF assembler. May be needed for PowerOpen ABI.
344 *
345 *  NOTE: Only PPC_ABI_ELF is currently fully supported.
346 */
347
348#define PPC_ASM_ELF   0
349#define PPC_ASM_XCOFF 1
350
351/*
352 *  Default to the assembler format used by the current GNU tools.
353 */
354
355#ifndef PPC_ASM
356#define PPC_ASM PPC_ASM_ELF
357#endif
358
359/*
360 *  If the maximum number of exception sources has not been defined,
361 *  then default it to 16.
362 */
363
364#ifndef PPC_INTERRUPT_MAX
365#define PPC_INTERRUPT_MAX       16
366#endif
367
368/*
369 *  Unless specified otherwise, the cache line size is defaulted to 32.
370 *
371 *  The derive the power of 2 the cache line is.
372 */
373
374#ifndef PPC_CACHE_ALIGNMENT
375#define PPC_CACHE_ALIGNMENT 32
376#endif
377
378#if (PPC_CACHE_ALIGNMENT == 16)
379#define PPC_CACHE_ALIGN_POWER 4
380#elif (PPC_CACHE_ALIGNMENT == 32)
381#define PPC_CACHE_ALIGN_POWER 5
382#else
383#error "Undefined power of 2 for PPC_CACHE_ALIGNMENT"
384#endif
385
386/*
387 *  Unless otherwise specified, assume the model has an IP/EP bit to
388 *  set the exception address prefix.
389 */
390
391#ifndef PPC_HAS_EXCEPTION_PREFIX
392#define PPC_HAS_EXCEPTION_PREFIX 1
393#endif
394
395/*
396 *  Unless otherwise specified, assume the model does NOT have
397 *  403 style EVPR register to set the exception address prefix.
398 */
399
400#ifndef PPC_HAS_EVPR
401#define PPC_HAS_EVPR 0
402#endif
403
404/*
405 *  If no low power mode model was specified, then assume there is none.
406 */
407
408#ifndef PPC_LOW_POWER_MODE
409#define PPC_LOW_POWER_MODE PPC_LOW_POWER_MODE_NONE
410#endif
411
412/*
413 *  Unless specified above, then assume the model has FP support.
414 */
415
416#ifndef PPC_HAS_FPU
417#define PPC_HAS_FPU 1
418#endif
419
420/*
421 *  Unless specified above, If the model has FP support, it is assumed to
422 *  support doubles (8-byte floating point numbers).
423 *
424 *  If the model does NOT have FP support, then the model does
425 *  NOT have double length FP registers.
426 */
427
428#ifndef PPC_HAS_DOUBLE
429#if (PPC_HAS_FPU)
430#define PPC_HAS_DOUBLE 1
431#else
432#define PPC_HAS_DOUBLE 0
433#endif
434#endif
435
436/*
437 *  Unless specified above, then assume the model does NOT have critical
438 *  interrupt support.
439 */
440
441#ifndef PPC_HAS_RFCI
442#define PPC_HAS_RFCI 0
443#endif
444
445/*
446 *  Unless specified above, do not use the load/store multiple instructions
447 *  in a context switch.
448 */
449
450#ifndef PPC_USE_MULTIPLE
451#define PPC_USE_MULTIPLE 0
452#endif
453
454/*
455 *  The following exceptions are not maskable, and are not
456 *  necessarily predictable, so cannot be offered to RTEMS:
457 *    Alignment exception - handled by the CPU module
458 *    Data exceptions.
459 *    Instruction exceptions.
460 */
461
462/*
463 *  Base Interrupt vectors supported on all models.
464 */
465#define PPC_IRQ_SYSTEM_RESET     0 /* 0x00100 - System reset.              */
466#define PPC_IRQ_MCHECK           1 /* 0x00200 - Machine check              */
467#define PPC_IRQ_PROTECT          2 /* 0x00300 - Protection violation       */
468#define PPC_IRQ_ISI              3 /* 0x00400 - Instruction Fetch error    */
469#define PPC_IRQ_EXTERNAL         4 /* 0x00500 - External interrupt         */
470#define PPC_IRQ_ALIGNMENT        5 /* 0X00600 - Alignment exception        */
471#define PPC_IRQ_PROGRAM          6 /* 0x00700 - Program exception          */
472#define PPC_IRQ_NOFP             7 /* 0x00800 - Floating point unavailable */
473#define PPC_IRQ_DECREMENTER      8 /* 0x00900 - Decrementer interrupt      */
474#define PPC_IRQ_RESERVED_A       9 /* 0x00a00 - Implementation Reserved    */
475#define PPC_IRQ_RESERVED_B      10 /* 0x00b00 - Implementation Reserved    */
476#define PPC_IRQ_SCALL           11 /* 0x00c00 - System call                */
477#define PPC_IRQ_TRACE           12 /* 0x00d00 - Trace Exception            */
478#define PPC_IRQ_FP_ASST         13 /* ox00e00 - Floating point assist      */
479#define PPC_STD_IRQ_LAST        PPC_IRQ_FP_ASST
480
481#define PPC_IRQ_FIRST           PPC_IRQ_SYSTEM_RESET
482
483#if defined(ppc403) || defined(ppc405)
484                                 
485#define PPC_IRQ_CRIT     PPC_IRQ_SYSTEM_RESET /*0x00100- Critical int. pin */
486#define PPC_IRQ_PIT      (PPC_STD_IRQ_LAST+1) /*0x01000- Pgm interval timer*/
487#define PPC_IRQ_FIT      (PPC_STD_IRQ_LAST+2) /*0x01010- Fixed int. timer  */
488#define PPC_IRQ_WATCHDOG (PPC_STD_IRQ_LAST+3) /*0x01020- Watchdog timer    */
489#define PPC_IRQ_DEBUG    (PPC_STD_IRQ_LAST+4) /*0x02000- Debug exceptions  */
490#define PPC_IRQ_LAST     PPC_IRQ_DEBUG
491
492#elif defined(mpc505) || defined(mpc509)
493#define PPC_IRQ_SOFTEMU   (PPC_STD_IRQ_LAST+1)    /* Software emulation. */
494#define PPC_IRQ_DATA_BP   (PPC_STD_IRQ_LAST+ 2)
495#define PPC_IRQ_INST_BP   (PPC_STD_IRQ_LAST+ 3)
496#define PPC_IRQ_MEXT_BP   (PPC_STD_IRQ_LAST+ 4)
497#define PPC_IRQ_NMEXT_BP  (PPC_STD_IRQ_LAST+ 5)
498
499#elif defined(ppc601)
500#define PPC_IRQ_TRACE    (PPC_STD_IRQ_LAST+1) /*0x02000-Run/Trace Exception*/
501#define PPC_IRQ_LAST     PPC_IRQ_TRACE       
502
503#elif defined(ppc602)
504#define PPC_IRQ_LAST     (PPC_STD_IRQ_LAST)
505
506#elif defined(ppc603)
507#define PPC_IRQ_TRANS_MISS (PPC_STD_IRQ_LAST+1) /*0x1000-Ins Translation Miss*/
508#define PPC_IRQ_DATA_LOAD  (PPC_STD_IRQ_LAST+2) /*0x1100-Data Load Trans Miss*/
509#define PPC_IRQ_DATA_STORE (PPC_STD_IRQ_LAST+3) /*0x1200-Data Store Miss     */
510#define PPC_IRQ_ADDR_BRK   (PPC_STD_IRQ_LAST+4) /*0x1300-Instruction Bkpoint */
511#define PPC_IRQ_SYS_MGT    (PPC_STD_IRQ_LAST+5) /*0x1400-System Management   */
512#define PPC_IRQ_LAST       PPC_IRQ_SYS_MGT   
513
514#elif defined(ppc603e)
515#define PPC_TLB_INST_MISS  (PPC_STD_IRQ_LAST+1) /*0x1000-Instruction TLB Miss*/
516#define PPC_TLB_LOAD_MISS  (PPC_STD_IRQ_LAST+2) /*0x1100-TLB miss on load  */
517#define PPC_TLB_STORE_MISS (PPC_STD_IRQ_LAST+3) /*0x1200-TLB Miss on store */
518#define PPC_IRQ_ADDRBRK    (PPC_STD_IRQ_LAST+4) /*0x1300-Instruct addr break */
519#define PPC_IRQ_SYS_MGT    (PPC_STD_IRQ_LAST+5) /*0x1400-System Management   */
520#define PPC_IRQ_LAST       PPC_IRQ_SYS_MGT   
521
522
523#elif defined(mpc604)
524#define PPC_IRQ_ADDR_BRK (PPC_STD_IRQ_LAST+1) /*0x1300- Inst. addr break  */
525#define PPC_IRQ_SYS_MGT  (PPC_STD_IRQ_LAST+2) /*0x1400- System Management */
526#define PPC_IRQ_LAST     PPC_IRQ_SYS_MGT 
527
528#elif defined(mpc860) || defined(mpc821)
529#define PPC_IRQ_EMULATE         (PPC_STD_IRQ_LAST+1) /*0x1000-Software emulation  */
530#define PPC_IRQ_INST_MISS       (PPC_STD_IRQ_LAST+2) /*0x1100-Instruction TLB miss*/
531#define PPC_IRQ_DATA_MISS       (PPC_STD_IRQ_LAST+3) /*0x1200-Data TLB miss */
532#define PPC_IRQ_INST_ERR        (PPC_STD_IRQ_LAST+4) /*0x1300-Instruction TLB err */
533#define PPC_IRQ_DATA_ERR        (PPC_STD_IRQ_LAST+5) /*0x1400-Data TLB error */
534#define PPC_IRQ_DATA_BPNT       (PPC_STD_IRQ_LAST+6) /*0x1C00-Data breakpoint */
535#define PPC_IRQ_INST_BPNT       (PPC_STD_IRQ_LAST+7) /*0x1D00-Inst breakpoint */
536#define PPC_IRQ_IO_BPNT         (PPC_STD_IRQ_LAST+8) /*0x1E00-Peripheral breakpnt */
537#define PPC_IRQ_DEV_PORT        (PPC_STD_IRQ_LAST+9) /*0x1F00-Development port */
538#define PPC_IRQ_IRQ0            (PPC_STD_IRQ_LAST + 10)
539#define PPC_IRQ_LVL0            (PPC_STD_IRQ_LAST + 11)
540#define PPC_IRQ_IRQ1            (PPC_STD_IRQ_LAST + 12)
541#define PPC_IRQ_LVL1            (PPC_STD_IRQ_LAST + 13)
542#define PPC_IRQ_IRQ2            (PPC_STD_IRQ_LAST + 14)
543#define PPC_IRQ_LVL2            (PPC_STD_IRQ_LAST + 15)
544#define PPC_IRQ_IRQ3            (PPC_STD_IRQ_LAST + 16)
545#define PPC_IRQ_LVL3            (PPC_STD_IRQ_LAST + 17)
546#define PPC_IRQ_IRQ4            (PPC_STD_IRQ_LAST + 18)
547#define PPC_IRQ_LVL4            (PPC_STD_IRQ_LAST + 19)
548#define PPC_IRQ_IRQ5            (PPC_STD_IRQ_LAST + 20)
549#define PPC_IRQ_LVL5            (PPC_STD_IRQ_LAST + 21)
550#define PPC_IRQ_IRQ6            (PPC_STD_IRQ_LAST + 22)
551#define PPC_IRQ_LVL6            (PPC_STD_IRQ_LAST + 23)
552#define PPC_IRQ_IRQ7            (PPC_STD_IRQ_LAST + 24)
553#define PPC_IRQ_LVL7            (PPC_STD_IRQ_LAST + 25)
554#define PPC_IRQ_CPM_ERROR       (PPC_STD_IRQ_LAST + 26)
555#define PPC_IRQ_CPM_PC4         (PPC_STD_IRQ_LAST + 27)
556#define PPC_IRQ_CPM_PC5         (PPC_STD_IRQ_LAST + 28)
557#define PPC_IRQ_CPM_SMC2        (PPC_STD_IRQ_LAST + 29)
558#define PPC_IRQ_CPM_SMC1        (PPC_STD_IRQ_LAST + 30)
559#define PPC_IRQ_CPM_SPI         (PPC_STD_IRQ_LAST + 31)
560#define PPC_IRQ_CPM_PC6         (PPC_STD_IRQ_LAST + 32)
561#define PPC_IRQ_CPM_TIMER4      (PPC_STD_IRQ_LAST + 33)
562#define PPC_IRQ_CPM_RESERVED_8  (PPC_STD_IRQ_LAST + 34)
563#define PPC_IRQ_CPM_PC7         (PPC_STD_IRQ_LAST + 35)
564#define PPC_IRQ_CPM_PC8         (PPC_STD_IRQ_LAST + 36)
565#define PPC_IRQ_CPM_PC9         (PPC_STD_IRQ_LAST + 37)
566#define PPC_IRQ_CPM_TIMER3      (PPC_STD_IRQ_LAST + 38)
567#define PPC_IRQ_CPM_RESERVED_D  (PPC_STD_IRQ_LAST + 39)
568#define PPC_IRQ_CPM_PC10        (PPC_STD_IRQ_LAST + 40)
569#define PPC_IRQ_CPM_PC11        (PPC_STD_IRQ_LAST + 41)
570#define PPC_IRQ_CPM_I2C         (PPC_STD_IRQ_LAST + 42)
571#define PPC_IRQ_CPM_RISC_TIMER  (PPC_STD_IRQ_LAST + 43)
572#define PPC_IRQ_CPM_TIMER2      (PPC_STD_IRQ_LAST + 44)
573#define PPC_IRQ_CPM_RESERVED_13 (PPC_STD_IRQ_LAST + 45)
574#define PPC_IRQ_CPM_IDMA2       (PPC_STD_IRQ_LAST + 46)
575#define PPC_IRQ_CPM_IDMA1       (PPC_STD_IRQ_LAST + 47)
576#define PPC_IRQ_CPM_SDMA_ERROR  (PPC_STD_IRQ_LAST + 48)
577#define PPC_IRQ_CPM_PC12        (PPC_STD_IRQ_LAST + 49)
578#define PPC_IRQ_CPM_PC13        (PPC_STD_IRQ_LAST + 50)
579#define PPC_IRQ_CPM_TIMER1      (PPC_STD_IRQ_LAST + 51)
580#define PPC_IRQ_CPM_PC14        (PPC_STD_IRQ_LAST + 52)
581#define PPC_IRQ_CPM_SCC4        (PPC_STD_IRQ_LAST + 53)
582#define PPC_IRQ_CPM_SCC3        (PPC_STD_IRQ_LAST + 54)
583#define PPC_IRQ_CPM_SCC2        (PPC_STD_IRQ_LAST + 55)
584#define PPC_IRQ_CPM_SCC1        (PPC_STD_IRQ_LAST + 56)
585#define PPC_IRQ_CPM_PC15        (PPC_STD_IRQ_LAST + 57)
586
587#define PPC_IRQ_LAST             PPC_IRQ_CPM_PC15
588
589#elif defined(mpc8260)
590
591#define PPC_IRQ_INST_MISS       (PPC_STD_IRQ_LAST+1) /*0x1000-Instruction TLB miss*/
592#define PPC_IRQ_DATA_MISS       (PPC_STD_IRQ_LAST+2) /*0x1100-Data TLB miss */
593#define PPC_IRQ_DATA_L_MISS     (PPC_STD_IRQ_LAST+3) /*0x1200-Data TLB load miss */
594#define PPC_IRQ_DATA_S_MISS     (PPC_STD_IRQ_LAST+4) /*0x1300-Data TLB store miss */
595#define PPC_IRQ_INST_BPNT       (PPC_STD_IRQ_LAST+5) /*0x1400-Inst address breakpoint */
596#define PPC_IRQ_SYS_MGT         (PPC_STD_IRQ_LAST+6) /*0x1500-System Management */
597/* 0x1600 - 0x2F00 reserved */
598#define PPC_IRQ_CPM_NONE        (PPC_STD_IRQ_LAST + 50)
599#define PPC_IRQ_CPM_I2C         (PPC_STD_IRQ_LAST + 51)
600#define PPC_IRQ_CPM_SPI         (PPC_STD_IRQ_LAST + 52)
601#define PPC_IRQ_CPM_RISC_TIMER  (PPC_STD_IRQ_LAST + 53)
602#define PPC_IRQ_CPM_SMC1        (PPC_STD_IRQ_LAST + 54)
603#define PPC_IRQ_CPM_SMC2        (PPC_STD_IRQ_LAST + 55)
604#define PPC_IRQ_CPM_IDMA1       (PPC_STD_IRQ_LAST + 56)
605#define PPC_IRQ_CPM_IDMA2       (PPC_STD_IRQ_LAST + 57)
606#define PPC_IRQ_CPM_IDMA3       (PPC_STD_IRQ_LAST + 58)
607#define PPC_IRQ_CPM_IDMA4       (PPC_STD_IRQ_LAST + 59)
608#define PPC_IRQ_CPM_SDMA        (PPC_STD_IRQ_LAST + 60)
609#define PPC_IRQ_CPM_RES_A       (PPC_STD_IRQ_LAST + 61)
610#define PPC_IRQ_CPM_TIMER1      (PPC_STD_IRQ_LAST + 62)
611#define PPC_IRQ_CPM_TIMER2      (PPC_STD_IRQ_LAST + 63)
612#define PPC_IRQ_CPM_TIMER3      (PPC_STD_IRQ_LAST + 64)
613#define PPC_IRQ_CPM_TIMER4      (PPC_STD_IRQ_LAST + 65)
614#define PPC_IRQ_CPM_TMCNT       (PPC_STD_IRQ_LAST + 66)
615#define PPC_IRQ_CPM_PIT         (PPC_STD_IRQ_LAST + 67)
616#define PPC_IRQ_CPM_RES_B       (PPC_STD_IRQ_LAST + 68)
617#define PPC_IRQ_CPM_IRQ1        (PPC_STD_IRQ_LAST + 69)
618#define PPC_IRQ_CPM_IRQ2        (PPC_STD_IRQ_LAST + 70)
619#define PPC_IRQ_CPM_IRQ3        (PPC_STD_IRQ_LAST + 71)
620#define PPC_IRQ_CPM_IRQ4        (PPC_STD_IRQ_LAST + 72)
621#define PPC_IRQ_CPM_IRQ5        (PPC_STD_IRQ_LAST + 73)
622#define PPC_IRQ_CPM_IRQ6        (PPC_STD_IRQ_LAST + 74)
623#define PPC_IRQ_CPM_IRQ7        (PPC_STD_IRQ_LAST + 75)
624#define PPC_IRQ_CPM_RES_C       (PPC_STD_IRQ_LAST + 76)
625#define PPC_IRQ_CPM_RES_D       (PPC_STD_IRQ_LAST + 77)
626#define PPC_IRQ_CPM_RES_E       (PPC_STD_IRQ_LAST + 78)
627#define PPC_IRQ_CPM_RES_F       (PPC_STD_IRQ_LAST + 79)
628#define PPC_IRQ_CPM_RES_G       (PPC_STD_IRQ_LAST + 80)
629#define PPC_IRQ_CPM_RES_H       (PPC_STD_IRQ_LAST + 81)
630#define PPC_IRQ_CPM_FCC1        (PPC_STD_IRQ_LAST + 82)
631#define PPC_IRQ_CPM_FCC2        (PPC_STD_IRQ_LAST + 83)
632#define PPC_IRQ_CPM_FCC3        (PPC_STD_IRQ_LAST + 84)
633#define PPC_IRQ_CPM_RES_I       (PPC_STD_IRQ_LAST + 85)
634#define PPC_IRQ_CPM_MCC1        (PPC_STD_IRQ_LAST + 86)
635#define PPC_IRQ_CPM_MCC2        (PPC_STD_IRQ_LAST + 87)
636#define PPC_IRQ_CPM_RES_J       (PPC_STD_IRQ_LAST + 88)
637#define PPC_IRQ_CPM_RES_K       (PPC_STD_IRQ_LAST + 89)
638#define PPC_IRQ_CPM_SCC1        (PPC_STD_IRQ_LAST + 90)
639#define PPC_IRQ_CPM_SCC2        (PPC_STD_IRQ_LAST + 91)
640#define PPC_IRQ_CPM_SCC3        (PPC_STD_IRQ_LAST + 92)
641#define PPC_IRQ_CPM_SCC4        (PPC_STD_IRQ_LAST + 93)
642#define PPC_IRQ_CPM_RES_L       (PPC_STD_IRQ_LAST + 94)
643#define PPC_IRQ_CPM_RES_M       (PPC_STD_IRQ_LAST + 95)
644#define PPC_IRQ_CPM_RES_N       (PPC_STD_IRQ_LAST + 96)
645#define PPC_IRQ_CPM_RES_O       (PPC_STD_IRQ_LAST + 97)
646#define PPC_IRQ_CPM_PC15        (PPC_STD_IRQ_LAST + 98)
647#define PPC_IRQ_CPM_PC14        (PPC_STD_IRQ_LAST + 99)
648#define PPC_IRQ_CPM_PC13        (PPC_STD_IRQ_LAST + 100)
649#define PPC_IRQ_CPM_PC12        (PPC_STD_IRQ_LAST + 101)
650#define PPC_IRQ_CPM_PC11        (PPC_STD_IRQ_LAST + 102)
651#define PPC_IRQ_CPM_PC10        (PPC_STD_IRQ_LAST + 103)
652#define PPC_IRQ_CPM_PC9         (PPC_STD_IRQ_LAST + 104)
653#define PPC_IRQ_CPM_PC8         (PPC_STD_IRQ_LAST + 105)
654#define PPC_IRQ_CPM_PC7         (PPC_STD_IRQ_LAST + 106)
655#define PPC_IRQ_CPM_PC6         (PPC_STD_IRQ_LAST + 107)
656#define PPC_IRQ_CPM_PC5         (PPC_STD_IRQ_LAST + 108)
657#define PPC_IRQ_CPM_PC4         (PPC_STD_IRQ_LAST + 109)
658#define PPC_IRQ_CPM_PC3         (PPC_STD_IRQ_LAST + 110)
659#define PPC_IRQ_CPM_PC2         (PPC_STD_IRQ_LAST + 111)
660#define PPC_IRQ_CPM_PC1         (PPC_STD_IRQ_LAST + 112)
661#define PPC_IRQ_CPM_PC0         (PPC_STD_IRQ_LAST + 113)
662
663#define PPC_IRQ_LAST             PPC_IRQ_CPM_PC0
664
665#endif
666
667
668/*
669 *  If the maximum number of exception sources is too low,
670 *  then fix it
671 */
672
673#if PPC_INTERRUPT_MAX <= PPC_IRQ_LAST
674#undef PPC_INTERRUPT_MAX
675#define PPC_INTERRUPT_MAX ((PPC_IRQ_LAST) + 1)
676#endif
677
678/*
679 *  Machine Status Register (MSR) Constants Used by RTEMS
680 */
681
682/*
683 *  Some PPC model manuals refer to the Exception Prefix (EP) bit as
684 *  IP for no apparent reason.
685 */
686
687#define PPC_MSR_RI       0x000000002 /* bit 30 - recoverable exception */
688#define PPC_MSR_DR       0x000000010 /* bit 27 - data address translation */
689#define PPC_MSR_IR       0x000000020 /* bit 26 - instruction addr translation*/
690
691#if (PPC_HAS_EXCEPTION_PREFIX)
692#define PPC_MSR_EP       0x000000040 /* bit 25 - exception prefix */
693#else
694#define PPC_MSR_EP       0x000000000 /* bit 25 - exception prefix */
695#endif
696
697#if (PPC_HAS_FPU)
698#define PPC_MSR_FP       0x000002000 /* bit 18 - floating point enable */
699#else
700#define PPC_MSR_FP       0x000000000 /* bit 18 - floating point enable */
701#endif
702
703#if (PPC_LOW_POWER_MODE == PPC_LOW_POWER_MODE_NONE)
704#define PPC_MSR_POW      0x000000000 /* bit 13 - power management enable */
705#else
706#define PPC_MSR_POW      0x000040000 /* bit 13 - power management enable */
707#endif
708
709#define PPC_MSR_ME       0x000001000 /* bit 19 - machine check enable */
710#define PPC_MSR_EE       0x000008000 /* bit 16 - external interrupt enable */
711
712#if (PPC_HAS_RFCI)
713#define PPC_MSR_CE       0x000020000 /* bit 14 - critical interrupt enable */
714#else
715#define PPC_MSR_CE       0x000000000 /* bit 14 - critical interrupt enable */
716#endif
717
718#define PPC_MSR_DISABLE_MASK (PPC_MSR_ME|PPC_MSR_EE|PPC_MSR_CE)
719
720/*
721 *  Initial value for the FPSCR register
722 */
723
724#define PPC_INIT_FPSCR          0x000000f8
725
726#ifdef __cplusplus
727}
728#endif
729
730#endif /* ! _INCLUDE_PPC_h */
731/* end of include file */
732
733
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