1 | /* ppc.h |
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2 | * |
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3 | * This file contains definitions for the IBM/Motorola PowerPC |
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4 | * family members. |
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5 | * |
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6 | * Author: Andrew Bray <andy@i-cubed.co.uk> |
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7 | * |
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8 | * COPYRIGHT (c) 1995 by i-cubed ltd. |
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9 | * |
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10 | * To anyone who acknowledges that this file is provided "AS IS" |
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11 | * without any express or implied warranty: |
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12 | * permission to use, copy, modify, and distribute this file |
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13 | * for any purpose is hereby granted without fee, provided that |
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14 | * the above copyright notice and this notice appears in all |
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15 | * copies, and that the name of i-cubed limited not be used in |
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16 | * advertising or publicity pertaining to distribution of the |
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17 | * software without specific, written prior permission. |
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18 | * i-cubed limited makes no representations about the suitability |
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19 | * of this software for any purpose. |
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20 | * |
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21 | * Derived from c/src/exec/cpu/no_cpu/no_cpu.h: |
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22 | * |
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23 | * COPYRIGHT (c) 1989-1997. |
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24 | * On-Line Applications Research Corporation (OAR). |
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25 | * |
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26 | * The license and distribution terms for this file may in |
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27 | * the file LICENSE in this distribution or at |
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28 | * http://www.OARcorp.com/rtems/license.html. |
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29 | * |
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30 | * |
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31 | * Note: |
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32 | * This file is included by both C and assembler code ( -DASM ) |
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33 | * |
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34 | * $Id$ |
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35 | */ |
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36 | |
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37 | |
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38 | #ifndef _INCLUDE_PPC_h |
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39 | #define _INCLUDE_PPC_h |
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40 | |
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41 | #ifdef __cplusplus |
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42 | extern "C" { |
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43 | #endif |
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44 | |
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45 | /* |
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46 | * Define the name of the CPU family. |
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47 | */ |
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48 | |
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49 | #define CPU_NAME "PowerPC" |
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50 | |
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51 | /* |
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52 | * This file contains the information required to build |
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53 | * RTEMS for a particular member of the PowerPC family. It does |
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54 | * this by setting variables to indicate which implementation |
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55 | * dependent features are present in a particular member |
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56 | * of the family. |
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57 | * |
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58 | * The following architectural feature definitions are defaulted |
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59 | * unless specifically set by the model definition: |
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60 | * |
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61 | * + PPC_DEBUG_MODEL - PPC_DEBUG_MODEL_STANDARD |
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62 | * + PPC_INTERRUPT_MAX - 16 |
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63 | * + PPC_CACHE_ALIGNMENT - 32 |
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64 | * + PPC_LOW_POWER_MODE - PPC_LOW_POWER_MODE_NONE |
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65 | * + PPC_HAS_EXCEPTION_PREFIX - 1 |
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66 | * + PPC_HAS_FPU - 1 |
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67 | * + PPC_HAS_DOUBLE - 1 if PPC_HAS_FPU, |
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68 | * - 0 otherwise |
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69 | * + PPC_USE_MULTIPLE - 0 |
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70 | */ |
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71 | |
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72 | /* |
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73 | * Define the debugging assistance models found in the PPC family. |
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74 | * |
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75 | * Standard: single step and branch trace |
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76 | * Single Step Only: single step only |
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77 | * IBM 4xx: debug exception |
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78 | */ |
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79 | |
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80 | #define PPC_DEBUG_MODEL_STANDARD 1 |
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81 | #define PPC_DEBUG_MODEL_SINGLE_STEP_ONLY 2 |
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82 | #define PPC_DEBUG_MODEL_IBM4xx 3 |
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83 | |
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84 | /* |
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85 | * Define the low power mode models |
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86 | * |
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87 | * Standard: as defined for 603e |
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88 | * Nap Mode: nap mode only (604) |
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89 | * XXX 403GB, 603, 603e, 604, 821 |
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90 | */ |
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91 | |
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92 | #define PPC_LOW_POWER_MODE_NONE 0 |
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93 | #define PPC_LOW_POWER_MODE_STANDARD 1 |
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94 | |
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95 | #if defined(ppc403) |
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96 | /* |
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97 | * IBM 403 |
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98 | * |
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99 | * Developed for 403GA. Book checked for 403GB. |
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100 | * |
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101 | * Does not have user mode. |
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102 | */ |
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103 | |
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104 | #define CPU_MODEL_NAME "PowerPC 403" |
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105 | #define PPC_ALIGNMENT 4 |
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106 | #define PPC_CACHE_ALIGNMENT 16 |
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107 | #define PPC_HAS_RFCI 1 |
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108 | #define PPC_HAS_FPU 0 |
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109 | #define PPC_USE_MULTIPLE 1 |
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110 | #define PPC_I_CACHE 2048 |
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111 | #define PPC_D_CACHE 1024 |
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112 | |
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113 | #define PPC_DEBUG_MODEL PPC_DEBUG_MODEL_IBM4xx |
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114 | #define PPC_HAS_EXCEPTION_PREFIX 0 |
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115 | #define PPC_HAS_EVPR 1 |
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116 | |
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117 | #elif defined(ppc601) |
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118 | /* |
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119 | * Submitted with original port -- book checked only. |
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120 | */ |
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121 | |
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122 | #define CPU_MODEL_NAME "PowerPC 601" |
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123 | |
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124 | #define PPC_ALIGNMENT 8 |
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125 | #define PPC_USE_MULTIPLE 1 |
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126 | #define PPC_I_CACHE 0 |
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127 | #define PPC_D_CACHE 32768 |
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128 | |
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129 | #define PPC_DEBUG_MODEL PPC_DEBUG_MODEL_SINGLE_STEP_ONLY |
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130 | |
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131 | #elif defined(ppc602) |
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132 | /* |
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133 | * Submitted with original port -- book checked only. |
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134 | */ |
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135 | |
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136 | #define CPU_MODEL_NAME "PowerPC 602" |
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137 | |
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138 | #define PPC_ALIGNMENT 4 |
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139 | #define PPC_HAS_DOUBLE 0 |
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140 | #define PPC_I_CACHE 4096 |
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141 | #define PPC_D_CACHE 4096 |
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142 | |
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143 | #elif defined(ppc603) |
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144 | /* |
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145 | * Submitted with original port -- book checked only. |
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146 | */ |
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147 | |
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148 | #define CPU_MODEL_NAME "PowerPC 603" |
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149 | |
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150 | #define PPC_ALIGNMENT 8 |
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151 | #define PPC_I_CACHE 8192 |
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152 | #define PPC_D_CACHE 8192 |
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153 | |
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154 | #elif defined(ppc603e) |
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155 | |
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156 | #define CPU_MODEL_NAME "PowerPC 603e" |
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157 | /* |
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158 | * Submitted with original port. |
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159 | * |
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160 | * Known to work on real hardware. |
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161 | */ |
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162 | |
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163 | #define PPC_ALIGNMENT 8 |
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164 | #define PPC_I_CACHE 16384 |
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165 | #define PPC_D_CACHE 16384 |
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166 | |
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167 | #define PPC_LOW_POWER_MODE PPC_LOW_POWER_MODE_STANDARD |
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168 | |
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169 | #elif defined(ppc604) |
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170 | /* |
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171 | * Submitted with original port -- book checked only. |
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172 | */ |
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173 | |
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174 | #define CPU_MODEL_NAME "PowerPC 604" |
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175 | |
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176 | #define PPC_ALIGNMENT 8 |
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177 | #define PPC_I_CACHE 16384 |
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178 | #define PPC_D_CACHE 16384 |
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179 | |
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180 | #else |
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181 | |
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182 | #error "Unsupported CPU Model" |
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183 | |
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184 | #endif |
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185 | |
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186 | /* |
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187 | * Application binary interfaces. |
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188 | * |
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189 | * PPC_ABI MUST be defined as one of these. |
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190 | * Only PPC_ABI_POWEROPEN is currently fully supported. |
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191 | * Only EABI will be supported in the end when |
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192 | * the tools are there. |
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193 | * Only big endian is currently supported. |
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194 | */ |
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195 | /* |
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196 | * PowerOpen ABI. This is Andy's hack of the |
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197 | * PowerOpen ABI to ELF. ELF rather than a |
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198 | * XCOFF assembler is used. This may work |
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199 | * if PPC_ASM == PPC_ASM_XCOFF is defined. |
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200 | */ |
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201 | #define PPC_ABI_POWEROPEN 0 |
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202 | /* |
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203 | * GCC 2.7.0 munched version of EABI, with |
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204 | * PowerOpen calling convention and stack frames, |
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205 | * but EABI style indirect function calls. |
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206 | */ |
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207 | #define PPC_ABI_GCC27 1 |
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208 | /* |
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209 | * SVR4 ABI |
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210 | */ |
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211 | #define PPC_ABI_SVR4 2 |
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212 | /* |
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213 | * Embedded ABI |
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214 | */ |
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215 | #define PPC_ABI_EABI 3 |
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216 | |
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217 | #if (PPC_ABI == PPC_ABI_POWEROPEN) |
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218 | #define PPC_STACK_ALIGNMENT 8 |
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219 | #elif (PPC_ABI == PPC_ABI_GCC27) |
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220 | #define PPC_STACK_ALIGNMENT 8 |
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221 | #elif (PPC_ABI == PPC_ABI_SVR4) |
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222 | #define PPC_STACK_ALIGNMENT 16 |
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223 | #elif (PPC_ABI == PPC_ABI_EABI) |
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224 | #define PPC_STACK_ALIGNMENT 8 |
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225 | #else |
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226 | #error "PPC_ABI is not properly defined" |
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227 | #endif |
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228 | #ifndef PPC_ABI |
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229 | #error "PPC_ABI is not properly defined" |
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230 | #endif |
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231 | |
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232 | /* |
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233 | * Assemblers. |
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234 | * PPC_ASM MUST be defined as one of these. |
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235 | * |
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236 | * PPC_ASM_ELF: ELF assembler. Currently used for all ABIs. |
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237 | * PPC_ASM_XCOFF: XCOFF assembler. May be needed for PowerOpen ABI. |
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238 | * |
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239 | * NOTE: Only PPC_ABI_ELF is currently fully supported. |
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240 | */ |
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241 | |
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242 | #define PPC_ASM_ELF 0 |
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243 | #define PPC_ASM_XCOFF 1 |
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244 | |
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245 | /* |
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246 | * Use the default debug scheme defined in the architectural specification |
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247 | * if another model has not been specified. |
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248 | */ |
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249 | |
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250 | #ifndef PPC_DEBUG_MODEL |
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251 | #define PPC_DEBUG_MODEL PPC_DEBUG_MODEL_STANDARD |
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252 | #endif |
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253 | |
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254 | /* |
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255 | * If the maximum number of exception sources has not been defined, |
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256 | * then default it to 16. |
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257 | */ |
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258 | |
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259 | #ifndef PPC_INTERRUPT_MAX |
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260 | #define PPC_INTERRUPT_MAX 16 |
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261 | #endif |
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262 | |
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263 | /* |
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264 | * Unless specified otherwise, the cache line size is defaulted to 32. |
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265 | * |
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266 | * The derive the power of 2 the cache line is. |
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267 | */ |
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268 | |
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269 | #ifndef PPC_CACHE_ALIGNMENT |
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270 | #define PPC_CACHE_ALIGNMENT 32 |
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271 | #endif |
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272 | |
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273 | #if (PPC_CACHE_ALIGNMENT == 16) |
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274 | #define PPC_CACHE_ALIGN_POWER 4 |
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275 | #elif (PPC_CACHE_ALIGNMENT == 32) |
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276 | #define PPC_CACHE_ALIGN_POWER 5 |
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277 | #else |
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278 | #error "Undefined power of 2 for PPC_CACHE_ALIGNMENT" |
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279 | #endif |
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280 | |
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281 | /* |
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282 | * Unless otherwise specified, assume the model has an IP/EP bit to |
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283 | * set the exception address prefix. |
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284 | */ |
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285 | |
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286 | #ifndef PPC_HAS_EXCEPTION_PREFIX |
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287 | #define PPC_HAS_EXCEPTION_PREFIX 1 |
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288 | #endif |
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289 | |
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290 | /* |
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291 | * Unless otherwise specified, assume the model does NOT have |
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292 | * 403 style EVPR register to set the exception address prefix. |
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293 | */ |
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294 | |
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295 | #ifndef PPC_HAS_EVPR |
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296 | #define PPC_HAS_EVPR 0 |
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297 | #endif |
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298 | |
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299 | /* |
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300 | * If no low power mode model was specified, then assume there is none. |
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301 | */ |
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302 | |
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303 | #ifndef PPC_LOW_POWER_MODE |
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304 | #define PPC_LOW_POWER_MODE PPC_LOW_POWER_MODE_NONE |
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305 | #endif |
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306 | |
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307 | /* |
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308 | * Unless specified above, then assume the model has FP support. |
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309 | */ |
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310 | |
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311 | #ifndef PPC_HAS_FPU |
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312 | #define PPC_HAS_FPU 1 |
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313 | #endif |
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314 | |
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315 | /* |
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316 | * Unless specified above, If the model has FP support, it is assumed to |
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317 | * support doubles (8-byte floating point numbers). |
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318 | * |
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319 | * If the model does NOT have FP support, then the model does |
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320 | * NOT have double length FP registers. |
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321 | */ |
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322 | |
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323 | #ifndef PPC_HAS_DOUBLE |
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324 | #if (PPC_HAS_FPU) |
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325 | #define PPC_HAS_DOUBLE 1 |
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326 | #else |
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327 | #define PPC_HAS_DOUBLE 0 |
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328 | #endif |
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329 | #endif |
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330 | |
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331 | /* |
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332 | * Unless specified above, then assume the model does NOT have critical |
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333 | * interrupt support. |
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334 | */ |
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335 | |
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336 | #ifndef PPC_HAS_RFCI |
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337 | #define PPC_HAS_RFCI 0 |
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338 | #endif |
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339 | |
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340 | /* |
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341 | * Unless specified above, do not use the load/store multiple instructions |
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342 | * in a context switch. |
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343 | */ |
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344 | |
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345 | #ifndef PPC_USE_MULTIPLE |
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346 | #define PPC_USE_MULTIPLE 0 |
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347 | #endif |
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348 | |
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349 | /* |
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350 | * The following exceptions are not maskable, and are not |
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351 | * necessarily predictable, so cannot be offered to RTEMS: |
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352 | * Alignment exception - handled by the CPU module |
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353 | * Data exceptions. |
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354 | * Instruction exceptions. |
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355 | */ |
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356 | |
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357 | /* |
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358 | * Base Interrupt vectors supported on all models. |
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359 | */ |
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360 | #define PPC_IRQ_SYSTEM_RESET 0 /* 0x00100 - System reset. */ |
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361 | #define PPC_IRQ_MCHECK 1 /* 0x00200 - Machine check */ |
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362 | #define PPC_IRQ_PROTECT 2 /* 0x00300 - Protection violation */ |
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363 | #define PPC_IRQ_ISI 3 /* 0x00400 - Instruction Fetch error */ |
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364 | #define PPC_IRQ_EXTERNAL 4 /* 0x00500 - External interrupt */ |
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365 | #define PPC_IRQ_ALIGNMENT 5 /* 0X00600 - Alignment exception */ |
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366 | #define PPC_IRQ_PROGRAM 6 /* 0x00700 - Program exception */ |
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367 | #define PPC_IRQ_NOFP 7 /* 0x00800 - Floating point unavailable */ |
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368 | #define PPC_IRQ_DECREMENTER 8 /* 0x00900 - Decrementer interrupt */ |
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369 | #define PPC_IRQ_RESERVED_A 9 /* 0x00a00 - Implementation Reserved */ |
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370 | #define PPC_IRQ_RESERVED_B 10 /* 0x00a00 - Implementation Reserved */ |
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371 | #define PPC_IRQ_SCALL 11 /* 0x00c00 - System call */ |
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372 | #define PPC_IRQ_TRACE 12 /* 0x00d00 - Trace Exception */ |
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373 | #define PPC_IRQ_FP_ASST 13 /* ox00e00 - Floating point assist */ |
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374 | #define PPC_STD_IRQ_LAST PPC_IRQ_FP_ASST |
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375 | |
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376 | #define PPC_IRQ_FIRST PPC_IRQ_SYSTEM_RESET |
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377 | |
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378 | #if defined(ppc403) |
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379 | |
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380 | #define PPC_IRQ_CRIT PPC_IRQ_SYSTEM_RESET /*0x00100- Critical int. pin */ |
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381 | #define PPC_IRQ_PIT (PPC_STD_IRQ_LAST+1) /*0x01000- Pgm interval timer*/ |
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382 | #define PPC_IRQ_FIT (PPC_STD_IRQ_LAST+2) /*0x01010- Fixed int. timer */ |
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383 | #define PPC_IRQ_WATCHDOG (PPC_STD_IRQ_LAST+3) /*0x01020- Watchdog timer */ |
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384 | #define PPC_IRQ_DEBUG (PPC_STD_IRQ_LAST+4) /*0x02000- Debug exceptions */ |
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385 | #define PPC_IRQ_LAST PPC_IRQ_DEBUG |
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386 | |
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387 | #elif defined(ppc601) |
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388 | #define PPC_IRQ_TRACE (PPC_STD_IRQ_LAST+1) /*0x02000-Run/Trace Exception*/ |
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389 | #define PPC_IRQ_LAST PPC_IRQ_TRACE |
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390 | |
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391 | #elif defined(ppc602) |
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392 | #define PPC_IRQ_LAST (PPC_STD_IRQ_LAST) |
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393 | |
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394 | #elif defined(ppc603) |
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395 | #define PPC_IRQ_TRANS_MISS (PPC_STD_IRQ_LAST+1) /*0x1000-Ins Translation Miss*/ |
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396 | #define PPC_IRQ_DATA_LOAD (PPC_STD_IRQ_LAST+2) /*0x1100-Data Load Trans Miss*/ |
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397 | #define PPC_IRQ_DATA_STORE (PPC_STD_IRQ_LAST+3) /*0x1200-Data Store Miss */ |
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398 | #define PPC_IRQ_ADDR_BRK (PPC_STD_IRQ_LAST+4) /*0x1300-Instruction Bkpoint */ |
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399 | #define PPC_IRQ_SYS_MGT (PPC_STD_IRQ_LAST+5) /*0x1400-System Management */ |
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400 | #define PPC_IRQ_LAST PPC_IRQ_SYS_MGT |
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401 | |
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402 | #elif defined(ppc603e) |
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403 | #define PPC_TLB_INST_MISS (PPC_STD_IRQ_LAST+1) /*0x1000-Instruction TLB Miss*/ |
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404 | #define PPC_TLB_LOAD_MISS (PPC_STD_IRQ_LAST+2) /*0x1100-TLB miss on load */ |
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405 | #define PPC_TLB_STORE_MISS (PPC_STD_IRQ_LAST+3) /*0x1200-TLB Miss on store */ |
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406 | #define PPC_IRQ_ADDRBRK (PPC_STD_IRQ_LAST+4) /*0x1300-Instruct addr break */ |
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407 | #define PPC_IRQ_SYS_MGT (PPC_STD_IRQ_LAST+5) /*0x1400-System Management */ |
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408 | #define PPC_IRQ_LAST PPC_IRQ_SYS_MGT |
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409 | |
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410 | |
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411 | #elif defined(ppc604) |
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412 | #define PPC_IRQ_ADDR_BRK (PPC_STD_IRQ_LAST+1) /*0x1300- Inst. addr break */ |
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413 | #define PPC_IRQ_SYS_MGT (PPC_STD_IRQ_LAST+2) /*0x1400- System Management */ |
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414 | #define PPC_IRQ_LAST PPC604_IRQ_SYS_MGT |
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415 | |
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416 | #endif |
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417 | |
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418 | /* |
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419 | * Machine Status Register (MSR) Constants Used by RTEMS |
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420 | */ |
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421 | |
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422 | /* |
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423 | * Some PPC model manuals refer to the Exception Prefix (EP) bit as |
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424 | * IP for no apparent reason. |
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425 | */ |
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426 | |
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427 | #define PPC_MSR_RI 0x000000002 /* bit 30 - recoverable exception */ |
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428 | #define PPC_MSR_DR 0x000000010 /* bit 27 - data address translation */ |
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429 | #define PPC_MSR_IR 0x000000020 /* bit 26 - instruction addr translation*/ |
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430 | |
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431 | #if (PPC_HAS_EXCEPTION_PREFIX) |
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432 | #define PPC_MSR_EP 0x000000040 /* bit 25 - exception prefix */ |
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433 | #else |
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434 | #define PPC_MSR_EP 0x000000000 /* bit 25 - exception prefix */ |
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435 | #endif |
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436 | |
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437 | #if (PPC_HAS_FPU) |
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438 | #define PPC_MSR_FP 0x000002000 /* bit 18 - floating point enable */ |
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439 | #else |
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440 | #define PPC_MSR_FP 0x000000000 /* bit 18 - floating point enable */ |
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441 | #endif |
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442 | |
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443 | #if (PPC_LOW_POWER_MODE == PPC_LOW_POWER_MODE_NONE) |
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444 | #define PPC_MSR_POW 0x000000000 /* bit 13 - power management enable */ |
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445 | #else |
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446 | #define PPC_MSR_POW 0x000040000 /* bit 13 - power management enable */ |
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447 | #endif |
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448 | |
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449 | /* |
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450 | * Interrupt/exception MSR bits set as defined on p. 2-20 in "The Programming |
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451 | * Environments" and the manuals for various PPC models. |
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452 | */ |
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453 | |
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454 | #if (PPC_DEBUG_MODEL == PPC_DEBUG_MODEL_STANDARD) |
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455 | #define PPC_MSR_DE 0x000000000 /* bit 22 - debug exception enable */ |
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456 | #define PPC_MSR_BE 0x000000200 /* bit 22 - branch trace enable */ |
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457 | #define PPC_MSR_SE 0x000000400 /* bit 21 - single step trace enable */ |
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458 | #elif (PPC_DEBUG_MODEL == PPC_DEBUG_MODEL_SINGLE_STEP_ONLY) |
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459 | #define PPC_MSR_DE 0x000000000 /* bit 22 - debug exception enable */ |
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460 | #define PPC_MSR_BE 0x000000200 /* bit 22 - branch trace enable */ |
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461 | #define PPC_MSR_SE 0x000000000 /* bit 21 - single step trace enable */ |
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462 | #elif (PPC_DEBUG_MODEL == PPC_DEBUG_MODEL_IBM4xx) |
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463 | #define PPC_MSR_DE 0x000000200 /* bit 22 - debug exception enable */ |
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464 | #define PPC_MSR_BE 0x000000000 /* bit 22 - branch trace enable */ |
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465 | #define PPC_MSR_SE 0x000000000 /* bit 21 - single step trace enable */ |
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466 | #else |
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467 | #error "MSR constants -- unknown PPC_DEBUG_MODEL!!" |
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468 | #endif |
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469 | |
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470 | #define PPC_MSR_ME 0x000001000 /* bit 19 - machine check enable */ |
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471 | #define PPC_MSR_EE 0x000008000 /* bit 16 - external interrupt enable */ |
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472 | |
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473 | #if (PPC_HAS_RFCI) |
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474 | #define PPC_MSR_CE 0x000020000 /* bit 14 - critical interrupt enable */ |
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475 | #else |
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476 | #define PPC_MSR_CE 0x000000000 /* bit 14 - critical interrupt enable */ |
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477 | #endif |
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478 | |
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479 | #define PPC_MSR_DISABLE_MASK (PPC_MSR_ME|PPC_MSR_EE|PPC_MSR_CE) |
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480 | |
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481 | /* |
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482 | * Initial value for the FPSCR register |
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483 | */ |
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484 | |
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485 | #define PPC_INIT_FPSCR 0x000000f8 |
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486 | |
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487 | #ifdef __cplusplus |
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488 | } |
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489 | #endif |
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490 | |
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491 | #endif /* ! _INCLUDE_PPC_h */ |
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492 | /* end of include file */ |
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493 | |
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494 | |
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