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cpu_asm.s @ 60b791ad

4.104.114.84.95

Last change on this file since 60b791ad was 60b791ad, checked in by Joel Sherrill <joel.sherrill@…>, on 02/17/98 at 23:46:28
updated copyright to 1998
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File size: 16.1 KB

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1
2	/* cpu_asm.s 1.1 - 95/12/04
3	*
4	* This file contains the assembly code for the PowerPC implementation
5	* of RTEMS.
6	*
7	* Author: Andrew Bray <andy@i-cubed.co.uk>
8	*
9	* COPYRIGHT (c) 1995 by i-cubed ltd.
10	*
11	* To anyone who acknowledges that this file is provided "AS IS"
12	* without any express or implied warranty:
13	* permission to use, copy, modify, and distribute this file
14	* for any purpose is hereby granted without fee, provided that
15	* the above copyright notice and this notice appears in all
16	* copies, and that the name of i-cubed limited not be used in
17	* advertising or publicity pertaining to distribution of the
18	* software without specific, written prior permission.
19	* i-cubed limited makes no representations about the suitability
20	* of this software for any purpose.
21	*
22	* Derived from c/src/exec/cpu/no_cpu/cpu_asm.c:
23	*
24	* COPYRIGHT (c) 1989-1998.
25	* On-Line Applications Research Corporation (OAR).
26	* Copyright assigned to U.S. Government, 1994.
27	*
28	* The license and distribution terms for this file may be
29	* found in the file LICENSE in this distribution or at
30	* http://www.OARcorp.com/rtems/license.html.
31	*
32	* $Id$
33	*/
34
35	#include <asm.h>
36
37	/*
38	* Offsets for various Contexts
39	*/
40	.set GP_1, 0
41	.set GP_2, (GP_1 + 4)
42	.set GP_13, (GP_2 + 4)
43	.set GP_14, (GP_13 + 4)
44
45	.set GP_15, (GP_14 + 4)
46	.set GP_16, (GP_15 + 4)
47	.set GP_17, (GP_16 + 4)
48	.set GP_18, (GP_17 + 4)
49
50	.set GP_19, (GP_18 + 4)
51	.set GP_20, (GP_19 + 4)
52	.set GP_21, (GP_20 + 4)
53	.set GP_22, (GP_21 + 4)
54
55	.set GP_23, (GP_22 + 4)
56	.set GP_24, (GP_23 + 4)
57	.set GP_25, (GP_24 + 4)
58	.set GP_26, (GP_25 + 4)
59
60	.set GP_27, (GP_26 + 4)
61	.set GP_28, (GP_27 + 4)
62	.set GP_29, (GP_28 + 4)
63	.set GP_30, (GP_29 + 4)
64
65	.set GP_31, (GP_30 + 4)
66	.set GP_CR, (GP_31 + 4)
67	.set GP_PC, (GP_CR + 4)
68	.set GP_MSR, (GP_PC + 4)
69
70	#if (PPC_HAS_DOUBLE == 1)
71	.set FP_0, 0
72	.set FP_1, (FP_0 + 8)
73	.set FP_2, (FP_1 + 8)
74	.set FP_3, (FP_2 + 8)
75	.set FP_4, (FP_3 + 8)
76	.set FP_5, (FP_4 + 8)
77	.set FP_6, (FP_5 + 8)
78	.set FP_7, (FP_6 + 8)
79	.set FP_8, (FP_7 + 8)
80	.set FP_9, (FP_8 + 8)
81	.set FP_10, (FP_9 + 8)
82	.set FP_11, (FP_10 + 8)
83	.set FP_12, (FP_11 + 8)
84	.set FP_13, (FP_12 + 8)
85	.set FP_14, (FP_13 + 8)
86	.set FP_15, (FP_14 + 8)
87	.set FP_16, (FP_15 + 8)
88	.set FP_17, (FP_16 + 8)
89	.set FP_18, (FP_17 + 8)
90	.set FP_19, (FP_18 + 8)
91	.set FP_20, (FP_19 + 8)
92	.set FP_21, (FP_20 + 8)
93	.set FP_22, (FP_21 + 8)
94	.set FP_23, (FP_22 + 8)
95	.set FP_24, (FP_23 + 8)
96	.set FP_25, (FP_24 + 8)
97	.set FP_26, (FP_25 + 8)
98	.set FP_27, (FP_26 + 8)
99	.set FP_28, (FP_27 + 8)
100	.set FP_29, (FP_28 + 8)
101	.set FP_30, (FP_29 + 8)
102	.set FP_31, (FP_30 + 8)
103	.set FP_FPSCR, (FP_31 + 8)
104	#else
105	.set FP_0, 0
106	.set FP_1, (FP_0 + 4)
107	.set FP_2, (FP_1 + 4)
108	.set FP_3, (FP_2 + 4)
109	.set FP_4, (FP_3 + 4)
110	.set FP_5, (FP_4 + 4)
111	.set FP_6, (FP_5 + 4)
112	.set FP_7, (FP_6 + 4)
113	.set FP_8, (FP_7 + 4)
114	.set FP_9, (FP_8 + 4)
115	.set FP_10, (FP_9 + 4)
116	.set FP_11, (FP_10 + 4)
117	.set FP_12, (FP_11 + 4)
118	.set FP_13, (FP_12 + 4)
119	.set FP_14, (FP_13 + 4)
120	.set FP_15, (FP_14 + 4)
121	.set FP_16, (FP_15 + 4)
122	.set FP_17, (FP_16 + 4)
123	.set FP_18, (FP_17 + 4)
124	.set FP_19, (FP_18 + 4)
125	.set FP_20, (FP_19 + 4)
126	.set FP_21, (FP_20 + 4)
127	.set FP_22, (FP_21 + 4)
128	.set FP_23, (FP_22 + 4)
129	.set FP_24, (FP_23 + 4)
130	.set FP_25, (FP_24 + 4)
131	.set FP_26, (FP_25 + 4)
132	.set FP_27, (FP_26 + 4)
133	.set FP_28, (FP_27 + 4)
134	.set FP_29, (FP_28 + 4)
135	.set FP_30, (FP_29 + 4)
136	.set FP_31, (FP_30 + 4)
137	.set FP_FPSCR, (FP_31 + 4)
138	#endif
139
140	.set IP_LINK, 0
141	#if (PPC_ABI == PPC_ABI_POWEROPEN \|\| PPC_ABI == PPC_ABI_GCC27)
142	.set IP_0, (IP_LINK + 56)
143	#else
144	.set IP_0, (IP_LINK + 8)
145	#endif
146	.set IP_2, (IP_0 + 4)
147
148	.set IP_3, (IP_2 + 4)
149	.set IP_4, (IP_3 + 4)
150	.set IP_5, (IP_4 + 4)
151	.set IP_6, (IP_5 + 4)
152
153	.set IP_7, (IP_6 + 4)
154	.set IP_8, (IP_7 + 4)
155	.set IP_9, (IP_8 + 4)
156	.set IP_10, (IP_9 + 4)
157
158	.set IP_11, (IP_10 + 4)
159	.set IP_12, (IP_11 + 4)
160	.set IP_13, (IP_12 + 4)
161	.set IP_28, (IP_13 + 4)
162
163	.set IP_29, (IP_28 + 4)
164	.set IP_30, (IP_29 + 4)
165	.set IP_31, (IP_30 + 4)
166	.set IP_CR, (IP_31 + 4)
167
168	.set IP_CTR, (IP_CR + 4)
169	.set IP_XER, (IP_CTR + 4)
170	.set IP_LR, (IP_XER + 4)
171	.set IP_PC, (IP_LR + 4)
172
173	.set IP_MSR, (IP_PC + 4)
174	.set IP_END, (IP_MSR + 16)
175
176	/* _CPU_IRQ_info offsets */
177	/* These must be in this order */
178	.set Nest_level, 0
179	.set Disable_level, 4
180	.set Vector_table, 8
181	.set Stack, 12
182	#if (PPC_ABI == PPC_ABI_POWEROPEN)
183	.set Dispatch_r2, 16
184	.set Switch_necessary, 20
185	#else
186	.set Default_r2, 16
187	#if (PPC_ABI != PPC_ABI_GCC27)
188	.set Default_r13, 20
189	.set Switch_necessary, 24
190	#else
191	.set Switch_necessary, 20
192	#endif
193	#endif
194	.set Signal, Switch_necessary + 4
195
196	BEGIN_CODE
197	/*
198	* _CPU_Context_save_fp_context
199	*
200	* This routine is responsible for saving the FP context
201	* at *fp_context_ptr. If the point to load the FP context
202	* from is changed then the pointer is modified by this routine.
203	*
204	* Sometimes a macro implementation of this is in cpu.h which dereferences
205	* the ** and a similarly named routine in this file is passed something
206	* like a (Context_Control_fp *). The general rule on making this decision
207	* is to avoid writing assembly language.
208	*/
209
210	ALIGN (PPC_CACHE_ALIGNMENT, PPC_CACHE_ALIGN_POWER)
211	PUBLIC_PROC (_CPU_Context_save_fp)
212	PROC (_CPU_Context_save_fp):
213	#if (PPC_HAS_FPU == 1)
214	lwz r3, 0(r3)
215	#if (PPC_HAS_DOUBLE == 1)
216	stfd f0, FP_0(r3)
217	stfd f1, FP_1(r3)
218	stfd f2, FP_2(r3)
219	stfd f3, FP_3(r3)
220	stfd f4, FP_4(r3)
221	stfd f5, FP_5(r3)
222	stfd f6, FP_6(r3)
223	stfd f7, FP_7(r3)
224	stfd f8, FP_8(r3)
225	stfd f9, FP_9(r3)
226	stfd f10, FP_10(r3)
227	stfd f11, FP_11(r3)
228	stfd f12, FP_12(r3)
229	stfd f13, FP_13(r3)
230	stfd f14, FP_14(r3)
231	stfd f15, FP_15(r3)
232	stfd f16, FP_16(r3)
233	stfd f17, FP_17(r3)
234	stfd f18, FP_18(r3)
235	stfd f19, FP_19(r3)
236	stfd f20, FP_20(r3)
237	stfd f21, FP_21(r3)
238	stfd f22, FP_22(r3)
239	stfd f23, FP_23(r3)
240	stfd f24, FP_24(r3)
241	stfd f25, FP_25(r3)
242	stfd f26, FP_26(r3)
243	stfd f27, FP_27(r3)
244	stfd f28, FP_28(r3)
245	stfd f29, FP_29(r3)
246	stfd f30, FP_30(r3)
247	stfd f31, FP_31(r3)
248	mffs f2
249	stfd f2, FP_FPSCR(r3)
250	#else
251	stfs f0, FP_0(r3)
252	stfs f1, FP_1(r3)
253	stfs f2, FP_2(r3)
254	stfs f3, FP_3(r3)
255	stfs f4, FP_4(r3)
256	stfs f5, FP_5(r3)
257	stfs f6, FP_6(r3)
258	stfs f7, FP_7(r3)
259	stfs f8, FP_8(r3)
260	stfs f9, FP_9(r3)
261	stfs f10, FP_10(r3)
262	stfs f11, FP_11(r3)
263	stfs f12, FP_12(r3)
264	stfs f13, FP_13(r3)
265	stfs f14, FP_14(r3)
266	stfs f15, FP_15(r3)
267	stfs f16, FP_16(r3)
268	stfs f17, FP_17(r3)
269	stfs f18, FP_18(r3)
270	stfs f19, FP_19(r3)
271	stfs f20, FP_20(r3)
272	stfs f21, FP_21(r3)
273	stfs f22, FP_22(r3)
274	stfs f23, FP_23(r3)
275	stfs f24, FP_24(r3)
276	stfs f25, FP_25(r3)
277	stfs f26, FP_26(r3)
278	stfs f27, FP_27(r3)
279	stfs f28, FP_28(r3)
280	stfs f29, FP_29(r3)
281	stfs f30, FP_30(r3)
282	stfs f31, FP_31(r3)
283	mffs f2
284	stfs f2, FP_FPSCR(r3)
285	#endif
286	#endif
287	blr
288
289	/*
290	* _CPU_Context_restore_fp_context
291	*
292	* This routine is responsible for restoring the FP context
293	* at *fp_context_ptr. If the point to load the FP context
294	* from is changed then the pointer is modified by this routine.
295	*
296	* Sometimes a macro implementation of this is in cpu.h which dereferences
297	* the ** and a similarly named routine in this file is passed something
298	* like a (Context_Control_fp *). The general rule on making this decision
299	* is to avoid writing assembly language.
300	*/
301
302	ALIGN (PPC_CACHE_ALIGNMENT, PPC_CACHE_ALIGN_POWER)
303	PUBLIC_PROC (_CPU_Context_restore_fp)
304	PROC (_CPU_Context_restore_fp):
305	#if (PPC_HAS_FPU == 1)
306	lwz r3, 0(r3)
307	#if (PPC_HAS_DOUBLE == 1)
308	lfd f2, FP_FPSCR(r3)
309	mtfsf 255, f2
310	lfd f0, FP_0(r3)
311	lfd f1, FP_1(r3)
312	lfd f2, FP_2(r3)
313	lfd f3, FP_3(r3)
314	lfd f4, FP_4(r3)
315	lfd f5, FP_5(r3)
316	lfd f6, FP_6(r3)
317	lfd f7, FP_7(r3)
318	lfd f8, FP_8(r3)
319	lfd f9, FP_9(r3)
320	lfd f10, FP_10(r3)
321	lfd f11, FP_11(r3)
322	lfd f12, FP_12(r3)
323	lfd f13, FP_13(r3)
324	lfd f14, FP_14(r3)
325	lfd f15, FP_15(r3)
326	lfd f16, FP_16(r3)
327	lfd f17, FP_17(r3)
328	lfd f18, FP_18(r3)
329	lfd f19, FP_19(r3)
330	lfd f20, FP_20(r3)
331	lfd f21, FP_21(r3)
332	lfd f22, FP_22(r3)
333	lfd f23, FP_23(r3)
334	lfd f24, FP_24(r3)
335	lfd f25, FP_25(r3)
336	lfd f26, FP_26(r3)
337	lfd f27, FP_27(r3)
338	lfd f28, FP_28(r3)
339	lfd f29, FP_29(r3)
340	lfd f30, FP_30(r3)
341	lfd f31, FP_31(r3)
342	#else
343	lfs f2, FP_FPSCR(r3)
344	mtfsf 255, f2
345	lfs f0, FP_0(r3)
346	lfs f1, FP_1(r3)
347	lfs f2, FP_2(r3)
348	lfs f3, FP_3(r3)
349	lfs f4, FP_4(r3)
350	lfs f5, FP_5(r3)
351	lfs f6, FP_6(r3)
352	lfs f7, FP_7(r3)
353	lfs f8, FP_8(r3)
354	lfs f9, FP_9(r3)
355	lfs f10, FP_10(r3)
356	lfs f11, FP_11(r3)
357	lfs f12, FP_12(r3)
358	lfs f13, FP_13(r3)
359	lfs f14, FP_14(r3)
360	lfs f15, FP_15(r3)
361	lfs f16, FP_16(r3)
362	lfs f17, FP_17(r3)
363	lfs f18, FP_18(r3)
364	lfs f19, FP_19(r3)
365	lfs f20, FP_20(r3)
366	lfs f21, FP_21(r3)
367	lfs f22, FP_22(r3)
368	lfs f23, FP_23(r3)
369	lfs f24, FP_24(r3)
370	lfs f25, FP_25(r3)
371	lfs f26, FP_26(r3)
372	lfs f27, FP_27(r3)
373	lfs f28, FP_28(r3)
374	lfs f29, FP_29(r3)
375	lfs f30, FP_30(r3)
376	lfs f31, FP_31(r3)
377	#endif
378	#endif
379	blr
380
381
382	/* _CPU_Context_switch
383	*
384	* This routine performs a normal non-FP context switch.
385	*/
386	ALIGN (PPC_CACHE_ALIGNMENT, PPC_CACHE_ALIGN_POWER)
387	PUBLIC_PROC (_CPU_Context_switch)
388	PROC (_CPU_Context_switch):
389	sync
390	isync
391	#if (PPC_CACHE_ALIGNMENT == 4) /* No cache */
392	stw r1, GP_1(r3)
393	lwz r1, GP_1(r4)
394	stw r2, GP_2(r3)
395	lwz r2, GP_2(r4)
396	#if (PPC_USE_MULTIPLE == 1)
397	stmw r13, GP_13(r3)
398	lmw r13, GP_13(r4)
399	#else
400	stw r13, GP_13(r3)
401	lwz r13, GP_13(r4)
402	stw r14, GP_14(r3)
403	lwz r14, GP_14(r4)
404	stw r15, GP_15(r3)
405	lwz r15, GP_15(r4)
406	stw r16, GP_16(r3)
407	lwz r16, GP_16(r4)
408	stw r17, GP_17(r3)
409	lwz r17, GP_17(r4)
410	stw r18, GP_18(r3)
411	lwz r18, GP_18(r4)
412	stw r19, GP_19(r3)
413	lwz r19, GP_19(r4)
414	stw r20, GP_20(r3)
415	lwz r20, GP_20(r4)
416	stw r21, GP_21(r3)
417	lwz r21, GP_21(r4)
418	stw r22, GP_22(r3)
419	lwz r22, GP_22(r4)
420	stw r23, GP_23(r3)
421	lwz r23, GP_23(r4)
422	stw r24, GP_24(r3)
423	lwz r24, GP_24(r4)
424	stw r25, GP_25(r3)
425	lwz r25, GP_25(r4)
426	stw r26, GP_26(r3)
427	lwz r26, GP_26(r4)
428	stw r27, GP_27(r3)
429	lwz r27, GP_27(r4)
430	stw r28, GP_28(r3)
431	lwz r28, GP_28(r4)
432	stw r29, GP_29(r3)
433	lwz r29, GP_29(r4)
434	stw r30, GP_30(r3)
435	lwz r30, GP_30(r4)
436	stw r31, GP_31(r3)
437	lwz r31, GP_31(r4)
438	#endif
439	mfcr r5
440	stw r5, GP_CR(r3)
441	lwz r5, GP_CR(r4)
442	mflr r6
443	mtcrf 255, r5
444	stw r6, GP_PC(r3)
445	lwz r6, GP_PC(r4)
446	mfmsr r7
447	mtlr r6
448	stw r7, GP_MSR(r3)
449	lwz r7, GP_MSR(r4)
450	mtmsr r7
451	#endif
452	#if (PPC_CACHE_ALIGNMENT == 16)
453	/* This assumes that all the registers are in the given order */
454	li r5, 16
455	addi r3,r3,-4
456	dcbz r5, r3
457	stw r1, GP_1+4(r3)
458	stw r2, GP_2+4(r3)
459	#if (PPC_USE_MULTIPLE == 1)
460	addi r3, r3, GP_14+4
461	dcbz r5, r3
462	addi r3, r3, GP_18-GP_14
463	dcbz r5, r3
464	addi r3, r3, GP_22-GP_18
465	dcbz r5, r3
466	addi r3, r3, GP_26-GP_22
467	dcbz r5, r3
468	stmw r13, GP_13-GP_26(r3)
469	#else
470	stw r13, GP_13+4(r3)
471	stwu r14, GP_14+4(r3)
472	dcbz r5, r3
473	stw r15, GP_15-GP_14(r3)
474	stw r16, GP_16-GP_14(r3)
475	stw r17, GP_17-GP_14(r3)
476	stwu r18, GP_18-GP_14(r3)
477	dcbz r5, r3
478	stw r19, GP_19-GP_18(r3)
479	stw r20, GP_20-GP_18(r3)
480	stw r21, GP_21-GP_18(r3)
481	stwu r22, GP_22-GP_18(r3)
482	dcbz r5, r3
483	stw r23, GP_23-GP_22(r3)
484	stw r24, GP_24-GP_22(r3)
485	stw r25, GP_25-GP_22(r3)
486	stwu r26, GP_26-GP_22(r3)
487	dcbz r5, r3
488	stw r27, GP_27-GP_26(r3)
489	stw r28, GP_28-GP_26(r3)
490	stw r29, GP_29-GP_26(r3)
491	stw r30, GP_30-GP_26(r3)
492	stw r31, GP_31-GP_26(r3)
493	#endif
494	dcbt r0, r4
495	mfcr r6
496	stw r6, GP_CR-GP_26(r3)
497	mflr r7
498	stw r7, GP_PC-GP_26(r3)
499	mfmsr r8
500	stw r8, GP_MSR-GP_26(r3)
501
502	dcbt r5, r4
503	lwz r1, GP_1(r4)
504	lwz r2, GP_2(r4)
505	#if (PPC_USE_MULTIPLE == 1)
506	addi r4, r4, GP_15
507	dcbt r5, r4
508	addi r4, r4, GP_19-GP_15
509	dcbt r5, r4
510	addi r4, r4, GP_23-GP_19
511	dcbt r5, r4
512	addi r4, r4, GP_27-GP_23
513	dcbt r5, r4
514	lmw r13, GP_13-GP_27(r4)
515	#else
516	lwz r13, GP_13(r4)
517	lwz r14, GP_14(r4)
518	lwzu r15, GP_15(r4)
519	dcbt r5, r4
520	lwz r16, GP_16-GP_15(r4)
521	lwz r17, GP_17-GP_15(r4)
522	lwz r18, GP_18-GP_15(r4)
523	lwzu r19, GP_19-GP_15(r4)
524	dcbt r5, r4
525	lwz r20, GP_20-GP_19(r4)
526	lwz r21, GP_21-GP_19(r4)
527	lwz r22, GP_22-GP_19(r4)
528	lwzu r23, GP_23-GP_19(r4)
529	dcbt r5, r4
530	lwz r24, GP_24-GP_23(r4)
531	lwz r25, GP_25-GP_23(r4)
532	lwz r26, GP_26-GP_23(r4)
533	lwzu r27, GP_27-GP_23(r4)
534	dcbt r5, r4
535	lwz r28, GP_28-GP_27(r4)
536	lwz r29, GP_29-GP_27(r4)
537	lwz r30, GP_30-GP_27(r4)
538	lwz r31, GP_31-GP_27(r4)
539	#endif
540	lwz r6, GP_CR-GP_27(r4)
541	lwz r7, GP_PC-GP_27(r4)
542	lwz r8, GP_MSR-GP_27(r4)
543	mtcrf 255, r6
544	mtlr r7
545	mtmsr r8
546	#endif
547	#if (PPC_CACHE_ALIGNMENT == 32)
548	/* This assumes that all the registers are in the given order */
549	li r5, 32
550	addi r3,r3,-4
551	dcbz r5, r3
552	stw r1, GP_1+4(r3)
553	stw r2, GP_2+4(r3)
554	#if (PPC_USE_MULTIPLE == 1)
555	addi r3, r3, GP_18+4
556	dcbz r5, r3
557	stmw r13, GP_13-GP_18(r3)
558	#else
559	stw r13, GP_13+4(r3)
560	stw r14, GP_14+4(r3)
561	stw r15, GP_15+4(r3)
562	stw r16, GP_16+4(r3)
563	stw r17, GP_17+4(r3)
564	stwu r18, GP_18+4(r3)
565	dcbz r5, r3
566	stw r19, GP_19-GP_18(r3)
567	stw r20, GP_20-GP_18(r3)
568	stw r21, GP_21-GP_18(r3)
569	stw r22, GP_22-GP_18(r3)
570	stw r23, GP_23-GP_18(r3)
571	stw r24, GP_24-GP_18(r3)
572	stw r25, GP_25-GP_18(r3)
573	stw r26, GP_26-GP_18(r3)
574	stw r27, GP_27-GP_18(r3)
575	stw r28, GP_28-GP_18(r3)
576	stw r29, GP_29-GP_18(r3)
577	stw r30, GP_30-GP_18(r3)
578	stw r31, GP_31-GP_18(r3)
579	#endif
580	dcbt r0, r4
581	mfcr r6
582	stw r6, GP_CR-GP_18(r3)
583	mflr r7
584	stw r7, GP_PC-GP_18(r3)
585	mfmsr r8
586	stw r8, GP_MSR-GP_18(r3)
587
588	dcbt r5, r4
589	lwz r1, GP_1(r4)
590	lwz r2, GP_2(r4)
591	#if (PPC_USE_MULTIPLE == 1)
592	addi r4, r4, GP_19
593	dcbt r5, r4
594	lmw r13, GP_13-GP_19(r4)
595	#else
596	lwz r13, GP_13(r4)
597	lwz r14, GP_14(r4)
598	lwz r15, GP_15(r4)
599	lwz r16, GP_16(r4)
600	lwz r17, GP_17(r4)
601	lwz r18, GP_18(r4)
602	lwzu r19, GP_19(r4)
603	dcbt r5, r4
604	lwz r20, GP_20-GP_19(r4)
605	lwz r21, GP_21-GP_19(r4)
606	lwz r22, GP_22-GP_19(r4)
607	lwz r23, GP_23-GP_19(r4)
608	lwz r24, GP_24-GP_19(r4)
609	lwz r25, GP_25-GP_19(r4)
610	lwz r26, GP_26-GP_19(r4)
611	lwz r27, GP_27-GP_19(r4)
612	lwz r28, GP_28-GP_19(r4)
613	lwz r29, GP_29-GP_19(r4)
614	lwz r30, GP_30-GP_19(r4)
615	lwz r31, GP_31-GP_19(r4)
616	#endif
617	lwz r6, GP_CR-GP_19(r4)
618	lwz r7, GP_PC-GP_19(r4)
619	lwz r8, GP_MSR-GP_19(r4)
620	mtcrf 255, r6
621	mtlr r7
622	mtmsr r8
623	#endif
624	blr
625
626	/*
627	* _CPU_Context_restore
628	*
629	* This routine is generally used only to restart self in an
630	* efficient manner. It may simply be a label in _CPU_Context_switch.
631	*
632	* NOTE: May be unnecessary to reload some registers.
633	*/
634	/*
635	* ACB: Don't worry about cache optimisation here - this is not THAT critical.
636	*/
637	ALIGN (PPC_CACHE_ALIGNMENT, PPC_CACHE_ALIGN_POWER)
638	PUBLIC_PROC (_CPU_Context_restore)
639	PROC (_CPU_Context_restore):
640	lwz r5, GP_CR(r3)
641	lwz r6, GP_PC(r3)
642	lwz r7, GP_MSR(r3)
643	mtcrf 255, r5
644	mtlr r6
645	mtmsr r7
646	lwz r1, GP_1(r3)
647	lwz r2, GP_2(r3)
648	#if (PPC_USE_MULTIPLE == 1)
649	lmw r13, GP_13(r3)
650	#else
651	lwz r13, GP_13(r3)
652	lwz r14, GP_14(r3)
653	lwz r15, GP_15(r3)
654	lwz r16, GP_16(r3)
655	lwz r17, GP_17(r3)
656	lwz r18, GP_18(r3)
657	lwz r19, GP_19(r3)
658	lwz r20, GP_20(r3)
659	lwz r21, GP_21(r3)
660	lwz r22, GP_22(r3)
661	lwz r23, GP_23(r3)
662	lwz r24, GP_24(r3)
663	lwz r25, GP_25(r3)
664	lwz r26, GP_26(r3)
665	lwz r27, GP_27(r3)
666	lwz r28, GP_28(r3)
667	lwz r29, GP_29(r3)
668	lwz r30, GP_30(r3)
669	lwz r31, GP_31(r3)
670	#endif
671
672	blr
673
674	/* Individual interrupt prologues look like this:
675	* #if (PPC_ABI == PPC_ABI_POWEROPEN \|\| PPC_ABI == PPC_ABI_GCC27)
676	* #if (PPC_HAS_FPU)
677	* stwu r1, -(204 + 188 + IP_END)(r1)
678	* #else
679	* stwu r1, -(20*4 + IP_END)(r1)
680	* #endif
681	* #else
682	* stwu r1, -(IP_END)(r1)
683	* #endif
684	* stw r0, IP_0(r1)
685	*
686	* li r0, vectornum
687	* b PROC (_ISR_Handler{,C})
688	*/
689
690	/* void __ISR_Handler()
691	*
692	* This routine provides the RTEMS interrupt management.
693	* The vector number is in r0. R0 has already been stacked.
694	*
695	*/
696	ALIGN (PPC_CACHE_ALIGNMENT, PPC_CACHE_ALIGN_POWER)
697	PUBLIC_PROC (_ISR_Handler)
698	PROC (_ISR_Handler):
699	#define LABEL(x) x
700	#define MTSAVE(x) mtspr sprg0, x
701	#define MFSAVE(x) mfspr x, sprg0
702	#define MTPC(x) mtspr srr0, x
703	#define MFPC(x) mfspr x, srr0
704	#define MTMSR(x) mtspr srr1, x
705	#define MFMSR(x) mfspr x, srr1
706	#include "irq_stub.s"
707	rfi
708
709	#if (PPC_HAS_RFCI == 1)
710	/* void __ISR_HandlerC()
711	*
712	* This routine provides the RTEMS interrupt management.
713	* For critical interrupts
714	*
715	*/
716	ALIGN (PPC_CACHE_ALIGNMENT, PPC_CACHE_ALIGN_POWER)
717	PUBLIC_PROC (_ISR_HandlerC)
718	PROC (_ISR_HandlerC):
719	#undef LABEL
720	#undef MTSAVE
721	#undef MFSAVE
722	#undef MTPC
723	#undef MFPC
724	#undef MTMSR
725	#undef MFMSR
726	#define LABEL(x) x##_C
727	#define MTSAVE(x) mtspr sprg1, x
728	#define MFSAVE(x) mfspr x, sprg1
729	#define MTPC(x) mtspr srr2, x
730	#define MFPC(x) mfspr x, srr2
731	#define MTMSR(x) mtspr srr3, x
732	#define MFMSR(x) mfspr x, srr3
733	#include "irq_stub.s"
734	rfci
735	#endif
736
737	/* PowerOpen descriptors for indirect function calls.
738	*/
739
740	#if (PPC_ABI == PPC_ABI_POWEROPEN)
741	DESCRIPTOR (_CPU_Context_save_fp)
742	DESCRIPTOR (_CPU_Context_restore_fp)
743	DESCRIPTOR (_CPU_Context_switch)
744	DESCRIPTOR (_CPU_Context_restore)
745	DESCRIPTOR (_ISR_Handler)
746	#if (PPC_HAS_RFCI == 1)
747	DESCRIPTOR (_ISR_HandlerC)
748	#endif
749	#endif

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