source: rtems/c/src/exec/score/cpu/powerpc/cpu.h @ 9700578

4.104.114.84.95
Last change on this file since 9700578 was 9700578, checked in by Joel Sherrill <joel.sherrill@…>, on Oct 30, 1995 at 9:54:45 PM

SPARC port passes all tests

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File size: 33.7 KB
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1/*  cpu.h
2 *
3 *  This include file contains information pertaining to the PowerPC
4 *  processor.
5 *
6 *  Author:     Andrew Bray <andy@i-cubed.demon.co.uk>
7 *
8 *  COPYRIGHT (c) 1995 by i-cubed ltd.
9 *
10 *  To anyone who acknowledges that this file is provided "AS IS"
11 *  without any express or implied warranty:
12 *      permission to use, copy, modify, and distribute this file
13 *      for any purpose is hereby granted without fee, provided that
14 *      the above copyright notice and this notice appears in all
15 *      copies, and that the name of i-cubed limited not be used in
16 *      advertising or publicity pertaining to distribution of the
17 *      software without specific, written prior permission.
18 *      i-cubed limited makes no representations about the suitability
19 *      of this software for any purpose.
20 *
21 *  Derived from c/src/exec/cpu/no_cpu/cpu.h:
22 *
23 *  COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994.
24 *  On-Line Applications Research Corporation (OAR).
25 *  All rights assigned to U.S. Government, 1994.
26 *
27 *  This material may be reproduced by or for the U.S. Government pursuant
28 *  to the copyright license under the clause at DFARS 252.227-7013.  This
29 *  notice must appear in all copies of this file and its derivatives.
30 *
31 *  $Id$
32 */
33
34#ifndef __CPU_h
35#define __CPU_h
36
37#ifdef __cplusplus
38extern "C" {
39#endif
40
41#include <rtems/score/ppc.h>               /* pick up machine definitions */
42#ifndef ASM
43struct CPU_Interrupt_frame;
44
45#include <rtems/score/ppctypes.h>
46#endif
47
48/* conditional compilation parameters */
49
50/*
51 *  Should the calls to _Thread_Enable_dispatch be inlined?
52 *
53 *  If TRUE, then they are inlined.
54 *  If FALSE, then a subroutine call is made.
55 *
56 *  Basically this is an example of the classic trade-off of size
57 *  versus speed.  Inlining the call (TRUE) typically increases the
58 *  size of RTEMS while speeding up the enabling of dispatching.
59 *  [NOTE: In general, the _Thread_Dispatch_disable_level will
60 *  only be 0 or 1 unless you are in an interrupt handler and that
61 *  interrupt handler invokes the executive.]  When not inlined
62 *  something calls _Thread_Enable_dispatch which in turns calls
63 *  _Thread_Dispatch.  If the enable dispatch is inlined, then
64 *  one subroutine call is avoided entirely.]
65 */
66
67#define CPU_INLINE_ENABLE_DISPATCH       FALSE
68
69/*
70 *  Should the body of the search loops in _Thread_queue_Enqueue_priority
71 *  be unrolled one time?  In unrolled each iteration of the loop examines
72 *  two "nodes" on the chain being searched.  Otherwise, only one node
73 *  is examined per iteration.
74 *
75 *  If TRUE, then the loops are unrolled.
76 *  If FALSE, then the loops are not unrolled.
77 *
78 *  The primary factor in making this decision is the cost of disabling
79 *  and enabling interrupts (_ISR_Flash) versus the cost of rest of the
80 *  body of the loop.  On some CPUs, the flash is more expensive than
81 *  one iteration of the loop body.  In this case, it might be desirable
82 *  to unroll the loop.  It is important to note that on some CPUs, this
83 *  code is the longest interrupt disable period in RTEMS.  So it is
84 *  necessary to strike a balance when setting this parameter.
85 */
86
87#define CPU_UNROLL_ENQUEUE_PRIORITY      FALSE
88
89/*
90 *  Does RTEMS manage a dedicated interrupt stack in software?
91 *
92 *  If TRUE, then a stack is allocated in _Interrupt_Manager_initialization.
93 *  If FALSE, nothing is done.
94 *
95 *  If the CPU supports a dedicated interrupt stack in hardware,
96 *  then it is generally the responsibility of the BSP to allocate it
97 *  and set it up.
98 *
99 *  If the CPU does not support a dedicated interrupt stack, then
100 *  the porter has two options: (1) execute interrupts on the
101 *  stack of the interrupted task, and (2) have RTEMS manage a dedicated
102 *  interrupt stack.
103 *
104 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
105 *
106 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
107 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
108 *  possible that both are FALSE for a particular CPU.  Although it
109 *  is unclear what that would imply about the interrupt processing
110 *  procedure on that CPU.
111 */
112
113#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE
114
115/*
116 *  Does this CPU have hardware support for a dedicated interrupt stack?
117 *
118 *  If TRUE, then it must be installed during initialization.
119 *  If FALSE, then no installation is performed.
120 *
121 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
122 *
123 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
124 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
125 *  possible that both are FALSE for a particular CPU.  Although it
126 *  is unclear what that would imply about the interrupt processing
127 *  procedure on that CPU.
128 */
129
130/*
131 *  ACB: This is a lie, but it gets us a handle on a call to set up
132 *  a variable derived from the top of the interrupt stack.
133 */
134
135#define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE
136
137/*
138 *  Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
139 *
140 *  If TRUE, then the memory is allocated during initialization.
141 *  If FALSE, then the memory is allocated during initialization.
142 *
143 *  This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE
144 *  or CPU_INSTALL_HARDWARE_INTERRUPT_STACK is TRUE.
145 */
146
147#define CPU_ALLOCATE_INTERRUPT_STACK TRUE
148
149/*
150 *  Does the CPU have hardware floating point?
151 *
152 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
153 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
154 *
155 *  If there is a FP coprocessor such as the i387 or mc68881, then
156 *  the answer is TRUE.
157 *
158 *  The macro name "PPC_HAS_FPU" should be made CPU specific.
159 *  It indicates whether or not this CPU model has FP support.  For
160 *  example, it would be possible to have an i386_nofp CPU model
161 *  which set this to false to indicate that you have an i386 without
162 *  an i387 and wish to leave floating point support out of RTEMS.
163 */
164
165#if ( PPC_HAS_FPU == 1 )
166#define CPU_HARDWARE_FP     TRUE
167#else
168#define CPU_HARDWARE_FP     FALSE
169#endif
170
171/*
172 *  Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
173 *
174 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
175 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
176 *
177 *  So far, the only CPU in which this option has been used is the
178 *  HP PA-RISC.  The HP C compiler and gcc both implicitly use the
179 *  floating point registers to perform integer multiplies.  If
180 *  a function which you would not think utilize the FP unit DOES,
181 *  then one can not easily predict which tasks will use the FP hardware.
182 *  In this case, this option should be TRUE.
183 *
184 *  If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
185 */
186
187#define CPU_ALL_TASKS_ARE_FP     FALSE
188
189/*
190 *  Should the IDLE task have a floating point context?
191 *
192 *  If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
193 *  and it has a floating point context which is switched in and out.
194 *  If FALSE, then the IDLE task does not have a floating point context.
195 *
196 *  Setting this to TRUE negatively impacts the time required to preempt
197 *  the IDLE task from an interrupt because the floating point context
198 *  must be saved as part of the preemption.
199 */
200
201#define CPU_IDLE_TASK_IS_FP      FALSE
202
203/*
204 *  Should the saving of the floating point registers be deferred
205 *  until a context switch is made to another different floating point
206 *  task?
207 *
208 *  If TRUE, then the floating point context will not be stored until
209 *  necessary.  It will remain in the floating point registers and not
210 *  disturned until another floating point task is switched to.
211 *
212 *  If FALSE, then the floating point context is saved when a floating
213 *  point task is switched out and restored when the next floating point
214 *  task is restored.  The state of the floating point registers between
215 *  those two operations is not specified.
216 *
217 *  If the floating point context does NOT have to be saved as part of
218 *  interrupt dispatching, then it should be safe to set this to TRUE.
219 *
220 *  Setting this flag to TRUE results in using a different algorithm
221 *  for deciding when to save and restore the floating point context.
222 *  The deferred FP switch algorithm minimizes the number of times
223 *  the FP context is saved and restored.  The FP context is not saved
224 *  until a context switch is made to another, different FP task.
225 *  Thus in a system with only one FP task, the FP context will never
226 *  be saved or restored.
227 */
228/*
229 *  ACB Note:  This could make debugging tricky..
230 */
231
232#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
233
234/*
235 *  Does this port provide a CPU dependent IDLE task implementation?
236 *
237 *  If TRUE, then the routine _CPU_Internal_threads_Idle_thread_body
238 *  must be provided and is the default IDLE thread body instead of
239 *  _Internal_threads_Idle_thread_body.
240 *
241 *  If FALSE, then use the generic IDLE thread body if the BSP does
242 *  not provide one.
243 *
244 *  This is intended to allow for supporting processors which have
245 *  a low power or idle mode.  When the IDLE thread is executed, then
246 *  the CPU can be powered down.
247 *
248 *  The order of precedence for selecting the IDLE thread body is:
249 *
250 *    1.  BSP provided
251 *    2.  CPU dependent (if provided)
252 *    3.  generic (if no BSP and no CPU dependent)
253 */
254
255#define CPU_PROVIDES_IDLE_THREAD_BODY    FALSE
256
257/*
258 *  Does the stack grow up (toward higher addresses) or down
259 *  (toward lower addresses)?
260 *
261 *  If TRUE, then the grows upward.
262 *  If FALSE, then the grows toward smaller addresses.
263 */
264
265#define CPU_STACK_GROWS_UP               FALSE
266
267/*
268 *  The following is the variable attribute used to force alignment
269 *  of critical RTEMS structures.  On some processors it may make
270 *  sense to have these aligned on tighter boundaries than
271 *  the minimum requirements of the compiler in order to have as
272 *  much of the critical data area as possible in a cache line.
273 *
274 *  The placement of this macro in the declaration of the variables
275 *  is based on the syntactically requirements of the GNU C
276 *  "__attribute__" extension.  For example with GNU C, use
277 *  the following to force a structures to a 32 byte boundary.
278 *
279 *      __attribute__ ((aligned (32)))
280 *
281 *  NOTE:  Currently only the Priority Bit Map table uses this feature.
282 *         To benefit from using this, the data must be heavily
283 *         used so it will stay in the cache and used frequently enough
284 *         in the executive to justify turning this on.
285 */
286
287#define CPU_STRUCTURE_ALIGNMENT    __attribute__ ((aligned (PPC_CACHE_ALIGNMENT)))
288
289/*
290 *  The following defines the number of bits actually used in the
291 *  interrupt field of the task mode.  How those bits map to the
292 *  CPU interrupt levels is defined by the routine _CPU_ISR_Set_level().
293 */
294/*
295 *  ACB Note: Levels are:
296 *   0: All maskable interrupts enabled
297 *   1: Other critical exceptions enabled
298 *   2: Machine check enabled
299 *   3: All maskable IRQs disabled
300 */
301
302#define CPU_MODES_INTERRUPT_MASK   0x00000003
303
304/*
305 *  Processor defined structures
306 *
307 *  Examples structures include the descriptor tables from the i386
308 *  and the processor control structure on the i960ca.
309 */
310
311/* may need to put some structures here.  */
312
313/*
314 * Contexts
315 *
316 *  Generally there are 2 types of context to save.
317 *     1. Interrupt registers to save
318 *     2. Task level registers to save
319 *
320 *  This means we have the following 3 context items:
321 *     1. task level context stuff::  Context_Control
322 *     2. floating point task stuff:: Context_Control_fp
323 *     3. special interrupt level context :: Context_Control_interrupt
324 *
325 *  On some processors, it is cost-effective to save only the callee
326 *  preserved registers during a task context switch.  This means
327 *  that the ISR code needs to save those registers which do not
328 *  persist across function calls.  It is not mandatory to make this
329 *  distinctions between the caller/callee saves registers for the
330 *  purpose of minimizing context saved during task switch and on interrupts.
331 *  If the cost of saving extra registers is minimal, simplicity is the
332 *  choice.  Save the same context on interrupt entry as for tasks in
333 *  this case.
334 *
335 *  Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
336 *  care should be used in designing the context area.
337 *
338 *  On some CPUs with hardware floating point support, the Context_Control_fp
339 *  structure will not be used or it simply consist of an array of a
340 *  fixed number of bytes.   This is done when the floating point context
341 *  is dumped by a "FP save context" type instruction and the format
342 *  is not really defined by the CPU.  In this case, there is no need
343 *  to figure out the exact format -- only the size.  Of course, although
344 *  this is enough information for RTEMS, it is probably not enough for
345 *  a debugger such as gdb.  But that is another problem.
346 */
347
348typedef struct {
349    unsigned32 gpr1;    /* Stack pointer for all */
350    unsigned32 gpr2;    /* TOC in PowerOpen, reserved SVR4, section ptr EABI + */
351    unsigned32 gpr13;   /* First non volatile PowerOpen, section ptr SVR4/EABI */
352    unsigned32 gpr14;   /* Non volatile for all */
353    unsigned32 gpr15;   /* Non volatile for all */
354    unsigned32 gpr16;   /* Non volatile for all */
355    unsigned32 gpr17;   /* Non volatile for all */
356    unsigned32 gpr18;   /* Non volatile for all */
357    unsigned32 gpr19;   /* Non volatile for all */
358    unsigned32 gpr20;   /* Non volatile for all */
359    unsigned32 gpr21;   /* Non volatile for all */
360    unsigned32 gpr22;   /* Non volatile for all */
361    unsigned32 gpr23;   /* Non volatile for all */
362    unsigned32 gpr24;   /* Non volatile for all */
363    unsigned32 gpr25;   /* Non volatile for all */
364    unsigned32 gpr26;   /* Non volatile for all */
365    unsigned32 gpr27;   /* Non volatile for all */
366    unsigned32 gpr28;   /* Non volatile for all */
367    unsigned32 gpr29;   /* Non volatile for all */
368    unsigned32 gpr30;   /* Non volatile for all */
369    unsigned32 gpr31;   /* Non volatile for all */
370    unsigned32 cr;      /* PART of the CR is non volatile for all */
371    unsigned32 pc;      /* Program counter/Link register */
372    unsigned32 msr;     /* Initial interrupt level */
373} Context_Control;
374
375typedef struct {
376    /* The ABIs (PowerOpen/SVR4/EABI) only require saving f14-f31 over
377     * procedure calls.  However, this would mean that the interrupt
378     * frame had to hold f0-f13, and the fpscr.  And as the majority
379     * of tasks will not have an FP context, we will save the whole
380     * context here.
381     */
382#if (PPC_HAS_DOUBLE == 1)
383    double      f[32];
384    double      fpscr;
385#else
386    float       f[32];
387    float       fpscr;
388#endif
389} Context_Control_fp;
390
391typedef struct CPU_Interrupt_frame {
392    unsigned32 stacklink;       /* Ensure this is a real frame (also reg1 save) */
393#if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27)
394    unsigned32 dummy[13];       /* Used by callees: PowerOpen ABI */
395#else
396    unsigned32 dummy[1];        /* Used by callees: SVR4/EABI */
397#endif
398    /* This is what is left out of the primary contexts */
399    unsigned32 gpr0;
400    unsigned32 gpr2;            /* play safe */
401    unsigned32 gpr3;
402    unsigned32 gpr4;
403    unsigned32 gpr5;
404    unsigned32 gpr6;
405    unsigned32 gpr7;
406    unsigned32 gpr8;
407    unsigned32 gpr9;
408    unsigned32 gpr10;
409    unsigned32 gpr11;
410    unsigned32 gpr12;
411    unsigned32 gpr13;   /* Play safe */
412    unsigned32 gpr28;   /* For internal use by the IRQ handler */
413    unsigned32 gpr29;   /* For internal use by the IRQ handler */
414    unsigned32 gpr30;   /* For internal use by the IRQ handler */
415    unsigned32 gpr31;   /* For internal use by the IRQ handler */
416    unsigned32 cr;      /* Bits of this are volatile, so no-one may save */
417    unsigned32 ctr;
418    unsigned32 xer;
419    unsigned32 lr;
420    unsigned32 pc;
421    unsigned32 msr;
422    unsigned32 pad[3];
423} CPU_Interrupt_frame;
424
425
426/*
427 *  The following table contains the information required to configure
428 *  the PowerPC processor specific parameters.
429 *
430 *  NOTE: The interrupt_stack_size field is required if
431 *        CPU_ALLOCATE_INTERRUPT_STACK is defined as TRUE.
432 *
433 *        The pretasking_hook, predriver_hook, and postdriver_hook,
434 *        and the do_zero_of_workspace fields are required on ALL CPUs.
435 */
436
437typedef struct {
438  void       (*pretasking_hook)( void );
439  void       (*predriver_hook)( void );
440  void       (*postdriver_hook)( void );
441  void       (*idle_task)( void );
442  boolean      do_zero_of_workspace;
443  unsigned32   interrupt_stack_size;
444  unsigned32   extra_system_initialization_stack;
445  unsigned32   clicks_per_usec; /* Timer clicks per microsecond */
446  unsigned32   serial_per_sec;  /* Serial clocks per second */
447  boolean      serial_external_clock;
448  boolean      serial_xon_xoff;
449  boolean      serial_cts_rts;
450  unsigned32   serial_rate;
451  unsigned32   timer_average_overhead; /* Average overhead of timer in ticks */
452  unsigned32   timer_least_valid; /* Least valid number from timer */
453  void (*spurious_handler)(unsigned32 vector, CPU_Interrupt_frame *);
454}   rtems_cpu_table;
455
456/*
457 *  This variable is optional.  It is used on CPUs on which it is difficult
458 *  to generate an "uninitialized" FP context.  It is filled in by
459 *  _CPU_Initialize and copied into the task's FP context area during
460 *  _CPU_Context_Initialize.
461 */
462
463/* EXTERN Context_Control_fp  _CPU_Null_fp_context; */
464
465/*
466 *  On some CPUs, RTEMS supports a software managed interrupt stack.
467 *  This stack is allocated by the Interrupt Manager and the switch
468 *  is performed in _ISR_Handler.  These variables contain pointers
469 *  to the lowest and highest addresses in the chunk of memory allocated
470 *  for the interrupt stack.  Since it is unknown whether the stack
471 *  grows up or down (in general), this give the CPU dependent
472 *  code the option of picking the version it wants to use.
473 *
474 *  NOTE: These two variables are required if the macro
475 *        CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
476 */
477
478EXTERN void               *_CPU_Interrupt_stack_low;
479EXTERN void               *_CPU_Interrupt_stack_high;
480
481/*
482 *  With some compilation systems, it is difficult if not impossible to
483 *  call a high-level language routine from assembly language.  This
484 *  is especially true of commercial Ada compilers and name mangling
485 *  C++ ones.  This variable can be optionally defined by the CPU porter
486 *  and contains the address of the routine _Thread_Dispatch.  This
487 *  can make it easier to invoke that routine at the end of the interrupt
488 *  sequence (if a dispatch is necessary).
489 */
490
491/* EXTERN void           (*_CPU_Thread_dispatch_pointer)(); */
492
493/*
494 *  Nothing prevents the porter from declaring more CPU specific variables.
495 */
496
497EXTERN struct {
498#if (PPC_ABI == PPC_ABI_POWEROPEN)
499  unsigned32 Dispatch_r2;
500#else
501  unsigned32 Default_r2;
502#if (PPC_ABI != PPC_ABI_GCC27)
503  unsigned32 Default_r13;
504#endif
505#endif
506  unsigned32 *Nest_level;
507  unsigned32 *Disable_level;
508  void *Vector_table;
509  void *Stack;
510  boolean *Switch_necessary;
511  boolean *Signal;
512} _CPU_IRQ_info CPU_STRUCTURE_ALIGNMENT;
513
514/*
515 *  The size of the floating point context area.  On some CPUs this
516 *  will not be a "sizeof" because the format of the floating point
517 *  area is not defined -- only the size is.  This is usually on
518 *  CPUs with a "floating point save context" instruction.
519 */
520
521#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
522
523/*
524 * (Optional) # of bytes for libmisc/stackchk to check
525 * If not specifed, then it defaults to something reasonable
526 * for most architectures.
527 */
528
529#define CPU_STACK_CHECK_SIZE    (128)
530
531/*
532 *  Amount of extra stack (above minimum stack size) required by
533 *  system initialization thread.  Remember that in a multiprocessor
534 *  system the system intialization thread becomes the MP server thread.
535 */
536
537#define CPU_SYSTEM_INITIALIZATION_THREAD_EXTRA_STACK 0
538
539/*
540 *  This defines the number of entries in the ISR_Vector_table managed
541 *  by RTEMS.
542 */
543
544#define CPU_INTERRUPT_NUMBER_OF_VECTORS      (PPC_INTERRUPT_MAX)
545#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
546
547/*
548 *  Should be large enough to run all RTEMS tests.  This insures
549 *  that a "reasonable" small application should not have any problems.
550 */
551
552#define CPU_STACK_MINIMUM_SIZE          (1024*3)
553
554/*
555 *  CPU's worst alignment requirement for data types on a byte boundary.  This
556 *  alignment does not take into account the requirements for the stack.
557 */
558
559#define CPU_ALIGNMENT              (PPC_ALIGNMENT)
560
561/*
562 *  This number corresponds to the byte alignment requirement for the
563 *  heap handler.  This alignment requirement may be stricter than that
564 *  for the data types alignment specified by CPU_ALIGNMENT.  It is
565 *  common for the heap to follow the same alignment requirement as
566 *  CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict enough for the heap,
567 *  then this should be set to CPU_ALIGNMENT.
568 *
569 *  NOTE:  This does not have to be a power of 2.  It does have to
570 *         be greater or equal to than CPU_ALIGNMENT.
571 */
572
573#define CPU_HEAP_ALIGNMENT         (PPC_CACHE_ALIGNMENT)
574
575/*
576 *  This number corresponds to the byte alignment requirement for memory
577 *  buffers allocated by the partition manager.  This alignment requirement
578 *  may be stricter than that for the data types alignment specified by
579 *  CPU_ALIGNMENT.  It is common for the partition to follow the same
580 *  alignment requirement as CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict
581 *  enough for the partition, then this should be set to CPU_ALIGNMENT.
582 *
583 *  NOTE:  This does not have to be a power of 2.  It does have to
584 *         be greater or equal to than CPU_ALIGNMENT.
585 */
586
587#define CPU_PARTITION_ALIGNMENT    (PPC_CACHE_ALIGNMENT)
588
589/*
590 *  This number corresponds to the byte alignment requirement for the
591 *  stack.  This alignment requirement may be stricter than that for the
592 *  data types alignment specified by CPU_ALIGNMENT.  If the CPU_ALIGNMENT
593 *  is strict enough for the stack, then this should be set to 0.
594 *
595 *  NOTE:  This must be a power of 2 either 0 or greater than CPU_ALIGNMENT.
596 */
597
598#define CPU_STACK_ALIGNMENT        (PPC_STACK_ALIGNMENT)
599
600/* ISR handler macros */
601
602/*
603 *  Disable all interrupts for an RTEMS critical section.  The previous
604 *  level is returned in _level.
605 */
606
607#define _CPU_ISR_Disable( _isr_cookie ) \
608  { \
609    asm volatile ( \
610        "mfmsr %0; andc %1,%0,%1; mtmsr %1" : \
611        "=r" ((_isr_cookie)) : "r" ((PPC_MSR_DISABLE_MASK)) \
612        ); \
613  }
614
615/*
616 *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
617 *  This indicates the end of an RTEMS critical section.  The parameter
618 *  _level is not modified.
619 */
620
621#define _CPU_ISR_Enable( _isr_cookie )  \
622  { \
623     asm volatile ( "mtmsr %0" : \
624                   "=r" ((_isr_cookie)) : "0" ((_isr_cookie))); \
625  }
626
627/*
628 *  This temporarily restores the interrupt to _level before immediately
629 *  disabling them again.  This is used to divide long RTEMS critical
630 *  sections into two or more parts.  The parameter _level is not
631 * modified.
632 */
633
634#define _CPU_ISR_Flash( _isr_cookie ) \
635  { \
636    asm volatile ( \
637        "mtmsr %0; andc %1,%0,%1; mtmsr %1" : \
638        "=r" ((_isr_cookie)) : \
639        "r" ((PPC_MSR_DISABLE_MASK)), "0" ((_isr_cookie)) \
640        ); \
641  }
642
643/*
644 *  Map interrupt level in task mode onto the hardware that the CPU
645 *  actually provides.  Currently, interrupt levels which do not
646 *  map onto the CPU in a generic fashion are undefined.  Someday,
647 *  it would be nice if these were "mapped" by the application
648 *  via a callout.  For example, m68k has 8 levels 0 - 7, levels
649 *  8 - 255 would be available for bsp/application specific meaning.
650 *  This could be used to manage a programmable interrupt controller
651 *  via the rtems_task_mode directive.
652 */
653
654#define _CPU_ISR_Set_level( new_level ) \
655  { \
656    register unsigned32 tmp; \
657    asm volatile ( \
658        "mfmsr %0; andc %0,%0,%1; and %2, %2, %1; or %0, %0, %2; mtmsr %0" : \
659        "=r" ((tmp)) : \
660        "r" ((PPC_MSR_DISABLE_MASK)), "r" ((_CPU_msrs[new_level])), "0" ((tmp)) \
661        ); \
662  }
663
664/* end of ISR handler macros */
665
666/* Context handler macros */
667
668/*
669 *  Initialize the context to a state suitable for starting a
670 *  task after a context restore operation.  Generally, this
671 *  involves:
672 *
673 *     - setting a starting address
674 *     - preparing the stack
675 *     - preparing the stack and frame pointers
676 *     - setting the proper interrupt level in the context
677 *     - initializing the floating point context
678 *
679 *  This routine generally does not set any unnecessary register
680 *  in the context.  The state of the "general data" registers is
681 *  undefined at task start time.
682 */
683
684#if PPC_ABI == PPC_ABI_POWEROPEN
685#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
686                                 _isr, _entry_point, _is_fp ) \
687  { \
688    unsigned32 sp, *desc; \
689    \
690    sp = ((unsigned32)_stack_base) + (_size) - 56; \
691    *((unsigned32 *)sp) = 0; \
692    \
693    desc = (unsigned32 *)_entry_point; \
694    \
695    (_the_context)->msr = PPC_MSR_INITIAL | \
696      _CPU_msrs[ _isr ]; \
697    (_the_context)->pc = desc[0]; \
698    (_the_context)->gpr1 = sp; \
699    (_the_context)->gpr2 = desc[1]; \
700  }
701#endif
702#if PPC_ABI == PPC_ABI_SVR4
703#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
704                                 _isr, _entry_point ) \
705  { \
706    unsigned32 sp, r13; \
707    \
708    sp = ((unsigned32)_stack_base) + (_size) - 8; \
709    *((unsigned32 *)sp) = 0; \
710    \
711    asm volatile ("mr %0, 13" : "=r" ((r13))); \
712    \
713    (_the_context->msr) = PPC_MSR_INITIAL | \
714      _CPU_msrs[ _isr ]; \
715    (_the_context->pc) = _entry_point; \
716    (_the_context->gpr1) = sp; \
717    (_the_context->gpr13) = r13; \
718  }
719#endif
720#if PPC_ABI == PPC_ABI_EABI
721#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
722                                 _isr, _entry_point ) \
723  { \
724    unsigned32 sp, r2, r13; \
725    \
726    sp = ((unsigned32)_stack_base) + (_size) - 8; \
727    *((unsigned32 *)sp) = 0; \
728    \
729    asm volatile ("mr %0,2; mr %1,13" : "=r" ((r2)), "=r" ((r13))); \
730    \
731    (_the_context)->msr = PPC_MSR_INITIAL | \
732      _CPU_msrs[ _isr ]; \
733    (_the_context->pc) = _entry_point; \
734    (_the_context->gpr1) = sp; \
735    (_the_context->gpr2) = r2; \
736    (_the_context->gpr13) = r13; \
737  }
738#endif
739
740/*
741 *  This routine is responsible for somehow restarting the currently
742 *  executing task.  If you are lucky, then all that is necessary
743 *  is restoring the context.  Otherwise, there will need to be
744 *  a special assembly routine which does something special in this
745 *  case.  Context_Restore should work most of the time.  It will
746 *  not work if restarting self conflicts with the stack frame
747 *  assumptions of restoring a context.
748 */
749
750#define _CPU_Context_Restart_self( _the_context ) \
751   _CPU_Context_restore( (_the_context) );
752
753/*
754 *  The purpose of this macro is to allow the initial pointer into
755 *  a floating point context area (used to save the floating point
756 *  context) to be at an arbitrary place in the floating point
757 *  context area.
758 *
759 *  This is necessary because some FP units are designed to have
760 *  their context saved as a stack which grows into lower addresses.
761 *  Other FP units can be saved by simply moving registers into offsets
762 *  from the base of the context area.  Finally some FP units provide
763 *  a "dump context" instruction which could fill in from high to low
764 *  or low to high based on the whim of the CPU designers.
765 */
766
767#define _CPU_Context_Fp_start( _base, _offset ) \
768   ( (void *) (_base) + (_offset) )
769
770/*
771 *  This routine initializes the FP context area passed to it to.
772 *  There are a few standard ways in which to initialize the
773 *  floating point context.  The code included for this macro assumes
774 *  that this is a CPU in which a "initial" FP context was saved into
775 *  _CPU_Null_fp_context and it simply copies it to the destination
776 *  context passed to it.
777 *
778 *  Other models include (1) not doing anything, and (2) putting
779 *  a "null FP status word" in the correct place in the FP context.
780 */
781
782#define _CPU_Context_Initialize_fp( _destination ) \
783  { \
784   ((Context_Control_fp *) *((void **) _destination))->fpscr = PPC_INIT_FPSCR; \
785  }
786
787/* end of Context handler macros */
788
789/* Fatal Error manager macros */
790
791/*
792 *  This routine copies _error into a known place -- typically a stack
793 *  location or a register, optionally disables interrupts, and
794 *  halts/stops the CPU.
795 */
796
797#define _CPU_Fatal_halt( _error ) \
798  _CPU_Fatal_error(_error)
799
800/* end of Fatal Error manager macros */
801
802/* Bitfield handler macros */
803
804/*
805 *  This routine sets _output to the bit number of the first bit
806 *  set in _value.  _value is of CPU dependent type Priority_Bit_map_control.
807 *  This type may be either 16 or 32 bits wide although only the 16
808 *  least significant bits will be used.
809 *
810 *  There are a number of variables in using a "find first bit" type
811 *  instruction.
812 *
813 *    (1) What happens when run on a value of zero?
814 *    (2) Bits may be numbered from MSB to LSB or vice-versa.
815 *    (3) The numbering may be zero or one based.
816 *    (4) The "find first bit" instruction may search from MSB or LSB.
817 *
818 *  RTEMS guarantees that (1) will never happen so it is not a concern.
819 *  (2),(3), (4) are handled by the macros _CPU_Priority_mask() and
820 *  _CPU_Priority_bits_index().  These three form a set of routines
821 *  which must logically operate together.  Bits in the _value are
822 *  set and cleared based on masks built by _CPU_Priority_mask().
823 *  The basic major and minor values calculated by _Priority_Major()
824 *  and _Priority_Minor() are "massaged" by _CPU_Priority_bits_index()
825 *  to properly range between the values returned by the "find first bit"
826 *  instruction.  This makes it possible for _Priority_Get_highest() to
827 *  calculate the major and directly index into the minor table.
828 *  This mapping is necessary to ensure that 0 (a high priority major/minor)
829 *  is the first bit found.
830 *
831 *  This entire "find first bit" and mapping process depends heavily
832 *  on the manner in which a priority is broken into a major and minor
833 *  components with the major being the 4 MSB of a priority and minor
834 *  the 4 LSB.  Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
835 *  priority.  And (15 << 4) + 14 corresponds to priority 254 -- the next
836 *  to the lowest priority.
837 *
838 *  If your CPU does not have a "find first bit" instruction, then
839 *  there are ways to make do without it.  Here are a handful of ways
840 *  to implement this in software:
841 *
842 *    - a series of 16 bit test instructions
843 *    - a "binary search using if's"
844 *    - _number = 0
845 *      if _value > 0x00ff
846 *        _value >>=8
847 *        _number = 8;
848 *
849 *      if _value > 0x0000f
850 *        _value >=8
851 *        _number += 4
852 *
853 *      _number += bit_set_table[ _value ]
854 *
855 *    where bit_set_table[ 16 ] has values which indicate the first
856 *      bit set
857 */
858
859#define CPU_USE_GENERIC_BITFIELD_CODE FALSE
860#define CPU_USE_GENERIC_BITFIELD_DATA FALSE
861
862#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
863  { \
864    asm volatile ("cntlzw %0, %1" : "=r" ((_output)), "=r" ((_value)) : \
865                  "1" ((_value))); \
866  }
867
868/* end of Bitfield handler macros */
869
870/*
871 *  This routine builds the mask which corresponds to the bit fields
872 *  as searched by _CPU_Bitfield_Find_first_bit().  See the discussion
873 *  for that routine.
874 */
875
876#define _CPU_Priority_Mask( _bit_number ) \
877  ( 0x80000000 >> (_bit_number) )
878
879/*
880 *  This routine translates the bit numbers returned by
881 *  _CPU_Bitfield_Find_first_bit() into something suitable for use as
882 *  a major or minor component of a priority.  See the discussion
883 *  for that routine.
884 */
885
886#define _CPU_Priority_bits_index( _priority ) \
887  (_priority)
888
889/* end of Priority handler macros */
890
891/* variables */
892
893extern const unsigned32 _CPU_msrs[4];
894
895/* functions */
896
897/*
898 *  _CPU_Initialize
899 *
900 *  This routine performs CPU dependent initialization.
901 */
902
903void _CPU_Initialize(
904  rtems_cpu_table  *cpu_table,
905  void      (*thread_dispatch)
906);
907
908/*
909 *  _CPU_ISR_install_vector
910 *
911 *  This routine installs an interrupt vector.
912 */
913
914void _CPU_ISR_install_vector(
915  unsigned32  vector,
916  proc_ptr    new_handler,
917  proc_ptr   *old_handler
918);
919
920/*
921 *  _CPU_Install_interrupt_stack
922 *
923 *  This routine installs the hardware interrupt stack pointer.
924 *
925 *  NOTE:  It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK
926 *         is TRUE.
927 */
928
929void _CPU_Install_interrupt_stack( void );
930
931/*
932 *  _CPU_Context_switch
933 *
934 *  This routine switches from the run context to the heir context.
935 */
936
937void _CPU_Context_switch(
938  Context_Control  *run,
939  Context_Control  *heir
940);
941
942/*
943 *  _CPU_Context_restore
944 *
945 *  This routine is generallu used only to restart self in an
946 *  efficient manner.  It may simply be a label in _CPU_Context_switch.
947 *
948 *  NOTE: May be unnecessary to reload some registers.
949 */
950
951void _CPU_Context_restore(
952  Context_Control *new_context
953);
954
955/*
956 *  _CPU_Context_save_fp
957 *
958 *  This routine saves the floating point context passed to it.
959 */
960
961void _CPU_Context_save_fp(
962  void **fp_context_ptr
963);
964
965/*
966 *  _CPU_Context_restore_fp
967 *
968 *  This routine restores the floating point context passed to it.
969 */
970
971void _CPU_Context_restore_fp(
972  void **fp_context_ptr
973);
974
975void _CPU_Fatal_error(
976  unsigned32 _error
977);
978
979/*  The following routine swaps the endian format of an unsigned int.
980 *  It must be static because it is referenced indirectly.
981 *
982 *  This version will work on any processor, but if there is a better
983 *  way for your CPU PLEASE use it.  The most common way to do this is to:
984 *
985 *     swap least significant two bytes with 16-bit rotate
986 *     swap upper and lower 16-bits
987 *     swap most significant two bytes with 16-bit rotate
988 *
989 *  Some CPUs have special instructions which swap a 32-bit quantity in
990 *  a single instruction (e.g. i486).  It is probably best to avoid
991 *  an "endian swapping control bit" in the CPU.  One good reason is
992 *  that interrupts would probably have to be disabled to insure that
993 *  an interrupt does not try to access the same "chunk" with the wrong
994 *  endian.  Another good reason is that on some CPUs, the endian bit
995 *  endianness for ALL fetches -- both code and data -- so the code
996 *  will be fetched incorrectly.
997 */
998 
999static inline unsigned int CPU_swap_u32(
1000  unsigned int value
1001)
1002{
1003  unsigned32 swapped;
1004 
1005  asm volatile("rlwimi %0,%1,8,24,31;"
1006               "rlwimi %0,%1,24,16,23;"
1007               "rlwimi %0,%1,8,8,15;"
1008               "rlwimi %0,%1,24,0,7;" :
1009               "=r" ((swapped)) : "r" ((value)));
1010
1011  return( swapped );
1012}
1013
1014#ifdef __cplusplus
1015}
1016#endif
1017
1018#endif
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