source: rtems/c/src/exec/score/cpu/powerpc/cpu.h @ 60b791ad

4.104.114.84.95
Last change on this file since 60b791ad was 60b791ad, checked in by Joel Sherrill <joel.sherrill@…>, on Feb 17, 1998 at 11:46:28 PM

updated copyright to 1998

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1/*  cpu.h
2 *
3 *  This include file contains information pertaining to the PowerPC
4 *  processor.
5 *
6 *  Author:     Andrew Bray <andy@i-cubed.co.uk>
7 *
8 *  COPYRIGHT (c) 1995 by i-cubed ltd.
9 *
10 *  To anyone who acknowledges that this file is provided "AS IS"
11 *  without any express or implied warranty:
12 *      permission to use, copy, modify, and distribute this file
13 *      for any purpose is hereby granted without fee, provided that
14 *      the above copyright notice and this notice appears in all
15 *      copies, and that the name of i-cubed limited not be used in
16 *      advertising or publicity pertaining to distribution of the
17 *      software without specific, written prior permission.
18 *      i-cubed limited makes no representations about the suitability
19 *      of this software for any purpose.
20 *
21 *  Derived from c/src/exec/cpu/no_cpu/cpu.h:
22 *
23 *  COPYRIGHT (c) 1989-1998.
24 *  On-Line Applications Research Corporation (OAR).
25 *  Copyright assigned to U.S. Government, 1994.
26 *
27 *  The license and distribution terms for this file may be
28 *  found in the file LICENSE in this distribution or at
29 *  http://www.OARcorp.com/rtems/license.html.
30 *
31 *  $Id$
32 */
33
34#ifndef __CPU_h
35#define __CPU_h
36
37#ifdef __cplusplus
38extern "C" {
39#endif
40
41#include <rtems/score/ppc.h>               /* pick up machine definitions */
42#ifndef ASM
43struct CPU_Interrupt_frame;
44
45#include <rtems/score/ppctypes.h>
46#endif
47
48/* conditional compilation parameters */
49
50/*
51 *  Should the calls to _Thread_Enable_dispatch be inlined?
52 *
53 *  If TRUE, then they are inlined.
54 *  If FALSE, then a subroutine call is made.
55 *
56 *  Basically this is an example of the classic trade-off of size
57 *  versus speed.  Inlining the call (TRUE) typically increases the
58 *  size of RTEMS while speeding up the enabling of dispatching.
59 *  [NOTE: In general, the _Thread_Dispatch_disable_level will
60 *  only be 0 or 1 unless you are in an interrupt handler and that
61 *  interrupt handler invokes the executive.]  When not inlined
62 *  something calls _Thread_Enable_dispatch which in turns calls
63 *  _Thread_Dispatch.  If the enable dispatch is inlined, then
64 *  one subroutine call is avoided entirely.]
65 */
66
67#define CPU_INLINE_ENABLE_DISPATCH       FALSE
68
69/*
70 *  Should the body of the search loops in _Thread_queue_Enqueue_priority
71 *  be unrolled one time?  In unrolled each iteration of the loop examines
72 *  two "nodes" on the chain being searched.  Otherwise, only one node
73 *  is examined per iteration.
74 *
75 *  If TRUE, then the loops are unrolled.
76 *  If FALSE, then the loops are not unrolled.
77 *
78 *  The primary factor in making this decision is the cost of disabling
79 *  and enabling interrupts (_ISR_Flash) versus the cost of rest of the
80 *  body of the loop.  On some CPUs, the flash is more expensive than
81 *  one iteration of the loop body.  In this case, it might be desirable
82 *  to unroll the loop.  It is important to note that on some CPUs, this
83 *  code is the longest interrupt disable period in RTEMS.  So it is
84 *  necessary to strike a balance when setting this parameter.
85 */
86
87#define CPU_UNROLL_ENQUEUE_PRIORITY      FALSE
88
89/*
90 *  Does RTEMS manage a dedicated interrupt stack in software?
91 *
92 *  If TRUE, then a stack is allocated in _Interrupt_Manager_initialization.
93 *  If FALSE, nothing is done.
94 *
95 *  If the CPU supports a dedicated interrupt stack in hardware,
96 *  then it is generally the responsibility of the BSP to allocate it
97 *  and set it up.
98 *
99 *  If the CPU does not support a dedicated interrupt stack, then
100 *  the porter has two options: (1) execute interrupts on the
101 *  stack of the interrupted task, and (2) have RTEMS manage a dedicated
102 *  interrupt stack.
103 *
104 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
105 *
106 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
107 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
108 *  possible that both are FALSE for a particular CPU.  Although it
109 *  is unclear what that would imply about the interrupt processing
110 *  procedure on that CPU.
111 */
112
113#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE
114
115/*
116 *  Does this CPU have hardware support for a dedicated interrupt stack?
117 *
118 *  If TRUE, then it must be installed during initialization.
119 *  If FALSE, then no installation is performed.
120 *
121 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
122 *
123 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
124 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
125 *  possible that both are FALSE for a particular CPU.  Although it
126 *  is unclear what that would imply about the interrupt processing
127 *  procedure on that CPU.
128 */
129
130/*
131 *  ACB: This is a lie, but it gets us a handle on a call to set up
132 *  a variable derived from the top of the interrupt stack.
133 */
134
135#define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE
136
137/*
138 *  Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
139 *
140 *  If TRUE, then the memory is allocated during initialization.
141 *  If FALSE, then the memory is allocated during initialization.
142 *
143 *  This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE
144 *  or CPU_INSTALL_HARDWARE_INTERRUPT_STACK is TRUE.
145 */
146
147#define CPU_ALLOCATE_INTERRUPT_STACK TRUE
148
149/*
150 *  Does the CPU have hardware floating point?
151 *
152 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
153 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
154 *
155 *  If there is a FP coprocessor such as the i387 or mc68881, then
156 *  the answer is TRUE.
157 *
158 *  The macro name "PPC_HAS_FPU" should be made CPU specific.
159 *  It indicates whether or not this CPU model has FP support.  For
160 *  example, it would be possible to have an i386_nofp CPU model
161 *  which set this to false to indicate that you have an i386 without
162 *  an i387 and wish to leave floating point support out of RTEMS.
163 */
164
165#if ( PPC_HAS_FPU == 1 )
166#define CPU_HARDWARE_FP     TRUE
167#else
168#define CPU_HARDWARE_FP     FALSE
169#endif
170
171/*
172 *  Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
173 *
174 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
175 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
176 *
177 *  So far, the only CPU in which this option has been used is the
178 *  HP PA-RISC.  The HP C compiler and gcc both implicitly use the
179 *  floating point registers to perform integer multiplies.  If
180 *  a function which you would not think utilize the FP unit DOES,
181 *  then one can not easily predict which tasks will use the FP hardware.
182 *  In this case, this option should be TRUE.
183 *
184 *  If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
185 */
186
187#define CPU_ALL_TASKS_ARE_FP     FALSE
188
189/*
190 *  Should the IDLE task have a floating point context?
191 *
192 *  If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
193 *  and it has a floating point context which is switched in and out.
194 *  If FALSE, then the IDLE task does not have a floating point context.
195 *
196 *  Setting this to TRUE negatively impacts the time required to preempt
197 *  the IDLE task from an interrupt because the floating point context
198 *  must be saved as part of the preemption.
199 */
200
201#define CPU_IDLE_TASK_IS_FP      FALSE
202
203/*
204 *  Should the saving of the floating point registers be deferred
205 *  until a context switch is made to another different floating point
206 *  task?
207 *
208 *  If TRUE, then the floating point context will not be stored until
209 *  necessary.  It will remain in the floating point registers and not
210 *  disturned until another floating point task is switched to.
211 *
212 *  If FALSE, then the floating point context is saved when a floating
213 *  point task is switched out and restored when the next floating point
214 *  task is restored.  The state of the floating point registers between
215 *  those two operations is not specified.
216 *
217 *  If the floating point context does NOT have to be saved as part of
218 *  interrupt dispatching, then it should be safe to set this to TRUE.
219 *
220 *  Setting this flag to TRUE results in using a different algorithm
221 *  for deciding when to save and restore the floating point context.
222 *  The deferred FP switch algorithm minimizes the number of times
223 *  the FP context is saved and restored.  The FP context is not saved
224 *  until a context switch is made to another, different FP task.
225 *  Thus in a system with only one FP task, the FP context will never
226 *  be saved or restored.
227 */
228/*
229 *  ACB Note:  This could make debugging tricky..
230 */
231
232#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
233
234/*
235 *  Does this port provide a CPU dependent IDLE task implementation?
236 *
237 *  If TRUE, then the routine _CPU_Thread_Idle_body
238 *  must be provided and is the default IDLE thread body instead of
239 *  _CPU_Thread_Idle_body.
240 *
241 *  If FALSE, then use the generic IDLE thread body if the BSP does
242 *  not provide one.
243 *
244 *  This is intended to allow for supporting processors which have
245 *  a low power or idle mode.  When the IDLE thread is executed, then
246 *  the CPU can be powered down.
247 *
248 *  The order of precedence for selecting the IDLE thread body is:
249 *
250 *    1.  BSP provided
251 *    2.  CPU dependent (if provided)
252 *    3.  generic (if no BSP and no CPU dependent)
253 */
254
255#define CPU_PROVIDES_IDLE_THREAD_BODY    FALSE
256
257/*
258 *  Does the stack grow up (toward higher addresses) or down
259 *  (toward lower addresses)?
260 *
261 *  If TRUE, then the grows upward.
262 *  If FALSE, then the grows toward smaller addresses.
263 */
264
265#define CPU_STACK_GROWS_UP               FALSE
266
267/*
268 *  The following is the variable attribute used to force alignment
269 *  of critical RTEMS structures.  On some processors it may make
270 *  sense to have these aligned on tighter boundaries than
271 *  the minimum requirements of the compiler in order to have as
272 *  much of the critical data area as possible in a cache line.
273 *
274 *  The placement of this macro in the declaration of the variables
275 *  is based on the syntactically requirements of the GNU C
276 *  "__attribute__" extension.  For example with GNU C, use
277 *  the following to force a structures to a 32 byte boundary.
278 *
279 *      __attribute__ ((aligned (32)))
280 *
281 *  NOTE:  Currently only the Priority Bit Map table uses this feature.
282 *         To benefit from using this, the data must be heavily
283 *         used so it will stay in the cache and used frequently enough
284 *         in the executive to justify turning this on.
285 */
286
287#define CPU_STRUCTURE_ALIGNMENT \
288   __attribute__ ((aligned (PPC_CACHE_ALIGNMENT)))
289
290/*
291 *  Define what is required to specify how the network to host conversion
292 *  routines are handled.
293 */
294
295#define CPU_CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES FALSE
296#define CPU_BIG_ENDIAN                           TRUE
297#define CPU_LITTLE_ENDIAN                        FALSE
298
299/*
300 *  The following defines the number of bits actually used in the
301 *  interrupt field of the task mode.  How those bits map to the
302 *  CPU interrupt levels is defined by the routine _CPU_ISR_Set_level().
303 */
304/*
305 *  ACB Note: Levels are:
306 *   0: All maskable interrupts enabled
307 *   1: Other critical exceptions enabled
308 *   2: Machine check enabled
309 *   3: All maskable IRQs disabled
310 */
311
312#define CPU_MODES_INTERRUPT_MASK   0x00000003
313
314/*
315 *  Processor defined structures
316 *
317 *  Examples structures include the descriptor tables from the i386
318 *  and the processor control structure on the i960ca.
319 */
320
321/* may need to put some structures here.  */
322
323/*
324 * Contexts
325 *
326 *  Generally there are 2 types of context to save.
327 *     1. Interrupt registers to save
328 *     2. Task level registers to save
329 *
330 *  This means we have the following 3 context items:
331 *     1. task level context stuff::  Context_Control
332 *     2. floating point task stuff:: Context_Control_fp
333 *     3. special interrupt level context :: Context_Control_interrupt
334 *
335 *  On some processors, it is cost-effective to save only the callee
336 *  preserved registers during a task context switch.  This means
337 *  that the ISR code needs to save those registers which do not
338 *  persist across function calls.  It is not mandatory to make this
339 *  distinctions between the caller/callee saves registers for the
340 *  purpose of minimizing context saved during task switch and on interrupts.
341 *  If the cost of saving extra registers is minimal, simplicity is the
342 *  choice.  Save the same context on interrupt entry as for tasks in
343 *  this case.
344 *
345 *  Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
346 *  care should be used in designing the context area.
347 *
348 *  On some CPUs with hardware floating point support, the Context_Control_fp
349 *  structure will not be used or it simply consist of an array of a
350 *  fixed number of bytes.   This is done when the floating point context
351 *  is dumped by a "FP save context" type instruction and the format
352 *  is not really defined by the CPU.  In this case, there is no need
353 *  to figure out the exact format -- only the size.  Of course, although
354 *  this is enough information for RTEMS, it is probably not enough for
355 *  a debugger such as gdb.  But that is another problem.
356 */
357
358typedef struct {
359    unsigned32 gpr1;    /* Stack pointer for all */
360    unsigned32 gpr2;    /* TOC in PowerOpen, reserved SVR4, section ptr EABI + */
361    unsigned32 gpr13;   /* First non volatile PowerOpen, section ptr SVR4/EABI */
362    unsigned32 gpr14;   /* Non volatile for all */
363    unsigned32 gpr15;   /* Non volatile for all */
364    unsigned32 gpr16;   /* Non volatile for all */
365    unsigned32 gpr17;   /* Non volatile for all */
366    unsigned32 gpr18;   /* Non volatile for all */
367    unsigned32 gpr19;   /* Non volatile for all */
368    unsigned32 gpr20;   /* Non volatile for all */
369    unsigned32 gpr21;   /* Non volatile for all */
370    unsigned32 gpr22;   /* Non volatile for all */
371    unsigned32 gpr23;   /* Non volatile for all */
372    unsigned32 gpr24;   /* Non volatile for all */
373    unsigned32 gpr25;   /* Non volatile for all */
374    unsigned32 gpr26;   /* Non volatile for all */
375    unsigned32 gpr27;   /* Non volatile for all */
376    unsigned32 gpr28;   /* Non volatile for all */
377    unsigned32 gpr29;   /* Non volatile for all */
378    unsigned32 gpr30;   /* Non volatile for all */
379    unsigned32 gpr31;   /* Non volatile for all */
380    unsigned32 cr;      /* PART of the CR is non volatile for all */
381    unsigned32 pc;      /* Program counter/Link register */
382    unsigned32 msr;     /* Initial interrupt level */
383} Context_Control;
384
385typedef struct {
386    /* The ABIs (PowerOpen/SVR4/EABI) only require saving f14-f31 over
387     * procedure calls.  However, this would mean that the interrupt
388     * frame had to hold f0-f13, and the fpscr.  And as the majority
389     * of tasks will not have an FP context, we will save the whole
390     * context here.
391     */
392#if (PPC_HAS_DOUBLE == 1)
393    double      f[32];
394    double      fpscr;
395#else
396    float       f[32];
397    float       fpscr;
398#endif
399} Context_Control_fp;
400
401typedef struct CPU_Interrupt_frame {
402    unsigned32 stacklink;       /* Ensure this is a real frame (also reg1 save) */
403#if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27)
404    unsigned32 dummy[13];       /* Used by callees: PowerOpen ABI */
405#else
406    unsigned32 dummy[1];        /* Used by callees: SVR4/EABI */
407#endif
408    /* This is what is left out of the primary contexts */
409    unsigned32 gpr0;
410    unsigned32 gpr2;            /* play safe */
411    unsigned32 gpr3;
412    unsigned32 gpr4;
413    unsigned32 gpr5;
414    unsigned32 gpr6;
415    unsigned32 gpr7;
416    unsigned32 gpr8;
417    unsigned32 gpr9;
418    unsigned32 gpr10;
419    unsigned32 gpr11;
420    unsigned32 gpr12;
421    unsigned32 gpr13;   /* Play safe */
422    unsigned32 gpr28;   /* For internal use by the IRQ handler */
423    unsigned32 gpr29;   /* For internal use by the IRQ handler */
424    unsigned32 gpr30;   /* For internal use by the IRQ handler */
425    unsigned32 gpr31;   /* For internal use by the IRQ handler */
426    unsigned32 cr;      /* Bits of this are volatile, so no-one may save */
427    unsigned32 ctr;
428    unsigned32 xer;
429    unsigned32 lr;
430    unsigned32 pc;
431    unsigned32 msr;
432    unsigned32 pad[3];
433} CPU_Interrupt_frame;
434
435
436/*
437 *  The following table contains the information required to configure
438 *  the PowerPC processor specific parameters.
439 */
440
441typedef struct {
442  void       (*pretasking_hook)( void );
443  void       (*predriver_hook)( void );
444  void       (*postdriver_hook)( void );
445  void       (*idle_task)( void );
446  boolean      do_zero_of_workspace;
447  unsigned32   interrupt_stack_size;
448  unsigned32   extra_mpci_receive_server_stack;
449  void *     (*stack_allocate_hook)( unsigned32 );
450  void       (*stack_free_hook)( void* );
451  /* end of fields required on all CPUs */
452
453  unsigned32   clicks_per_usec; /* Timer clicks per microsecond */
454  unsigned32   serial_per_sec;  /* Serial clocks per second */
455  boolean      serial_external_clock;
456  boolean      serial_xon_xoff;
457  boolean      serial_cts_rts;
458  unsigned32   serial_rate;
459  unsigned32   timer_average_overhead; /* Average overhead of timer in ticks */
460  unsigned32   timer_least_valid; /* Least valid number from timer */
461  void (*spurious_handler)(unsigned32 vector, CPU_Interrupt_frame *);
462}   rtems_cpu_table;
463
464/*
465 *  This variable is optional.  It is used on CPUs on which it is difficult
466 *  to generate an "uninitialized" FP context.  It is filled in by
467 *  _CPU_Initialize and copied into the task's FP context area during
468 *  _CPU_Context_Initialize.
469 */
470
471/* EXTERN Context_Control_fp  _CPU_Null_fp_context; */
472
473/*
474 *  On some CPUs, RTEMS supports a software managed interrupt stack.
475 *  This stack is allocated by the Interrupt Manager and the switch
476 *  is performed in _ISR_Handler.  These variables contain pointers
477 *  to the lowest and highest addresses in the chunk of memory allocated
478 *  for the interrupt stack.  Since it is unknown whether the stack
479 *  grows up or down (in general), this give the CPU dependent
480 *  code the option of picking the version it wants to use.
481 *
482 *  NOTE: These two variables are required if the macro
483 *        CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
484 */
485
486SCORE_EXTERN void               *_CPU_Interrupt_stack_low;
487SCORE_EXTERN void               *_CPU_Interrupt_stack_high;
488
489/*
490 *  With some compilation systems, it is difficult if not impossible to
491 *  call a high-level language routine from assembly language.  This
492 *  is especially true of commercial Ada compilers and name mangling
493 *  C++ ones.  This variable can be optionally defined by the CPU porter
494 *  and contains the address of the routine _Thread_Dispatch.  This
495 *  can make it easier to invoke that routine at the end of the interrupt
496 *  sequence (if a dispatch is necessary).
497 */
498
499/* EXTERN void           (*_CPU_Thread_dispatch_pointer)(); */
500
501/*
502 *  Nothing prevents the porter from declaring more CPU specific variables.
503 */
504
505SCORE_EXTERN struct {
506  unsigned32 *Nest_level;
507  unsigned32 *Disable_level;
508  void *Vector_table;
509  void *Stack;
510#if (PPC_ABI == PPC_ABI_POWEROPEN)
511  unsigned32 Dispatch_r2;
512#else
513  unsigned32 Default_r2;
514#if (PPC_ABI != PPC_ABI_GCC27)
515  unsigned32 Default_r13;
516#endif
517#endif
518  volatile boolean *Switch_necessary;
519  boolean *Signal;
520} _CPU_IRQ_info CPU_STRUCTURE_ALIGNMENT;
521
522/*
523 *  The size of the floating point context area.  On some CPUs this
524 *  will not be a "sizeof" because the format of the floating point
525 *  area is not defined -- only the size is.  This is usually on
526 *  CPUs with a "floating point save context" instruction.
527 */
528
529#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
530
531/*
532 * (Optional) # of bytes for libmisc/stackchk to check
533 * If not specifed, then it defaults to something reasonable
534 * for most architectures.
535 */
536
537#define CPU_STACK_CHECK_SIZE    (128)
538
539/*
540 *  Amount of extra stack (above minimum stack size) required by
541 *  MPCI receive server thread.  Remember that in a multiprocessor
542 *  system this thread must exist and be able to process all directives.
543 */
544
545#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
546
547/*
548 *  This defines the number of entries in the ISR_Vector_table managed
549 *  by RTEMS.
550 */
551
552#define CPU_INTERRUPT_NUMBER_OF_VECTORS  (PPC_INTERRUPT_MAX)
553#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
554
555/*
556 *  Should be large enough to run all RTEMS tests.  This insures
557 *  that a "reasonable" small application should not have any problems.
558 */
559
560#define CPU_STACK_MINIMUM_SIZE          (1024*3)
561
562/*
563 *  CPU's worst alignment requirement for data types on a byte boundary.  This
564 *  alignment does not take into account the requirements for the stack.
565 */
566
567#define CPU_ALIGNMENT              (PPC_ALIGNMENT)
568
569/*
570 *  This number corresponds to the byte alignment requirement for the
571 *  heap handler.  This alignment requirement may be stricter than that
572 *  for the data types alignment specified by CPU_ALIGNMENT.  It is
573 *  common for the heap to follow the same alignment requirement as
574 *  CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict enough for the heap,
575 *  then this should be set to CPU_ALIGNMENT.
576 *
577 *  NOTE:  This does not have to be a power of 2.  It does have to
578 *         be greater or equal to than CPU_ALIGNMENT.
579 */
580
581#define CPU_HEAP_ALIGNMENT         (PPC_ALIGNMENT)
582
583/*
584 *  This number corresponds to the byte alignment requirement for memory
585 *  buffers allocated by the partition manager.  This alignment requirement
586 *  may be stricter than that for the data types alignment specified by
587 *  CPU_ALIGNMENT.  It is common for the partition to follow the same
588 *  alignment requirement as CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict
589 *  enough for the partition, then this should be set to CPU_ALIGNMENT.
590 *
591 *  NOTE:  This does not have to be a power of 2.  It does have to
592 *         be greater or equal to than CPU_ALIGNMENT.
593 */
594
595#define CPU_PARTITION_ALIGNMENT    (PPC_ALIGNMENT)
596
597/*
598 *  This number corresponds to the byte alignment requirement for the
599 *  stack.  This alignment requirement may be stricter than that for the
600 *  data types alignment specified by CPU_ALIGNMENT.  If the CPU_ALIGNMENT
601 *  is strict enough for the stack, then this should be set to 0.
602 *
603 *  NOTE:  This must be a power of 2 either 0 or greater than CPU_ALIGNMENT.
604 */
605
606#define CPU_STACK_ALIGNMENT        (PPC_STACK_ALIGNMENT)
607
608/* ISR handler macros */
609
610/*
611 *  Disable all interrupts for an RTEMS critical section.  The previous
612 *  level is returned in _level.
613 */
614
615#define loc_string(a,b) a " (" #b ")\n"
616
617#define _CPU_ISR_Disable( _isr_cookie ) \
618  { \
619    asm volatile ( \
620        "mfmsr %0; andc %1,%0,%1; mtmsr %1" : \
621        "=r" ((_isr_cookie)) : "r" ((PPC_MSR_DISABLE_MASK)) \
622        ); \
623  }
624
625/*
626 *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
627 *  This indicates the end of an RTEMS critical section.  The parameter
628 *  _level is not modified.
629 */
630
631#define _CPU_ISR_Enable( _isr_cookie )  \
632  { \
633     asm volatile ( "mtmsr %0" : \
634                   "=r" ((_isr_cookie)) : "0" ((_isr_cookie))); \
635  }
636
637/*
638 *  This temporarily restores the interrupt to _level before immediately
639 *  disabling them again.  This is used to divide long RTEMS critical
640 *  sections into two or more parts.  The parameter _level is not
641 * modified.
642 */
643
644#define _CPU_ISR_Flash( _isr_cookie ) \
645  { \
646    asm volatile ( \
647        "mtmsr %0; andc %1,%0,%1; mtmsr %1" : \
648        "=r" ((_isr_cookie)) : \
649        "r" ((PPC_MSR_DISABLE_MASK)), "0" ((_isr_cookie)) \
650        ); \
651  }
652
653/*
654 *  Map interrupt level in task mode onto the hardware that the CPU
655 *  actually provides.  Currently, interrupt levels which do not
656 *  map onto the CPU in a generic fashion are undefined.  Someday,
657 *  it would be nice if these were "mapped" by the application
658 *  via a callout.  For example, m68k has 8 levels 0 - 7, levels
659 *  8 - 255 would be available for bsp/application specific meaning.
660 *  This could be used to manage a programmable interrupt controller
661 *  via the rtems_task_mode directive.
662 */
663
664#define _CPU_ISR_Set_level( new_level ) \
665  { \
666    register unsigned32 tmp = 0; \
667    asm volatile ( \
668        "mfmsr %0; andc %0,%0,%1; and %2, %2, %1; or %0, %0, %2; mtmsr %0" : \
669        "=r" ((tmp)) : \
670        "r" ((PPC_MSR_DISABLE_MASK)), "r" ((_CPU_msrs[new_level])), "0" ((tmp)) \
671        ); \
672  }
673
674unsigned32 _CPU_ISR_Get_level( void );
675
676/* end of ISR handler macros */
677
678/* Context handler macros */
679
680/*
681 *  Initialize the context to a state suitable for starting a
682 *  task after a context restore operation.  Generally, this
683 *  involves:
684 *
685 *     - setting a starting address
686 *     - preparing the stack
687 *     - preparing the stack and frame pointers
688 *     - setting the proper interrupt level in the context
689 *     - initializing the floating point context
690 *
691 *  This routine generally does not set any unnecessary register
692 *  in the context.  The state of the "general data" registers is
693 *  undefined at task start time.
694 */
695
696#if PPC_ABI == PPC_ABI_POWEROPEN
697#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
698                                 _isr, _entry_point, _is_fp ) \
699  { \
700    unsigned32 sp, *desc; \
701    \
702    sp = ((unsigned32)_stack_base) + (_size) - 56; \
703    *((unsigned32 *)sp) = 0; \
704    \
705    desc = (unsigned32 *)_entry_point; \
706    \
707    (_the_context)->msr = PPC_MSR_INITIAL | \
708      _CPU_msrs[ _isr ]; \
709    (_the_context)->pc = desc[0]; \
710    (_the_context)->gpr1 = sp; \
711    (_the_context)->gpr2 = desc[1]; \
712  }
713#endif
714#if PPC_ABI == PPC_ABI_SVR4
715#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
716                                 _isr, _entry_point ) \
717  { \
718    unsigned32 sp, r13; \
719    \
720    sp = ((unsigned32)_stack_base) + (_size) - 8; \
721    *((unsigned32 *)sp) = 0; \
722    \
723    asm volatile ("mr %0, 13" : "=r" ((r13))); \
724    \
725    (_the_context->msr) = PPC_MSR_INITIAL | \
726      _CPU_msrs[ _isr ]; \
727    (_the_context->pc) = _entry_point; \
728    (_the_context->gpr1) = sp; \
729    (_the_context->gpr13) = r13; \
730  }
731#endif
732#if PPC_ABI == PPC_ABI_EABI
733#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
734                                 _isr, _entry_point ) \
735  { \
736    unsigned32 sp, r2, r13; \
737    \
738    sp = ((unsigned32)_stack_base) + (_size) - 8; \
739    *((unsigned32 *)sp) = 0; \
740    \
741    asm volatile ("mr %0,2; mr %1,13" : "=r" ((r2)), "=r" ((r13))); \
742    \
743    (_the_context)->msr = PPC_MSR_INITIAL | \
744      _CPU_msrs[ _isr ]; \
745    (_the_context->pc) = _entry_point; \
746    (_the_context->gpr1) = sp; \
747    (_the_context->gpr2) = r2; \
748    (_the_context->gpr13) = r13; \
749  }
750#endif
751
752/*
753 *  This routine is responsible for somehow restarting the currently
754 *  executing task.  If you are lucky, then all that is necessary
755 *  is restoring the context.  Otherwise, there will need to be
756 *  a special assembly routine which does something special in this
757 *  case.  Context_Restore should work most of the time.  It will
758 *  not work if restarting self conflicts with the stack frame
759 *  assumptions of restoring a context.
760 */
761
762#define _CPU_Context_Restart_self( _the_context ) \
763   _CPU_Context_restore( (_the_context) );
764
765/*
766 *  The purpose of this macro is to allow the initial pointer into
767 *  a floating point context area (used to save the floating point
768 *  context) to be at an arbitrary place in the floating point
769 *  context area.
770 *
771 *  This is necessary because some FP units are designed to have
772 *  their context saved as a stack which grows into lower addresses.
773 *  Other FP units can be saved by simply moving registers into offsets
774 *  from the base of the context area.  Finally some FP units provide
775 *  a "dump context" instruction which could fill in from high to low
776 *  or low to high based on the whim of the CPU designers.
777 */
778
779#define _CPU_Context_Fp_start( _base, _offset ) \
780   ( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
781
782/*
783 *  This routine initializes the FP context area passed to it to.
784 *  There are a few standard ways in which to initialize the
785 *  floating point context.  The code included for this macro assumes
786 *  that this is a CPU in which a "initial" FP context was saved into
787 *  _CPU_Null_fp_context and it simply copies it to the destination
788 *  context passed to it.
789 *
790 *  Other models include (1) not doing anything, and (2) putting
791 *  a "null FP status word" in the correct place in the FP context.
792 */
793
794#define _CPU_Context_Initialize_fp( _destination ) \
795  { \
796   ((Context_Control_fp *) *((void **) _destination))->fpscr = PPC_INIT_FPSCR; \
797  }
798
799/* end of Context handler macros */
800
801/* Fatal Error manager macros */
802
803/*
804 *  This routine copies _error into a known place -- typically a stack
805 *  location or a register, optionally disables interrupts, and
806 *  halts/stops the CPU.
807 */
808
809#define _CPU_Fatal_halt( _error ) \
810  _CPU_Fatal_error(_error)
811
812/* end of Fatal Error manager macros */
813
814/* Bitfield handler macros */
815
816/*
817 *  This routine sets _output to the bit number of the first bit
818 *  set in _value.  _value is of CPU dependent type Priority_Bit_map_control.
819 *  This type may be either 16 or 32 bits wide although only the 16
820 *  least significant bits will be used.
821 *
822 *  There are a number of variables in using a "find first bit" type
823 *  instruction.
824 *
825 *    (1) What happens when run on a value of zero?
826 *    (2) Bits may be numbered from MSB to LSB or vice-versa.
827 *    (3) The numbering may be zero or one based.
828 *    (4) The "find first bit" instruction may search from MSB or LSB.
829 *
830 *  RTEMS guarantees that (1) will never happen so it is not a concern.
831 *  (2),(3), (4) are handled by the macros _CPU_Priority_mask() and
832 *  _CPU_Priority_Bits_index().  These three form a set of routines
833 *  which must logically operate together.  Bits in the _value are
834 *  set and cleared based on masks built by _CPU_Priority_mask().
835 *  The basic major and minor values calculated by _Priority_Major()
836 *  and _Priority_Minor() are "massaged" by _CPU_Priority_Bits_index()
837 *  to properly range between the values returned by the "find first bit"
838 *  instruction.  This makes it possible for _Priority_Get_highest() to
839 *  calculate the major and directly index into the minor table.
840 *  This mapping is necessary to ensure that 0 (a high priority major/minor)
841 *  is the first bit found.
842 *
843 *  This entire "find first bit" and mapping process depends heavily
844 *  on the manner in which a priority is broken into a major and minor
845 *  components with the major being the 4 MSB of a priority and minor
846 *  the 4 LSB.  Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
847 *  priority.  And (15 << 4) + 14 corresponds to priority 254 -- the next
848 *  to the lowest priority.
849 *
850 *  If your CPU does not have a "find first bit" instruction, then
851 *  there are ways to make do without it.  Here are a handful of ways
852 *  to implement this in software:
853 *
854 *    - a series of 16 bit test instructions
855 *    - a "binary search using if's"
856 *    - _number = 0
857 *      if _value > 0x00ff
858 *        _value >>=8
859 *        _number = 8;
860 *
861 *      if _value > 0x0000f
862 *        _value >=8
863 *        _number += 4
864 *
865 *      _number += bit_set_table[ _value ]
866 *
867 *    where bit_set_table[ 16 ] has values which indicate the first
868 *      bit set
869 */
870
871#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
872  { \
873    asm volatile ("cntlzw %0, %1" : "=r" ((_output)), "=r" ((_value)) : \
874                  "1" ((_value))); \
875  }
876
877/* end of Bitfield handler macros */
878
879/*
880 *  This routine builds the mask which corresponds to the bit fields
881 *  as searched by _CPU_Bitfield_Find_first_bit().  See the discussion
882 *  for that routine.
883 */
884
885#define _CPU_Priority_Mask( _bit_number ) \
886  ( 0x80000000 >> (_bit_number) )
887
888/*
889 *  This routine translates the bit numbers returned by
890 *  _CPU_Bitfield_Find_first_bit() into something suitable for use as
891 *  a major or minor component of a priority.  See the discussion
892 *  for that routine.
893 */
894
895#define _CPU_Priority_bits_index( _priority ) \
896  (_priority)
897
898/* end of Priority handler macros */
899
900/* variables */
901
902extern const unsigned32 _CPU_msrs[4];
903
904/* functions */
905
906/*
907 *  _CPU_Initialize
908 *
909 *  This routine performs CPU dependent initialization.
910 */
911
912void _CPU_Initialize(
913  rtems_cpu_table  *cpu_table,
914  void      (*thread_dispatch)
915);
916
917/*
918 *  _CPU_ISR_install_vector
919 *
920 *  This routine installs an interrupt vector.
921 */
922
923void _CPU_ISR_install_vector(
924  unsigned32  vector,
925  proc_ptr    new_handler,
926  proc_ptr   *old_handler
927);
928
929/*
930 *  _CPU_Install_interrupt_stack
931 *
932 *  This routine installs the hardware interrupt stack pointer.
933 *
934 *  NOTE:  It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK
935 *         is TRUE.
936 */
937
938void _CPU_Install_interrupt_stack( void );
939
940/*
941 *  _CPU_Context_switch
942 *
943 *  This routine switches from the run context to the heir context.
944 */
945
946void _CPU_Context_switch(
947  Context_Control  *run,
948  Context_Control  *heir
949);
950
951/*
952 *  _CPU_Context_restore
953 *
954 *  This routine is generally used only to restart self in an
955 *  efficient manner.  It may simply be a label in _CPU_Context_switch.
956 *
957 *  NOTE: May be unnecessary to reload some registers.
958 */
959
960void _CPU_Context_restore(
961  Context_Control *new_context
962);
963
964/*
965 *  _CPU_Context_save_fp
966 *
967 *  This routine saves the floating point context passed to it.
968 */
969
970void _CPU_Context_save_fp(
971  void **fp_context_ptr
972);
973
974/*
975 *  _CPU_Context_restore_fp
976 *
977 *  This routine restores the floating point context passed to it.
978 */
979
980void _CPU_Context_restore_fp(
981  void **fp_context_ptr
982);
983
984void _CPU_Fatal_error(
985  unsigned32 _error
986);
987
988/*  The following routine swaps the endian format of an unsigned int.
989 *  It must be static because it is referenced indirectly.
990 *
991 *  This version will work on any processor, but if there is a better
992 *  way for your CPU PLEASE use it.  The most common way to do this is to:
993 *
994 *     swap least significant two bytes with 16-bit rotate
995 *     swap upper and lower 16-bits
996 *     swap most significant two bytes with 16-bit rotate
997 *
998 *  Some CPUs have special instructions which swap a 32-bit quantity in
999 *  a single instruction (e.g. i486).  It is probably best to avoid
1000 *  an "endian swapping control bit" in the CPU.  One good reason is
1001 *  that interrupts would probably have to be disabled to insure that
1002 *  an interrupt does not try to access the same "chunk" with the wrong
1003 *  endian.  Another good reason is that on some CPUs, the endian bit
1004 *  endianness for ALL fetches -- both code and data -- so the code
1005 *  will be fetched incorrectly.
1006 */
1007 
1008static inline unsigned int CPU_swap_u32(
1009  unsigned int value
1010)
1011{
1012  unsigned32 swapped;
1013 
1014  asm volatile("rlwimi %0,%1,8,24,31;"
1015               "rlwimi %0,%1,24,16,23;"
1016               "rlwimi %0,%1,8,8,15;"
1017               "rlwimi %0,%1,24,0,7;" :
1018               "=r" ((swapped)) : "r" ((value)));
1019
1020  return( swapped );
1021}
1022
1023#ifdef __cplusplus
1024}
1025#endif
1026
1027#endif
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