source: rtems/c/src/exec/score/cpu/powerpc/cpu.c @ eb5a7e07

4.104.114.84.95
Last change on this file since eb5a7e07 was eb5a7e07, checked in by Joel Sherrill <joel.sherrill@…>, on Oct 6, 1995 at 8:48:38 PM

fixed missing CVS IDs

  • Property mode set to 100644
File size: 5.8 KB
Line 
1/*
2 *  PowerPC CPU Dependent Source
3 *
4 *  Author:     Andrew Bray <andy@i-cubed.demon.co.uk>
5 *
6 *  COPYRIGHT (c) 1995 by i-cubed ltd.
7 *
8 *  To anyone who acknowledges that this file is provided "AS IS"
9 *  without any express or implied warranty:
10 *      permission to use, copy, modify, and distribute this file
11 *      for any purpose is hereby granted without fee, provided that
12 *      the above copyright notice and this notice appears in all
13 *      copies, and that the name of i-cubed limited not be used in
14 *      advertising or publicity pertaining to distribution of the
15 *      software without specific, written prior permission.
16 *      i-cubed limited makes no representations about the suitability
17 *      of this software for any purpose.
18 *
19 *  Derived from c/src/exec/cpu/no_cpu/cpu.c:
20 *
21 *  COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994.
22 *  On-Line Applications Research Corporation (OAR).
23 *  All rights assigned to U.S. Government, 1994.
24 *
25 *  This material may be reproduced by or for the U.S. Government pursuant
26 *  to the copyright license under the clause at DFARS 252.227-7013.  This
27 *  notice must appear in all copies of this file and its derivatives.
28 *
29 *  $Id$
30 */
31
32#include <rtems/system.h>
33#include <rtems/score/isr.h>
34#include <rtems/score/context.h>
35#include <rtems/score/thread.h>
36#include <rtems/score/wkspace.h>
37
38/*
39 *  These are for testing purposes.
40 */
41/*
42#define Testing
43*/
44
45#ifdef Testing
46static unsigned32 msr;
47#ifdef ppc403
48static unsigned32 evpr;
49static unsigned32 exier;
50#endif
51#endif
52
53/*
54 *  ppc_interrupt_level_to_msr
55 *
56 *  This routine converts a two bit interrupt level to an MSR bit map.
57 */
58
59const unsigned32 _CPU_msrs[4] =
60  { PPC_MSR_0, PPC_MSR_1, PPC_MSR_2, PPC_MSR_3 };
61
62/*  _CPU_Initialize
63 *
64 *  This routine performs processor dependent initialization.
65 *
66 *  INPUT PARAMETERS:
67 *    cpu_table       - CPU table to initialize
68 *    thread_dispatch - address of disptaching routine
69 */
70
71static void ppc_spurious(int, CPU_Interrupt_frame *);
72
73void _CPU_Initialize(
74  rtems_cpu_table  *cpu_table,
75  void      (*thread_dispatch)      /* ignored on this CPU */
76)
77{
78  proc_ptr handler = (proc_ptr)ppc_spurious;
79  int i;
80#if (PPC_ABI != PPC_ABI_POWEROPEN)
81  register unsigned32 r2;
82#if (PPC_ABI != PPC_ABI_GCC27)
83  register unsigned32 r13;
84
85  asm ("mr %0,13" : "=r" ((r13)) : "0" ((r13)));
86  _CPU_IRQ_info.Default_r13 = r13;
87#endif
88
89  asm ("mr %0,2" : "=r" ((r2)) : "0" ((r2)));
90  _CPU_IRQ_info.Default_r2 = r2;
91#endif
92
93  _CPU_IRQ_info.Nest_level = &_ISR_Nest_level;
94  _CPU_IRQ_info.Disable_level = &_Thread_Dispatch_disable_level;
95  _CPU_IRQ_info.Vector_table = _ISR_Vector_table;
96#if (PPC_ABI == PPC_ABI_POWEROPEN)
97  _CPU_IRQ_info.Dispatch_r2 = ((unsigned32 *)_Thread_Dispatch)[1];
98#endif
99  _CPU_IRQ_info.Switch_necessary = &_Context_Switch_necessary;
100  _CPU_IRQ_info.Signal = &_ISR_Signals_to_thread_executing;
101
102  i = (int)&_CPU_IRQ_info;
103  asm volatile("mtsprg3 %0" : "=r" (i) : "0" (i));
104
105  i = PPC_MSR_INITIAL & ~PPC_MSR_DISABLE_MASK;
106  asm volatile("mtsprg2 %0" : "=r" (i) : "0" (i));
107
108#ifdef Testing
109  {
110    unsigned32 tmp;
111
112    asm volatile ("mfmsr %0" : "=r" (tmp));
113    msr = tmp;
114#ifdef ppc403
115    asm volatile ("mfevpr %0" : "=r" (tmp));
116    evpr = tmp;
117    asm volatile ("mfexier %0" : "=r" (tmp));
118    exier = tmp;
119    asm volatile ("mtevpr %0" :: "r" (0));
120#endif
121  }
122#endif
123
124  if ( cpu_table->spurious_handler )
125    handler = (proc_ptr)cpu_table->spurious_handler;
126
127  for (i = 0; i < PPC_INTERRUPT_MAX;  i++)
128    _ISR_Vector_table[i] = handler;
129
130  _CPU_Table = *cpu_table;
131}
132
133/*  _CPU_ISR_install_vector
134 *
135 *  This kernel routine installs the RTEMS handler for the
136 *  specified vector.
137 *
138 *  Input parameters:
139 *    vector      - interrupt vector number
140 *    old_handler - former ISR for this vector number
141 *    new_handler - replacement ISR for this vector number
142 *
143 *  Output parameters:  NONE
144 *
145 */
146
147void _CPU_ISR_install_vector(
148  unsigned32  vector,
149  proc_ptr    new_handler,
150  proc_ptr   *old_handler
151)
152{
153   *old_handler = _ISR_Vector_table[ vector ];
154
155   /*
156    *  If the interrupt vector table is a table of pointer to isr entry
157    *  points, then we need to install the appropriate RTEMS interrupt
158    *  handler for this vector number.
159    */
160
161   /*
162    *  We put the actual user ISR address in '_ISR_vector_table'.  This will
163    *  be used by the _ISR_Handler so the user gets control.
164    */
165
166    _ISR_Vector_table[ vector ] = 
167       (new_handler) ? (ISR_Handler_entry) new_handler :
168       ((_CPU_Table.spurious_handler) ? 
169          (ISR_Handler_entry) _CPU_Table.spurious_handler :
170          (ISR_Handler_entry) ppc_spurious);
171}
172
173/*PAGE
174 *
175 *  _CPU_Install_interrupt_stack
176 */
177
178void _CPU_Install_interrupt_stack( void )
179{
180#if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27)
181  _CPU_IRQ_info.Stack = _CPU_Interrupt_stack_high - 56;
182#else
183  _CPU_IRQ_info.Stack = _CPU_Interrupt_stack_high - 8;
184#endif
185}
186
187/* Handle a spurious interrupt */
188static void ppc_spurious(int v, CPU_Interrupt_frame *i)
189{
190#if 0
191    printf("Spurious interrupt on vector %d from %08.8x\n",
192           v, i->pc);
193#endif
194#ifdef ppc403
195    if (v == PPC_IRQ_EXTERNAL)
196        {
197            register int r = 0;
198
199            asm volatile("mtexier %0" : "=r" ((r)) : "0" ((r)));
200        }
201    else if (v == PPC_IRQ_PIT)
202        {
203            register int r = 0x08000000;
204
205            asm volatile("mttsr %0" : "=r" ((r)) : "0" ((r)));
206        }
207    else if (v == PPC_IRQ_FIT)
208        {
209            register int r = 0x04000000;
210
211            asm volatile("mttsr %0" : "=r" ((r)) : "0" ((r)));
212        }
213#endif
214}
215
216void _CPU_Fatal_error(unsigned32 _error)
217{
218#ifdef Testing
219  unsigned32 tmp;
220
221  tmp = msr;
222  asm volatile ("mtmsr %0" :: "r" (tmp));
223#ifdef ppc403
224  tmp = evpr;
225  asm volatile ("mtevpr %0" :: "r" (tmp));
226  tmp = exier;
227  asm volatile ("mtexier %0" :: "r" (tmp));
228#endif
229#endif
230  asm volatile ("mr 3, %0" : : "r" ((_error)));
231  asm volatile ("tweq 5,5");
232  asm volatile ("li 0,0; mtmsr 0");
233  while (1) ;
234}
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