1 | /* |
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2 | * PowerPC CPU Dependent Source |
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3 | * |
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4 | * Author: Andrew Bray <andy@i-cubed.demon.co.uk> |
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5 | * |
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6 | * COPYRIGHT (c) 1995 by i-cubed ltd. |
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7 | * |
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8 | * To anyone who acknowledges that this file is provided "AS IS" |
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9 | * without any express or implied warranty: |
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10 | * permission to use, copy, modify, and distribute this file |
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11 | * for any purpose is hereby granted without fee, provided that |
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12 | * the above copyright notice and this notice appears in all |
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13 | * copies, and that the name of i-cubed limited not be used in |
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14 | * advertising or publicity pertaining to distribution of the |
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15 | * software without specific, written prior permission. |
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16 | * i-cubed limited makes no representations about the suitability |
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17 | * of this software for any purpose. |
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18 | * |
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19 | * Derived from c/src/exec/cpu/no_cpu/cpu.c: |
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20 | * |
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21 | * COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994. |
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22 | * On-Line Applications Research Corporation (OAR). |
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23 | * All rights assigned to U.S. Government, 1994. |
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24 | * |
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25 | * This material may be reproduced by or for the U.S. Government pursuant |
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26 | * to the copyright license under the clause at DFARS 252.227-7013. This |
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27 | * notice must appear in all copies of this file and its derivatives. |
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28 | * |
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29 | * $Id$ |
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30 | */ |
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31 | |
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32 | #include <rtems/system.h> |
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33 | #include <rtems/score/isr.h> |
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34 | #include <rtems/score/context.h> |
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35 | #include <rtems/score/thread.h> |
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36 | #include <rtems/score/wkspace.h> |
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37 | |
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38 | /* |
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39 | * These are for testing purposes. |
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40 | */ |
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41 | /* |
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42 | #define Testing |
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43 | */ |
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44 | |
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45 | #ifdef Testing |
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46 | static unsigned32 msr; |
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47 | #ifdef ppc403 |
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48 | static unsigned32 evpr; |
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49 | static unsigned32 exier; |
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50 | #endif |
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51 | #endif |
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52 | |
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53 | /* |
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54 | * ppc_interrupt_level_to_msr |
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55 | * |
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56 | * This routine converts a two bit interrupt level to an MSR bit map. |
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57 | */ |
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58 | |
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59 | const unsigned32 _CPU_msrs[4] = |
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60 | { PPC_MSR_0, PPC_MSR_1, PPC_MSR_2, PPC_MSR_3 }; |
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61 | |
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62 | /* _CPU_Initialize |
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63 | * |
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64 | * This routine performs processor dependent initialization. |
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65 | * |
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66 | * INPUT PARAMETERS: |
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67 | * cpu_table - CPU table to initialize |
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68 | * thread_dispatch - address of disptaching routine |
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69 | */ |
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70 | |
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71 | static void ppc_spurious(int, CPU_Interrupt_frame *); |
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72 | |
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73 | void _CPU_Initialize( |
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74 | rtems_cpu_table *cpu_table, |
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75 | void (*thread_dispatch) /* ignored on this CPU */ |
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76 | ) |
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77 | { |
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78 | proc_ptr handler = (proc_ptr)ppc_spurious; |
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79 | int i; |
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80 | #if (PPC_ABI != PPC_ABI_POWEROPEN) |
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81 | register unsigned32 r2; |
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82 | #if (PPC_ABI != PPC_ABI_GCC27) |
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83 | register unsigned32 r13; |
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84 | |
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85 | asm ("mr %0,13" : "=r" ((r13)) : "0" ((r13))); |
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86 | _CPU_IRQ_info.Default_r13 = r13; |
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87 | #endif |
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88 | |
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89 | asm ("mr %0,2" : "=r" ((r2)) : "0" ((r2))); |
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90 | _CPU_IRQ_info.Default_r2 = r2; |
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91 | #endif |
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92 | |
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93 | _CPU_IRQ_info.Nest_level = &_ISR_Nest_level; |
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94 | _CPU_IRQ_info.Disable_level = &_Thread_Dispatch_disable_level; |
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95 | _CPU_IRQ_info.Vector_table = _ISR_Vector_table; |
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96 | #if (PPC_ABI == PPC_ABI_POWEROPEN) |
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97 | _CPU_IRQ_info.Dispatch_r2 = ((unsigned32 *)_Thread_Dispatch)[1]; |
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98 | #endif |
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99 | _CPU_IRQ_info.Switch_necessary = &_Context_Switch_necessary; |
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100 | _CPU_IRQ_info.Signal = &_ISR_Signals_to_thread_executing; |
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101 | |
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102 | i = (int)&_CPU_IRQ_info; |
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103 | asm volatile("mtsprg3 %0" : "=r" (i) : "0" (i)); |
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104 | |
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105 | i = PPC_MSR_INITIAL & ~PPC_MSR_DISABLE_MASK; |
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106 | asm volatile("mtsprg2 %0" : "=r" (i) : "0" (i)); |
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107 | |
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108 | #ifdef Testing |
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109 | { |
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110 | unsigned32 tmp; |
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111 | |
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112 | asm volatile ("mfmsr %0" : "=r" (tmp)); |
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113 | msr = tmp; |
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114 | #ifdef ppc403 |
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115 | asm volatile ("mfevpr %0" : "=r" (tmp)); |
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116 | evpr = tmp; |
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117 | asm volatile ("mfexier %0" : "=r" (tmp)); |
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118 | exier = tmp; |
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119 | asm volatile ("mtevpr %0" :: "r" (0)); |
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120 | #endif |
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121 | } |
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122 | #endif |
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123 | |
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124 | if ( cpu_table->spurious_handler ) |
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125 | handler = (proc_ptr)cpu_table->spurious_handler; |
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126 | |
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127 | for (i = 0; i < PPC_INTERRUPT_MAX; i++) |
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128 | _ISR_Vector_table[i] = handler; |
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129 | |
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130 | _CPU_Table = *cpu_table; |
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131 | } |
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132 | |
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133 | /* _CPU_ISR_install_vector |
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134 | * |
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135 | * This kernel routine installs the RTEMS handler for the |
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136 | * specified vector. |
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137 | * |
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138 | * Input parameters: |
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139 | * vector - interrupt vector number |
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140 | * old_handler - former ISR for this vector number |
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141 | * new_handler - replacement ISR for this vector number |
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142 | * |
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143 | * Output parameters: NONE |
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144 | * |
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145 | */ |
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146 | |
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147 | void _CPU_ISR_install_vector( |
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148 | unsigned32 vector, |
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149 | proc_ptr new_handler, |
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150 | proc_ptr *old_handler |
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151 | ) |
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152 | { |
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153 | *old_handler = _ISR_Vector_table[ vector ]; |
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154 | |
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155 | /* |
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156 | * If the interrupt vector table is a table of pointer to isr entry |
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157 | * points, then we need to install the appropriate RTEMS interrupt |
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158 | * handler for this vector number. |
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159 | */ |
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160 | |
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161 | /* |
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162 | * We put the actual user ISR address in '_ISR_vector_table'. This will |
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163 | * be used by the _ISR_Handler so the user gets control. |
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164 | */ |
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165 | |
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166 | _ISR_Vector_table[ vector ] = |
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167 | (new_handler) ? (ISR_Handler_entry) new_handler : |
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168 | ((_CPU_Table.spurious_handler) ? |
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169 | (ISR_Handler_entry) _CPU_Table.spurious_handler : |
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170 | (ISR_Handler_entry) ppc_spurious); |
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171 | } |
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172 | |
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173 | /*PAGE |
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174 | * |
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175 | * _CPU_Install_interrupt_stack |
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176 | */ |
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177 | |
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178 | void _CPU_Install_interrupt_stack( void ) |
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179 | { |
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180 | #if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27) |
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181 | _CPU_IRQ_info.Stack = _CPU_Interrupt_stack_high - 56; |
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182 | #else |
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183 | _CPU_IRQ_info.Stack = _CPU_Interrupt_stack_high - 8; |
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184 | #endif |
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185 | } |
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186 | |
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187 | /* Handle a spurious interrupt */ |
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188 | static void ppc_spurious(int v, CPU_Interrupt_frame *i) |
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189 | { |
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190 | #if 0 |
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191 | printf("Spurious interrupt on vector %d from %08.8x\n", |
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192 | v, i->pc); |
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193 | #endif |
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194 | #ifdef ppc403 |
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195 | if (v == PPC_IRQ_EXTERNAL) |
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196 | { |
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197 | register int r = 0; |
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198 | |
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199 | asm volatile("mtexier %0" : "=r" ((r)) : "0" ((r))); |
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200 | } |
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201 | else if (v == PPC_IRQ_PIT) |
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202 | { |
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203 | register int r = 0x08000000; |
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204 | |
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205 | asm volatile("mttsr %0" : "=r" ((r)) : "0" ((r))); |
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206 | } |
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207 | else if (v == PPC_IRQ_FIT) |
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208 | { |
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209 | register int r = 0x04000000; |
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210 | |
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211 | asm volatile("mttsr %0" : "=r" ((r)) : "0" ((r))); |
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212 | } |
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213 | #endif |
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214 | } |
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215 | |
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216 | void _CPU_Fatal_error(unsigned32 _error) |
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217 | { |
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218 | #ifdef Testing |
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219 | unsigned32 tmp; |
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220 | |
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221 | tmp = msr; |
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222 | asm volatile ("mtmsr %0" :: "r" (tmp)); |
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223 | #ifdef ppc403 |
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224 | tmp = evpr; |
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225 | asm volatile ("mtevpr %0" :: "r" (tmp)); |
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226 | tmp = exier; |
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227 | asm volatile ("mtexier %0" :: "r" (tmp)); |
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228 | #endif |
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229 | #endif |
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230 | asm volatile ("mr 3, %0" : : "r" ((_error))); |
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231 | asm volatile ("tweq 5,5"); |
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232 | asm volatile ("li 0,0; mtmsr 0"); |
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233 | while (1) ; |
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234 | } |
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