1 | /* |
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2 | * PowerPC CPU Dependent Source |
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3 | * |
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4 | * Author: Andrew Bray <andy@i-cubed.co.uk> |
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5 | * |
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6 | * COPYRIGHT (c) 1995 by i-cubed ltd. |
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7 | * |
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8 | * To anyone who acknowledges that this file is provided "AS IS" |
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9 | * without any express or implied warranty: |
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10 | * permission to use, copy, modify, and distribute this file |
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11 | * for any purpose is hereby granted without fee, provided that |
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12 | * the above copyright notice and this notice appears in all |
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13 | * copies, and that the name of i-cubed limited not be used in |
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14 | * advertising or publicity pertaining to distribution of the |
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15 | * software without specific, written prior permission. |
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16 | * i-cubed limited makes no representations about the suitability |
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17 | * of this software for any purpose. |
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18 | * |
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19 | * Derived from c/src/exec/cpu/no_cpu/cpu.c: |
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20 | * |
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21 | * COPYRIGHT (c) 1989-1997. |
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22 | * On-Line Applications Research Corporation (OAR). |
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23 | * Copyright assigned to U.S. Government, 1994. |
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24 | * |
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25 | * The license and distribution terms for this file may be found in |
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26 | * the file LICENSE in this distribution or at |
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27 | * http://www.OARcorp.com/rtems/license.html. |
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28 | * |
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29 | * $Id$ |
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30 | */ |
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31 | |
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32 | #include <rtems/system.h> |
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33 | #include <rtems/score/isr.h> |
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34 | #include <rtems/score/context.h> |
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35 | #include <rtems/score/thread.h> |
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36 | #include <rtems/score/interr.h> |
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37 | |
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38 | /* |
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39 | * These are for testing purposes. |
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40 | */ |
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41 | |
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42 | /* _CPU_Initialize |
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43 | * |
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44 | * This routine performs processor dependent initialization. |
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45 | * |
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46 | * INPUT PARAMETERS: |
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47 | * cpu_table - CPU table to initialize |
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48 | * thread_dispatch - address of disptaching routine |
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49 | */ |
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50 | |
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51 | static void ppc_spurious(int, CPU_Interrupt_frame *); |
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52 | |
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53 | void _CPU_Initialize( |
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54 | rtems_cpu_table *cpu_table, |
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55 | void (*thread_dispatch) /* ignored on this CPU */ |
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56 | ) |
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57 | { |
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58 | proc_ptr handler = (proc_ptr)ppc_spurious; |
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59 | int i; |
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60 | #if (PPC_ABI != PPC_ABI_POWEROPEN) |
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61 | register unsigned32 r2 = 0; |
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62 | #if (PPC_ABI != PPC_ABI_GCC27) |
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63 | register unsigned32 r13 = 0; |
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64 | |
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65 | asm ("mr %0,13" : "=r" ((r13)) : "0" ((r13))); |
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66 | _CPU_IRQ_info.Default_r13 = r13; |
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67 | #endif |
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68 | |
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69 | asm ("mr %0,2" : "=r" ((r2)) : "0" ((r2))); |
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70 | _CPU_IRQ_info.Default_r2 = r2; |
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71 | #endif |
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72 | |
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73 | _CPU_IRQ_info.Nest_level = &_ISR_Nest_level; |
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74 | _CPU_IRQ_info.Disable_level = &_Thread_Dispatch_disable_level; |
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75 | _CPU_IRQ_info.Vector_table = _ISR_Vector_table; |
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76 | #if (PPC_ABI == PPC_ABI_POWEROPEN) |
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77 | _CPU_IRQ_info.Dispatch_r2 = ((unsigned32 *)_Thread_Dispatch)[1]; |
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78 | #endif |
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79 | _CPU_IRQ_info.Switch_necessary = &_Context_Switch_necessary; |
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80 | _CPU_IRQ_info.Signal = &_ISR_Signals_to_thread_executing; |
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81 | |
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82 | #if (PPC_USE_SPRG) |
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83 | i = (int)&_CPU_IRQ_info; |
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84 | asm volatile("mtspr 0x113, %0" : "=r" (i) : "0" (i)); /* SPRG 3 */ |
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85 | #endif |
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86 | |
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87 | /* |
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88 | * Store Msr Value in the IRQ info structure. |
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89 | */ |
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90 | _CPU_MSR_Value(_CPU_IRQ_info.msr_initial); |
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91 | |
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92 | #if (PPC_USE_SPRG) |
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93 | i = _CPU_IRQ_info.msr_initial; |
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94 | asm volatile("mtspr 0x112, %0" : "=r" (i) : "0" (i)); /* SPRG 2 */ |
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95 | #endif |
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96 | |
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97 | if ( cpu_table->spurious_handler ) |
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98 | handler = (proc_ptr)cpu_table->spurious_handler; |
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99 | |
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100 | for (i = 0; i < PPC_INTERRUPT_MAX; i++) |
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101 | _ISR_Vector_table[i] = handler; |
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102 | |
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103 | _CPU_Table = *cpu_table; |
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104 | } |
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105 | |
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106 | /*PAGE |
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107 | * |
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108 | * _CPU_ISR_Calculate_level |
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109 | * |
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110 | * The PowerPC puts its interrupt enable status in the MSR register |
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111 | * which also contains things like endianness control. To be more |
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112 | * awkward, the layout varies from processor to processor. This |
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113 | * is why it was necessary to adopt a scheme which allowed the user |
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114 | * to specify specifically which interrupt sources were enabled. |
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115 | */ |
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116 | |
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117 | unsigned32 _CPU_ISR_Calculate_level( |
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118 | unsigned32 new_level |
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119 | ) |
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120 | { |
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121 | register unsigned32 new_msr = 0; |
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122 | |
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123 | /* |
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124 | * Set the critical interrupt enable bit |
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125 | */ |
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126 | |
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127 | #if (PPC_HAS_RFCI) |
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128 | if ( !(new_level & PPC_INTERRUPT_LEVEL_CE) ) |
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129 | new_msr |= PPC_MSR_CE; |
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130 | #endif |
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131 | |
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132 | if ( !(new_level & PPC_INTERRUPT_LEVEL_ME) ) |
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133 | new_msr |= PPC_MSR_ME; |
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134 | |
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135 | if ( !(new_level & PPC_INTERRUPT_LEVEL_EE) ) |
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136 | new_msr |= PPC_MSR_EE; |
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137 | |
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138 | return new_msr; |
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139 | } |
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140 | |
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141 | /*PAGE |
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142 | * |
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143 | * _CPU_ISR_Set_level |
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144 | * |
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145 | * This routine sets the requested level in the MSR. |
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146 | */ |
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147 | |
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148 | void _CPU_ISR_Set_level( |
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149 | unsigned32 new_level |
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150 | ) |
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151 | { |
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152 | register unsigned32 tmp = 0; |
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153 | register unsigned32 new_msr; |
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154 | |
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155 | new_msr = _CPU_ISR_Calculate_level( new_level ); |
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156 | |
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157 | asm volatile ( |
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158 | "mfmsr %0; andc %0,%0,%1; and %2, %2, %1; or %0, %0, %2; mtmsr %0" : |
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159 | "=&r" ((tmp)) : |
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160 | "r" ((PPC_MSR_DISABLE_MASK)), "r" ((new_msr)), "0" ((tmp)) |
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161 | ); |
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162 | } |
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163 | |
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164 | /*PAGE |
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165 | * |
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166 | * _CPU_ISR_Get_level |
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167 | * |
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168 | * This routine gets the current interrupt level from the MSR and |
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169 | * converts it to an RTEMS interrupt level. |
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170 | */ |
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171 | |
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172 | unsigned32 _CPU_ISR_Get_level( void ) |
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173 | { |
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174 | unsigned32 level = 0; |
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175 | unsigned32 msr; |
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176 | |
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177 | asm volatile("mfmsr %0" : "=r" ((msr))); |
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178 | |
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179 | msr &= PPC_MSR_DISABLE_MASK; |
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180 | |
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181 | /* |
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182 | * Set the critical interrupt enable bit |
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183 | */ |
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184 | |
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185 | #if (PPC_HAS_RFCI) |
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186 | if ( !(msr & PPC_MSR_CE) ) |
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187 | level |= PPC_INTERRUPT_LEVEL_CE; |
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188 | #endif |
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189 | |
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190 | if ( !(msr & PPC_MSR_ME) ) |
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191 | level |= PPC_INTERRUPT_LEVEL_ME; |
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192 | |
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193 | if ( !(msr & PPC_MSR_EE) ) |
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194 | level |= PPC_INTERRUPT_LEVEL_EE; |
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195 | |
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196 | return level; |
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197 | } |
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198 | |
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199 | /*PAGE |
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200 | * |
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201 | * _CPU_Context_Initialize |
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202 | */ |
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203 | |
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204 | #if (PPC_ABI == PPC_ABI_POWEROPEN) |
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205 | #define CPU_MINIMUM_STACK_FRAME_SIZE 56 |
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206 | #else /* PPC_ABI_SVR4 or PPC_ABI_EABI */ |
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207 | #define CPU_MINIMUM_STACK_FRAME_SIZE 8 |
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208 | #endif |
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209 | |
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210 | void _CPU_Context_Initialize( |
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211 | Context_Control *the_context, |
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212 | unsigned32 *stack_base, |
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213 | unsigned32 size, |
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214 | unsigned32 new_level, |
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215 | void *entry_point, |
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216 | boolean is_fp |
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217 | ) |
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218 | { |
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219 | unsigned32 msr_value; |
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220 | unsigned32 sp; |
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221 | |
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222 | sp = (unsigned32)stack_base + size - CPU_MINIMUM_STACK_FRAME_SIZE; |
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223 | *((unsigned32 *)sp) = 0; |
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224 | the_context->gpr1 = sp; |
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225 | |
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226 | the_context->msr = _CPU_ISR_Calculate_level( new_level ); |
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227 | |
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228 | /* |
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229 | * The FP bit of the MSR should only be enabled if this is a floating |
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230 | * point task. Unfortunately, the vfprintf_r routine in newlib |
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231 | * ends up pushing a floating point register regardless of whether or |
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232 | * not a floating point number is being printed. Serious restructuring |
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233 | * of vfprintf.c will be required to avoid this behavior. At this |
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234 | * time (7 July 1997), this restructuring is not being done. |
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235 | */ |
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236 | |
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237 | /*if ( is_fp ) */ |
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238 | the_context->msr |= PPC_MSR_FP; |
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239 | |
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240 | /* |
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241 | * Calculate the task's MSR value: |
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242 | * |
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243 | * + Set the exception prefix bit to point to the exception table |
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244 | * + Force the RI bit |
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245 | * + Use the DR and IR bits |
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246 | */ |
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247 | _CPU_MSR_Value( msr_value ); |
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248 | the_context->msr |= (msr_value & PPC_MSR_EP); |
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249 | the_context->msr |= PPC_MSR_RI; |
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250 | the_context->msr |= msr_value & (PPC_MSR_DR|PPC_MSR_IR); |
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251 | |
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252 | #if (PPC_ABI == PPC_ABI_POWEROPEN) |
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253 | { unsigned32 *desc = (unsigned32 *)entry_point; |
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254 | |
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255 | the_context->pc = desc[0]; |
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256 | the_context->gpr2 = desc[1]; |
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257 | } |
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258 | #endif |
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259 | |
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260 | #if (PPC_ABI == PPC_ABI_SVR4) |
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261 | { unsigned r13 = 0; |
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262 | asm volatile ("mr %0, 13" : "=r" ((r13))); |
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263 | |
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264 | the_context->pc = (unsigned32)entry_point; |
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265 | the_context->gpr13 = r13; |
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266 | } |
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267 | #endif |
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268 | |
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269 | #if (PPC_ABI == PPC_ABI_EABI) |
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270 | { unsigned32 r2 = 0; |
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271 | unsigned r13 = 0; |
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272 | asm volatile ("mr %0,2; mr %1,13" : "=r" ((r2)), "=r" ((r13))); |
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273 | |
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274 | the_context->pc = (unsigned32)entry_point; |
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275 | the_context->gpr2 = r2; |
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276 | the_context->gpr13 = r13; |
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277 | } |
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278 | #endif |
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279 | } |
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280 | |
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281 | |
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282 | /* _CPU_ISR_install_vector |
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283 | * |
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284 | * This kernel routine installs the RTEMS handler for the |
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285 | * specified vector. |
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286 | * |
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287 | * Input parameters: |
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288 | * vector - interrupt vector number |
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289 | * old_handler - former ISR for this vector number |
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290 | * new_handler - replacement ISR for this vector number |
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291 | * |
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292 | * Output parameters: NONE |
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293 | * |
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294 | */ |
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295 | |
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296 | void _CPU_ISR_install_vector( |
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297 | unsigned32 vector, |
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298 | proc_ptr new_handler, |
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299 | proc_ptr *old_handler |
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300 | ) |
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301 | { |
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302 | proc_ptr ignored; |
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303 | *old_handler = _ISR_Vector_table[ vector ]; |
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304 | |
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305 | /* |
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306 | * If the interrupt vector table is a table of pointer to isr entry |
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307 | * points, then we need to install the appropriate RTEMS interrupt |
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308 | * handler for this vector number. |
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309 | */ |
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310 | |
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311 | /* |
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312 | * Install the wrapper so this ISR can be invoked properly. |
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313 | */ |
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314 | if (_CPU_Table.exceptions_in_RAM) |
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315 | _CPU_ISR_install_raw_handler( vector, _ISR_Handler, &ignored ); |
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316 | |
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317 | /* |
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318 | * We put the actual user ISR address in '_ISR_vector_table'. This will |
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319 | * be used by the _ISR_Handler so the user gets control. |
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320 | */ |
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321 | |
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322 | _ISR_Vector_table[ vector ] = new_handler ? (ISR_Handler_entry)new_handler : |
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323 | _CPU_Table.spurious_handler ? |
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324 | (ISR_Handler_entry)_CPU_Table.spurious_handler : |
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325 | (ISR_Handler_entry)ppc_spurious; |
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326 | } |
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327 | |
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328 | /*PAGE |
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329 | * |
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330 | * _CPU_Install_interrupt_stack |
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331 | */ |
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332 | |
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333 | void _CPU_Install_interrupt_stack( void ) |
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334 | { |
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335 | #if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27) |
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336 | _CPU_IRQ_info.Stack = _CPU_Interrupt_stack_high - 56; |
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337 | #else |
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338 | _CPU_IRQ_info.Stack = _CPU_Interrupt_stack_high - 8; |
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339 | #endif |
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340 | } |
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341 | |
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342 | /* Handle a spurious interrupt */ |
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343 | static void ppc_spurious(int v, CPU_Interrupt_frame *i) |
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344 | { |
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345 | #if 0 |
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346 | printf("Spurious interrupt on vector %d from %08.8x\n", |
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347 | v, i->pc); |
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348 | #endif |
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349 | #ifdef ppc403 |
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350 | if (v == PPC_IRQ_EXTERNAL) |
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351 | { |
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352 | register int r = 0; |
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353 | |
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354 | asm volatile("mtdcr 0x42, %0" : |
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355 | "=&r" ((r)) : "0" ((r))); /* EXIER */ |
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356 | } |
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357 | else if (v == PPC_IRQ_PIT) |
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358 | { |
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359 | register int r = 0x08000000; |
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360 | |
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361 | asm volatile("mtspr 0x3d8, %0" : |
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362 | "=&r" ((r)) : "0" ((r))); /* TSR */ |
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363 | } |
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364 | else if (v == PPC_IRQ_FIT) |
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365 | { |
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366 | register int r = 0x04000000; |
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367 | |
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368 | asm volatile("mtspr 0x3d8, %0" : |
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369 | "=&r" ((r)) : "0" ((r))); /* TSR */ |
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370 | } |
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371 | #endif |
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372 | } |
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373 | |
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374 | void _CPU_Fatal_error(unsigned32 _error) |
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375 | { |
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376 | asm volatile ("mr 3, %0" : : "r" ((_error))); |
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377 | asm volatile ("tweq 5,5"); |
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378 | asm volatile ("li 0,0; mtmsr 0"); |
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379 | while (1) ; |
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380 | } |
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381 | |
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382 | #define PPC_SYNCHRONOUS_TRAP_BIT_MASK 0x100 |
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383 | #define PPC_ASYNCHRONOUS_TRAP( _trap ) (_trap) |
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384 | #define PPC_SYNCHRONOUS_TRAP ( _trap ) ((_trap)+PPC_SYNCHRONOUS_TRAP_BIT_MASK) |
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385 | #define PPC_REAL_TRAP_NUMBER ( _trap ) ((_trap)%PPC_SYNCHRONOUS_TRAP_BIT_MASK) |
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386 | |
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387 | |
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388 | const CPU_Trap_table_entry _CPU_Trap_slot_template = { |
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389 | |
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390 | #if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27) |
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391 | #error " Vector install not tested." |
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392 | #if (PPC_HAS_FPU) |
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393 | #error " Vector install not tested." |
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394 | 0x9421feb0, /* stwu r1, -(20*4 + 18*8 + IP_END)(r1) */ |
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395 | #else |
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396 | #error " Vector install not tested." |
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397 | 0x9421ff40, /* stwu r1, -(20*4 + IP_END)(r1) */ |
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398 | #endif |
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399 | #else |
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400 | 0x9421ff90, /* stwu r1, -(IP_END)(r1) */ |
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401 | #endif |
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402 | |
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403 | 0x90010008, /* stw %r0, IP_0(%r1) */ |
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404 | 0x38000000, /* li %r0, PPC_IRQ */ |
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405 | 0x48000002 /* ba PROC (_ISR_Handler) */ |
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406 | }; |
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407 | |
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408 | unsigned32 ppc_exception_vector_addr( |
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409 | unsigned32 vector |
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410 | ); |
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411 | |
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412 | |
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413 | /*PAGE |
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414 | * |
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415 | * _CPU_ISR_install_raw_handler |
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416 | * |
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417 | * This routine installs the specified handler as a "raw" non-executive |
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418 | * supported trap handler (a.k.a. interrupt service routine). |
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419 | * |
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420 | * Input Parameters: |
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421 | * vector - trap table entry number plus synchronous |
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422 | * vs. asynchronous information |
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423 | * new_handler - address of the handler to be installed |
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424 | * old_handler - pointer to an address of the handler previously installed |
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425 | * |
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426 | * Output Parameters: NONE |
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427 | * *new_handler - address of the handler previously installed |
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428 | * |
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429 | * NOTE: |
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430 | * |
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431 | * This routine is based on the SPARC routine _CPU_ISR_install_raw_handler. |
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432 | * Install a software trap handler as an executive interrupt handler |
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433 | * (which is desirable since RTEMS takes care of window and register issues), |
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434 | * then the executive needs to know that the return address is to the trap |
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435 | * rather than the instruction following the trap. |
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436 | * |
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437 | */ |
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438 | |
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439 | void _CPU_ISR_install_raw_handler( |
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440 | unsigned32 vector, |
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441 | proc_ptr new_handler, |
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442 | proc_ptr *old_handler |
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443 | ) |
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444 | { |
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445 | unsigned32 real_vector; |
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446 | CPU_Trap_table_entry *slot; |
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447 | unsigned32 u32_handler=0; |
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448 | |
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449 | /* |
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450 | * Get the "real" trap number for this vector ignoring the synchronous |
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451 | * versus asynchronous indicator included with our vector numbers. |
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452 | */ |
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453 | |
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454 | real_vector = vector; |
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455 | |
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456 | /* |
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457 | * Get the current base address of the trap table and calculate a pointer |
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458 | * to the slot we are interested in. |
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459 | */ |
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460 | slot = (CPU_Trap_table_entry *)ppc_exception_vector_addr( real_vector ); |
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461 | |
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462 | /* |
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463 | * Get the address of the old_handler from the trap table. |
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464 | * |
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465 | * NOTE: The old_handler returned will be bogus if it does not follow |
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466 | * the RTEMS model. |
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467 | */ |
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468 | |
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469 | #define HIGH_BITS_MASK 0xFFFFFC00 |
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470 | #define HIGH_BITS_SHIFT 10 |
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471 | #define LOW_BITS_MASK 0x000003FF |
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472 | |
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473 | if (slot->stwu_r1 == _CPU_Trap_slot_template.stwu_r1) { |
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474 | /* |
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475 | * Set u32_handler = to target address |
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476 | */ |
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477 | u32_handler = slot->b_Handler & 0x03fffffc; |
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478 | |
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479 | /* IMD FIX: sign extend address fragment... */ |
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480 | if (u32_handler & 0x02000000) { |
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481 | u32_handler |= 0xfc000000; |
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482 | } |
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483 | |
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484 | *old_handler = (proc_ptr) u32_handler; |
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485 | } else |
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486 | *old_handler = 0; |
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487 | |
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488 | /* |
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489 | * Copy the template to the slot and then fix it. |
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490 | */ |
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491 | *slot = _CPU_Trap_slot_template; |
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492 | |
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493 | u32_handler = (unsigned32) new_handler; |
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494 | |
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495 | /* |
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496 | * IMD FIX: insert address fragment only (bits 6..29) |
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497 | * therefore check for proper address range |
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498 | * and remove unwanted bits |
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499 | */ |
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500 | if ((u32_handler & 0xfc000000) == 0xfc000000) { |
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501 | u32_handler &= ~0xfc000000; |
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502 | } |
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503 | else if ((u32_handler & 0xfc000000) != 0x00000000) { |
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504 | _Internal_error_Occurred(INTERNAL_ERROR_CORE, |
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505 | TRUE, |
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506 | u32_handler); |
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507 | } |
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508 | |
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509 | slot->b_Handler |= u32_handler; |
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510 | |
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511 | slot->li_r0_IRQ |= vector; |
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512 | |
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513 | _CPU_Data_Cache_Block_Flush( slot ); |
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514 | } |
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515 | |
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516 | unsigned32 ppc_exception_vector_addr( |
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517 | unsigned32 vector |
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518 | ) |
---|
519 | { |
---|
520 | #if (!PPC_HAS_EVPR) |
---|
521 | unsigned32 Msr; |
---|
522 | #endif |
---|
523 | unsigned32 Top = 0; |
---|
524 | unsigned32 Offset = 0x000; |
---|
525 | |
---|
526 | #if (PPC_HAS_EXCEPTION_PREFIX) |
---|
527 | _CPU_MSR_Value ( Msr ); |
---|
528 | if ( ( Msr & PPC_MSR_EP) != 0 ) /* Vectors at FFFx_xxxx */ |
---|
529 | Top = 0xfff00000; |
---|
530 | #elif (PPC_HAS_EVPR) |
---|
531 | asm volatile( "mfspr %0,0x3d6" : "=r" (Top)); /* EVPR */ |
---|
532 | Top = Top & 0xffff0000; |
---|
533 | #endif |
---|
534 | |
---|
535 | switch ( vector ) { |
---|
536 | case PPC_IRQ_SYSTEM_RESET: /* on 40x aka PPC_IRQ_CRIT */ |
---|
537 | Offset = 0x00100; |
---|
538 | break; |
---|
539 | case PPC_IRQ_MCHECK: |
---|
540 | Offset = 0x00200; |
---|
541 | break; |
---|
542 | case PPC_IRQ_PROTECT: |
---|
543 | Offset = 0x00300; |
---|
544 | break; |
---|
545 | case PPC_IRQ_ISI: |
---|
546 | Offset = 0x00400; |
---|
547 | break; |
---|
548 | case PPC_IRQ_EXTERNAL: |
---|
549 | Offset = 0x00500; |
---|
550 | break; |
---|
551 | case PPC_IRQ_ALIGNMENT: |
---|
552 | Offset = 0x00600; |
---|
553 | break; |
---|
554 | case PPC_IRQ_PROGRAM: |
---|
555 | Offset = 0x00700; |
---|
556 | break; |
---|
557 | case PPC_IRQ_NOFP: |
---|
558 | Offset = 0x00800; |
---|
559 | break; |
---|
560 | case PPC_IRQ_DECREMENTER: |
---|
561 | Offset = 0x00900; |
---|
562 | break; |
---|
563 | case PPC_IRQ_RESERVED_A: |
---|
564 | Offset = 0x00a00; |
---|
565 | break; |
---|
566 | case PPC_IRQ_RESERVED_B: |
---|
567 | Offset = 0x00b00; |
---|
568 | break; |
---|
569 | case PPC_IRQ_SCALL: |
---|
570 | Offset = 0x00c00; |
---|
571 | break; |
---|
572 | case PPC_IRQ_TRACE: |
---|
573 | Offset = 0x00d00; |
---|
574 | break; |
---|
575 | case PPC_IRQ_FP_ASST: |
---|
576 | Offset = 0x00e00; |
---|
577 | break; |
---|
578 | |
---|
579 | #if defined(ppc403) |
---|
580 | |
---|
581 | /* PPC_IRQ_CRIT is the same vector as PPC_IRQ_RESET |
---|
582 | case PPC_IRQ_CRIT: |
---|
583 | Offset = 0x00100; |
---|
584 | break; |
---|
585 | */ |
---|
586 | case PPC_IRQ_PIT: |
---|
587 | Offset = 0x01000; |
---|
588 | break; |
---|
589 | case PPC_IRQ_FIT: |
---|
590 | Offset = 0x01010; |
---|
591 | break; |
---|
592 | case PPC_IRQ_WATCHDOG: |
---|
593 | Offset = 0x01020; |
---|
594 | break; |
---|
595 | case PPC_IRQ_DEBUG: |
---|
596 | Offset = 0x02000; |
---|
597 | break; |
---|
598 | |
---|
599 | #elif defined(ppc601) |
---|
600 | case PPC_IRQ_TRACE: |
---|
601 | Offset = 0x02000; |
---|
602 | break; |
---|
603 | |
---|
604 | #elif defined(ppc603) |
---|
605 | case PPC_IRQ_TRANS_MISS: |
---|
606 | Offset = 0x1000; |
---|
607 | break; |
---|
608 | case PPC_IRQ_DATA_LOAD: |
---|
609 | Offset = 0x1100; |
---|
610 | break; |
---|
611 | case PPC_IRQ_DATA_STORE: |
---|
612 | Offset = 0x1200; |
---|
613 | break; |
---|
614 | case PPC_IRQ_ADDR_BRK: |
---|
615 | Offset = 0x1300; |
---|
616 | break; |
---|
617 | case PPC_IRQ_SYS_MGT: |
---|
618 | Offset = 0x1400; |
---|
619 | break; |
---|
620 | |
---|
621 | #elif defined(ppc603e) |
---|
622 | case PPC_TLB_INST_MISS: |
---|
623 | Offset = 0x1000; |
---|
624 | break; |
---|
625 | case PPC_TLB_LOAD_MISS: |
---|
626 | Offset = 0x1100; |
---|
627 | break; |
---|
628 | case PPC_TLB_STORE_MISS: |
---|
629 | Offset = 0x1200; |
---|
630 | break; |
---|
631 | case PPC_IRQ_ADDRBRK: |
---|
632 | Offset = 0x1300; |
---|
633 | break; |
---|
634 | case PPC_IRQ_SYS_MGT: |
---|
635 | Offset = 0x1400; |
---|
636 | break; |
---|
637 | |
---|
638 | #elif defined(ppc604) |
---|
639 | case PPC_IRQ_ADDR_BRK: |
---|
640 | Offset = 0x1300; |
---|
641 | break; |
---|
642 | case PPC_IRQ_SYS_MGT: |
---|
643 | Offset = 0x1400; |
---|
644 | break; |
---|
645 | #endif |
---|
646 | |
---|
647 | } |
---|
648 | Top += Offset; |
---|
649 | return Top; |
---|
650 | } |
---|
651 | |
---|