source: rtems/c/src/exec/score/cpu/no_cpu/cpu.h @ 2069773

4.104.114.84.95
Last change on this file since 2069773 was 2069773, checked in by Joel Sherrill <joel.sherrill@…>, on Sep 18, 1996 at 8:47:39 PM

use address object to avoid direct pointer arithmetic

  • Property mode set to 100644
File size: 27.6 KB
Line 
1/*  cpu.h
2 *
3 *  This include file contains information pertaining to the XXX
4 *  processor.
5 *
6 *  COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994.
7 *  On-Line Applications Research Corporation (OAR).
8 *  All rights assigned to U.S. Government, 1994.
9 *
10 *  This material may be reproduced by or for the U.S. Government pursuant
11 *  to the copyright license under the clause at DFARS 252.227-7013.  This
12 *  notice must appear in all copies of this file and its derivatives.
13 *
14 *  $Id$
15 */
16
17#ifndef __CPU_h
18#define __CPU_h
19
20#ifdef __cplusplus
21extern "C" {
22#endif
23
24#include <rtems/score/no_cpu.h>               /* pick up machine definitions */
25#ifndef ASM
26#include <rtems/score/no_cputypes.h>
27#endif
28
29/* conditional compilation parameters */
30
31/*
32 *  Should the calls to _Thread_Enable_dispatch be inlined?
33 *
34 *  If TRUE, then they are inlined.
35 *  If FALSE, then a subroutine call is made.
36 *
37 *  Basically this is an example of the classic trade-off of size
38 *  versus speed.  Inlining the call (TRUE) typically increases the
39 *  size of RTEMS while speeding up the enabling of dispatching.
40 *  [NOTE: In general, the _Thread_Dispatch_disable_level will
41 *  only be 0 or 1 unless you are in an interrupt handler and that
42 *  interrupt handler invokes the executive.]  When not inlined
43 *  something calls _Thread_Enable_dispatch which in turns calls
44 *  _Thread_Dispatch.  If the enable dispatch is inlined, then
45 *  one subroutine call is avoided entirely.]
46 */
47
48#define CPU_INLINE_ENABLE_DISPATCH       FALSE
49
50/*
51 *  Should the body of the search loops in _Thread_queue_Enqueue_priority
52 *  be unrolled one time?  In unrolled each iteration of the loop examines
53 *  two "nodes" on the chain being searched.  Otherwise, only one node
54 *  is examined per iteration.
55 *
56 *  If TRUE, then the loops are unrolled.
57 *  If FALSE, then the loops are not unrolled.
58 *
59 *  The primary factor in making this decision is the cost of disabling
60 *  and enabling interrupts (_ISR_Flash) versus the cost of rest of the
61 *  body of the loop.  On some CPUs, the flash is more expensive than
62 *  one iteration of the loop body.  In this case, it might be desirable
63 *  to unroll the loop.  It is important to note that on some CPUs, this
64 *  code is the longest interrupt disable period in RTEMS.  So it is
65 *  necessary to strike a balance when setting this parameter.
66 */
67
68#define CPU_UNROLL_ENQUEUE_PRIORITY      TRUE
69
70/*
71 *  Does RTEMS manage a dedicated interrupt stack in software?
72 *
73 *  If TRUE, then a stack is allocated in _Interrupt_Manager_initialization.
74 *  If FALSE, nothing is done.
75 *
76 *  If the CPU supports a dedicated interrupt stack in hardware,
77 *  then it is generally the responsibility of the BSP to allocate it
78 *  and set it up.
79 *
80 *  If the CPU does not support a dedicated interrupt stack, then
81 *  the porter has two options: (1) execute interrupts on the
82 *  stack of the interrupted task, and (2) have RTEMS manage a dedicated
83 *  interrupt stack.
84 *
85 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
86 *
87 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
88 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
89 *  possible that both are FALSE for a particular CPU.  Although it
90 *  is unclear what that would imply about the interrupt processing
91 *  procedure on that CPU.
92 */
93
94#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE
95
96/*
97 *  Does this CPU have hardware support for a dedicated interrupt stack?
98 *
99 *  If TRUE, then it must be installed during initialization.
100 *  If FALSE, then no installation is performed.
101 *
102 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
103 *
104 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
105 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
106 *  possible that both are FALSE for a particular CPU.  Although it
107 *  is unclear what that would imply about the interrupt processing
108 *  procedure on that CPU.
109 */
110
111#define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE
112
113/*
114 *  Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
115 *
116 *  If TRUE, then the memory is allocated during initialization.
117 *  If FALSE, then the memory is allocated during initialization.
118 *
119 *  This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE
120 *  or CPU_INSTALL_HARDWARE_INTERRUPT_STACK is TRUE.
121 */
122
123#define CPU_ALLOCATE_INTERRUPT_STACK TRUE
124
125/*
126 *  Does the CPU have hardware floating point?
127 *
128 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
129 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
130 *
131 *  If there is a FP coprocessor such as the i387 or mc68881, then
132 *  the answer is TRUE.
133 *
134 *  The macro name "NO_CPU_HAS_FPU" should be made CPU specific.
135 *  It indicates whether or not this CPU model has FP support.  For
136 *  example, it would be possible to have an i386_nofp CPU model
137 *  which set this to false to indicate that you have an i386 without
138 *  an i387 and wish to leave floating point support out of RTEMS.
139 */
140
141#if ( NO_CPU_HAS_FPU == 1 )
142#define CPU_HARDWARE_FP     TRUE
143#else
144#define CPU_HARDWARE_FP     FALSE
145#endif
146
147/*
148 *  Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
149 *
150 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
151 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
152 *
153 *  So far, the only CPU in which this option has been used is the
154 *  HP PA-RISC.  The HP C compiler and gcc both implicitly use the
155 *  floating point registers to perform integer multiplies.  If
156 *  a function which you would not think utilize the FP unit DOES,
157 *  then one can not easily predict which tasks will use the FP hardware.
158 *  In this case, this option should be TRUE.
159 *
160 *  If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
161 */
162
163#define CPU_ALL_TASKS_ARE_FP     TRUE
164
165/*
166 *  Should the IDLE task have a floating point context?
167 *
168 *  If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
169 *  and it has a floating point context which is switched in and out.
170 *  If FALSE, then the IDLE task does not have a floating point context.
171 *
172 *  Setting this to TRUE negatively impacts the time required to preempt
173 *  the IDLE task from an interrupt because the floating point context
174 *  must be saved as part of the preemption.
175 */
176
177#define CPU_IDLE_TASK_IS_FP      FALSE
178
179/*
180 *  Should the saving of the floating point registers be deferred
181 *  until a context switch is made to another different floating point
182 *  task?
183 *
184 *  If TRUE, then the floating point context will not be stored until
185 *  necessary.  It will remain in the floating point registers and not
186 *  disturned until another floating point task is switched to.
187 *
188 *  If FALSE, then the floating point context is saved when a floating
189 *  point task is switched out and restored when the next floating point
190 *  task is restored.  The state of the floating point registers between
191 *  those two operations is not specified.
192 *
193 *  If the floating point context does NOT have to be saved as part of
194 *  interrupt dispatching, then it should be safe to set this to TRUE.
195 *
196 *  Setting this flag to TRUE results in using a different algorithm
197 *  for deciding when to save and restore the floating point context.
198 *  The deferred FP switch algorithm minimizes the number of times
199 *  the FP context is saved and restored.  The FP context is not saved
200 *  until a context switch is made to another, different FP task.
201 *  Thus in a system with only one FP task, the FP context will never
202 *  be saved or restored.
203 */
204
205#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
206
207/*
208 *  Does this port provide a CPU dependent IDLE task implementation?
209 *
210 *  If TRUE, then the routine _CPU_Thread_Idle_body
211 *  must be provided and is the default IDLE thread body instead of
212 *  _CPU_Thread_Idle_body.
213 *
214 *  If FALSE, then use the generic IDLE thread body if the BSP does
215 *  not provide one.
216 *
217 *  This is intended to allow for supporting processors which have
218 *  a low power or idle mode.  When the IDLE thread is executed, then
219 *  the CPU can be powered down.
220 *
221 *  The order of precedence for selecting the IDLE thread body is:
222 *
223 *    1.  BSP provided
224 *    2.  CPU dependent (if provided)
225 *    3.  generic (if no BSP and no CPU dependent)
226 */
227
228#define CPU_PROVIDES_IDLE_THREAD_BODY    TRUE
229
230/*
231 *  Does the stack grow up (toward higher addresses) or down
232 *  (toward lower addresses)?
233 *
234 *  If TRUE, then the grows upward.
235 *  If FALSE, then the grows toward smaller addresses.
236 */
237
238#define CPU_STACK_GROWS_UP               TRUE
239
240/*
241 *  The following is the variable attribute used to force alignment
242 *  of critical RTEMS structures.  On some processors it may make
243 *  sense to have these aligned on tighter boundaries than
244 *  the minimum requirements of the compiler in order to have as
245 *  much of the critical data area as possible in a cache line.
246 *
247 *  The placement of this macro in the declaration of the variables
248 *  is based on the syntactically requirements of the GNU C
249 *  "__attribute__" extension.  For example with GNU C, use
250 *  the following to force a structures to a 32 byte boundary.
251 *
252 *      __attribute__ ((aligned (32)))
253 *
254 *  NOTE:  Currently only the Priority Bit Map table uses this feature.
255 *         To benefit from using this, the data must be heavily
256 *         used so it will stay in the cache and used frequently enough
257 *         in the executive to justify turning this on.
258 */
259
260#define CPU_STRUCTURE_ALIGNMENT
261
262/*
263 *  The following defines the number of bits actually used in the
264 *  interrupt field of the task mode.  How those bits map to the
265 *  CPU interrupt levels is defined by the routine _CPU_ISR_Set_level().
266 */
267
268#define CPU_MODES_INTERRUPT_MASK   0x00000001
269
270/*
271 *  Processor defined structures
272 *
273 *  Examples structures include the descriptor tables from the i386
274 *  and the processor control structure on the i960ca.
275 */
276
277/* may need to put some structures here.  */
278
279/*
280 * Contexts
281 *
282 *  Generally there are 2 types of context to save.
283 *     1. Interrupt registers to save
284 *     2. Task level registers to save
285 *
286 *  This means we have the following 3 context items:
287 *     1. task level context stuff::  Context_Control
288 *     2. floating point task stuff:: Context_Control_fp
289 *     3. special interrupt level context :: Context_Control_interrupt
290 *
291 *  On some processors, it is cost-effective to save only the callee
292 *  preserved registers during a task context switch.  This means
293 *  that the ISR code needs to save those registers which do not
294 *  persist across function calls.  It is not mandatory to make this
295 *  distinctions between the caller/callee saves registers for the
296 *  purpose of minimizing context saved during task switch and on interrupts.
297 *  If the cost of saving extra registers is minimal, simplicity is the
298 *  choice.  Save the same context on interrupt entry as for tasks in
299 *  this case.
300 *
301 *  Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
302 *  care should be used in designing the context area.
303 *
304 *  On some CPUs with hardware floating point support, the Context_Control_fp
305 *  structure will not be used or it simply consist of an array of a
306 *  fixed number of bytes.   This is done when the floating point context
307 *  is dumped by a "FP save context" type instruction and the format
308 *  is not really defined by the CPU.  In this case, there is no need
309 *  to figure out the exact format -- only the size.  Of course, although
310 *  this is enough information for RTEMS, it is probably not enough for
311 *  a debugger such as gdb.  But that is another problem.
312 */
313
314typedef struct {
315    unsigned32 some_integer_register;
316    unsigned32 some_system_register;
317} Context_Control;
318
319typedef struct {
320    double      some_float_register;
321} Context_Control_fp;
322
323typedef struct {
324    unsigned32 special_interrupt_register;
325} CPU_Interrupt_frame;
326
327
328/*
329 *  The following table contains the information required to configure
330 *  the XXX processor specific parameters.
331 */
332
333typedef struct {
334  void       (*pretasking_hook)( void );
335  void       (*predriver_hook)( void );
336  void       (*postdriver_hook)( void );
337  void       (*idle_task)( void );
338  boolean      do_zero_of_workspace;
339  unsigned32   interrupt_stack_size;
340  unsigned32   extra_mpci_receive_server_stack;
341  void *     (*stack_allocate_hook)( unsigned32 );
342  void       (*stack_free_hook)( void* );
343  /* end of fields required on all CPUs */
344
345  unsigned32   some_other_cpu_dependent_info;
346}   rtems_cpu_table;
347
348/*
349 *  This variable is optional.  It is used on CPUs on which it is difficult
350 *  to generate an "uninitialized" FP context.  It is filled in by
351 *  _CPU_Initialize and copied into the task's FP context area during
352 *  _CPU_Context_Initialize.
353 */
354
355SCORE_EXTERN Context_Control_fp  _CPU_Null_fp_context;
356
357/*
358 *  On some CPUs, RTEMS supports a software managed interrupt stack.
359 *  This stack is allocated by the Interrupt Manager and the switch
360 *  is performed in _ISR_Handler.  These variables contain pointers
361 *  to the lowest and highest addresses in the chunk of memory allocated
362 *  for the interrupt stack.  Since it is unknown whether the stack
363 *  grows up or down (in general), this give the CPU dependent
364 *  code the option of picking the version it wants to use.
365 *
366 *  NOTE: These two variables are required if the macro
367 *        CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
368 */
369
370SCORE_EXTERN void               *_CPU_Interrupt_stack_low;
371SCORE_EXTERN void               *_CPU_Interrupt_stack_high;
372
373/*
374 *  With some compilation systems, it is difficult if not impossible to
375 *  call a high-level language routine from assembly language.  This
376 *  is especially true of commercial Ada compilers and name mangling
377 *  C++ ones.  This variable can be optionally defined by the CPU porter
378 *  and contains the address of the routine _Thread_Dispatch.  This
379 *  can make it easier to invoke that routine at the end of the interrupt
380 *  sequence (if a dispatch is necessary).
381 */
382
383SCORE_EXTERN void           (*_CPU_Thread_dispatch_pointer)();
384
385/*
386 *  Nothing prevents the porter from declaring more CPU specific variables.
387 */
388
389/* XXX: if needed, put more variables here */
390
391/*
392 *  The size of the floating point context area.  On some CPUs this
393 *  will not be a "sizeof" because the format of the floating point
394 *  area is not defined -- only the size is.  This is usually on
395 *  CPUs with a "floating point save context" instruction.
396 */
397
398#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
399
400/*
401 *  Amount of extra stack (above minimum stack size) required by
402 *  MPCI receive server thread.  Remember that in a multiprocessor
403 *  system this thread must exist and be able to process all directives.
404 */
405
406#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
407
408/*
409 *  This defines the number of entries in the ISR_Vector_table managed
410 *  by RTEMS.
411 */
412
413#define CPU_INTERRUPT_NUMBER_OF_VECTORS      32
414#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
415
416/*
417 *  Should be large enough to run all RTEMS tests.  This insures
418 *  that a "reasonable" small application should not have any problems.
419 */
420
421#define CPU_STACK_MINIMUM_SIZE          (1024*4)
422
423/*
424 *  CPU's worst alignment requirement for data types on a byte boundary.  This
425 *  alignment does not take into account the requirements for the stack.
426 */
427
428#define CPU_ALIGNMENT              8
429
430/*
431 *  This number corresponds to the byte alignment requirement for the
432 *  heap handler.  This alignment requirement may be stricter than that
433 *  for the data types alignment specified by CPU_ALIGNMENT.  It is
434 *  common for the heap to follow the same alignment requirement as
435 *  CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict enough for the heap,
436 *  then this should be set to CPU_ALIGNMENT.
437 *
438 *  NOTE:  This does not have to be a power of 2.  It does have to
439 *         be greater or equal to than CPU_ALIGNMENT.
440 */
441
442#define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT
443
444/*
445 *  This number corresponds to the byte alignment requirement for memory
446 *  buffers allocated by the partition manager.  This alignment requirement
447 *  may be stricter than that for the data types alignment specified by
448 *  CPU_ALIGNMENT.  It is common for the partition to follow the same
449 *  alignment requirement as CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict
450 *  enough for the partition, then this should be set to CPU_ALIGNMENT.
451 *
452 *  NOTE:  This does not have to be a power of 2.  It does have to
453 *         be greater or equal to than CPU_ALIGNMENT.
454 */
455
456#define CPU_PARTITION_ALIGNMENT    CPU_ALIGNMENT
457
458/*
459 *  This number corresponds to the byte alignment requirement for the
460 *  stack.  This alignment requirement may be stricter than that for the
461 *  data types alignment specified by CPU_ALIGNMENT.  If the CPU_ALIGNMENT
462 *  is strict enough for the stack, then this should be set to 0.
463 *
464 *  NOTE:  This must be a power of 2 either 0 or greater than CPU_ALIGNMENT.
465 */
466
467#define CPU_STACK_ALIGNMENT        0
468
469/* ISR handler macros */
470
471/*
472 *  Disable all interrupts for an RTEMS critical section.  The previous
473 *  level is returned in _level.
474 */
475
476#define _CPU_ISR_Disable( _isr_cookie ) \
477  { \
478    (_isr_cookie) = 0;   /* do something to prevent warnings */ \
479  }
480
481/*
482 *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
483 *  This indicates the end of an RTEMS critical section.  The parameter
484 *  _level is not modified.
485 */
486
487#define _CPU_ISR_Enable( _isr_cookie )  \
488  { \
489  }
490
491/*
492 *  This temporarily restores the interrupt to _level before immediately
493 *  disabling them again.  This is used to divide long RTEMS critical
494 *  sections into two or more parts.  The parameter _level is not
495 * modified.
496 */
497
498#define _CPU_ISR_Flash( _isr_cookie ) \
499  { \
500  }
501
502/*
503 *  Map interrupt level in task mode onto the hardware that the CPU
504 *  actually provides.  Currently, interrupt levels which do not
505 *  map onto the CPU in a generic fashion are undefined.  Someday,
506 *  it would be nice if these were "mapped" by the application
507 *  via a callout.  For example, m68k has 8 levels 0 - 7, levels
508 *  8 - 255 would be available for bsp/application specific meaning.
509 *  This could be used to manage a programmable interrupt controller
510 *  via the rtems_task_mode directive.
511 */
512
513#define _CPU_ISR_Set_level( new_level ) \
514  { \
515  }
516
517/* end of ISR handler macros */
518
519/* Context handler macros */
520
521/*
522 *  Initialize the context to a state suitable for starting a
523 *  task after a context restore operation.  Generally, this
524 *  involves:
525 *
526 *     - setting a starting address
527 *     - preparing the stack
528 *     - preparing the stack and frame pointers
529 *     - setting the proper interrupt level in the context
530 *     - initializing the floating point context
531 *
532 *  This routine generally does not set any unnecessary register
533 *  in the context.  The state of the "general data" registers is
534 *  undefined at task start time.
535 *
536 *  NOTE: This is_fp parameter is TRUE if the thread is to be a floating
537 *        point thread.  This is typically only used on CPUs where the
538 *        FPU may be easily disabled by software such as on the SPARC
539 *        where the PSR contains an enable FPU bit.
540 */
541
542#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
543                                 _isr, _entry_point, _is_fp ) \
544  { \
545  }
546
547/*
548 *  This routine is responsible for somehow restarting the currently
549 *  executing task.  If you are lucky, then all that is necessary
550 *  is restoring the context.  Otherwise, there will need to be
551 *  a special assembly routine which does something special in this
552 *  case.  Context_Restore should work most of the time.  It will
553 *  not work if restarting self conflicts with the stack frame
554 *  assumptions of restoring a context.
555 */
556
557#define _CPU_Context_Restart_self( _the_context ) \
558   _CPU_Context_restore( (_the_context) );
559
560/*
561 *  The purpose of this macro is to allow the initial pointer into
562 *  a floating point context area (used to save the floating point
563 *  context) to be at an arbitrary place in the floating point
564 *  context area.
565 *
566 *  This is necessary because some FP units are designed to have
567 *  their context saved as a stack which grows into lower addresses.
568 *  Other FP units can be saved by simply moving registers into offsets
569 *  from the base of the context area.  Finally some FP units provide
570 *  a "dump context" instruction which could fill in from high to low
571 *  or low to high based on the whim of the CPU designers.
572 */
573
574#define _CPU_Context_Fp_start( _base, _offset ) \
575   ( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
576
577/*
578 *  This routine initializes the FP context area passed to it to.
579 *  There are a few standard ways in which to initialize the
580 *  floating point context.  The code included for this macro assumes
581 *  that this is a CPU in which a "initial" FP context was saved into
582 *  _CPU_Null_fp_context and it simply copies it to the destination
583 *  context passed to it.
584 *
585 *  Other models include (1) not doing anything, and (2) putting
586 *  a "null FP status word" in the correct place in the FP context.
587 */
588
589#define _CPU_Context_Initialize_fp( _destination ) \
590  { \
591   *((Context_Control_fp *) *((void **) _destination)) = _CPU_Null_fp_context; \
592  }
593
594/* end of Context handler macros */
595
596/* Fatal Error manager macros */
597
598/*
599 *  This routine copies _error into a known place -- typically a stack
600 *  location or a register, optionally disables interrupts, and
601 *  halts/stops the CPU.
602 */
603
604#define _CPU_Fatal_halt( _error ) \
605  { \
606  }
607
608/* end of Fatal Error manager macros */
609
610/* Bitfield handler macros */
611
612/*
613 *  This routine sets _output to the bit number of the first bit
614 *  set in _value.  _value is of CPU dependent type Priority_Bit_map_control.
615 *  This type may be either 16 or 32 bits wide although only the 16
616 *  least significant bits will be used.
617 *
618 *  There are a number of variables in using a "find first bit" type
619 *  instruction.
620 *
621 *    (1) What happens when run on a value of zero?
622 *    (2) Bits may be numbered from MSB to LSB or vice-versa.
623 *    (3) The numbering may be zero or one based.
624 *    (4) The "find first bit" instruction may search from MSB or LSB.
625 *
626 *  RTEMS guarantees that (1) will never happen so it is not a concern.
627 *  (2),(3), (4) are handled by the macros _CPU_Priority_mask() and
628 *  _CPU_Priority_bits_index().  These three form a set of routines
629 *  which must logically operate together.  Bits in the _value are
630 *  set and cleared based on masks built by _CPU_Priority_mask().
631 *  The basic major and minor values calculated by _Priority_Major()
632 *  and _Priority_Minor() are "massaged" by _CPU_Priority_bits_index()
633 *  to properly range between the values returned by the "find first bit"
634 *  instruction.  This makes it possible for _Priority_Get_highest() to
635 *  calculate the major and directly index into the minor table.
636 *  This mapping is necessary to ensure that 0 (a high priority major/minor)
637 *  is the first bit found.
638 *
639 *  This entire "find first bit" and mapping process depends heavily
640 *  on the manner in which a priority is broken into a major and minor
641 *  components with the major being the 4 MSB of a priority and minor
642 *  the 4 LSB.  Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
643 *  priority.  And (15 << 4) + 14 corresponds to priority 254 -- the next
644 *  to the lowest priority.
645 *
646 *  If your CPU does not have a "find first bit" instruction, then
647 *  there are ways to make do without it.  Here are a handful of ways
648 *  to implement this in software:
649 *
650 *    - a series of 16 bit test instructions
651 *    - a "binary search using if's"
652 *    - _number = 0
653 *      if _value > 0x00ff
654 *        _value >>=8
655 *        _number = 8;
656 *
657 *      if _value > 0x0000f
658 *        _value >=8
659 *        _number += 4
660 *
661 *      _number += bit_set_table[ _value ]
662 *
663 *    where bit_set_table[ 16 ] has values which indicate the first
664 *      bit set
665 */
666
667#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
668#define CPU_USE_GENERIC_BITFIELD_DATA TRUE
669
670#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
671
672#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
673  { \
674    (_output) = 0;   /* do something to prevent warnings */ \
675  }
676
677#endif
678
679/* end of Bitfield handler macros */
680
681/*
682 *  This routine builds the mask which corresponds to the bit fields
683 *  as searched by _CPU_Bitfield_Find_first_bit().  See the discussion
684 *  for that routine.
685 */
686
687#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
688
689#define _CPU_Priority_Mask( _bit_number ) \
690  ( 1 << (_bit_number) )
691
692#endif
693
694/*
695 *  This routine translates the bit numbers returned by
696 *  _CPU_Bitfield_Find_first_bit() into something suitable for use as
697 *  a major or minor component of a priority.  See the discussion
698 *  for that routine.
699 */
700
701#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
702
703#define _CPU_Priority_bits_index( _priority ) \
704  (_priority)
705
706#endif
707
708/* end of Priority handler macros */
709
710/* functions */
711
712/*
713 *  _CPU_Initialize
714 *
715 *  This routine performs CPU dependent initialization.
716 */
717
718void _CPU_Initialize(
719  rtems_cpu_table  *cpu_table,
720  void      (*thread_dispatch)
721);
722
723/*
724 *  _CPU_ISR_install_raw_handler
725 *
726 *  This routine installs a "raw" interrupt handler directly into the
727 *  processor's vector table.
728 */
729 
730void _CPU_ISR_install_raw_handler(
731  unsigned32  vector,
732  proc_ptr    new_handler,
733  proc_ptr   *old_handler
734);
735
736/*
737 *  _CPU_ISR_install_vector
738 *
739 *  This routine installs an interrupt vector.
740 */
741
742void _CPU_ISR_install_vector(
743  unsigned32  vector,
744  proc_ptr    new_handler,
745  proc_ptr   *old_handler
746);
747
748/*
749 *  _CPU_Install_interrupt_stack
750 *
751 *  This routine installs the hardware interrupt stack pointer.
752 *
753 *  NOTE:  It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK
754 *         is TRUE.
755 */
756
757void _CPU_Install_interrupt_stack( void );
758
759/*
760 *  _CPU_Thread_Idle_body
761 *
762 *  This routine is the CPU dependent IDLE thread body.
763 *
764 *  NOTE:  It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY
765 *         is TRUE.
766 */
767
768void _CPU_Thread_Idle_body( void );
769
770/*
771 *  _CPU_Context_switch
772 *
773 *  This routine switches from the run context to the heir context.
774 */
775
776void _CPU_Context_switch(
777  Context_Control  *run,
778  Context_Control  *heir
779);
780
781/*
782 *  _CPU_Context_restore
783 *
784 *  This routine is generallu used only to restart self in an
785 *  efficient manner.  It may simply be a label in _CPU_Context_switch.
786 *
787 *  NOTE: May be unnecessary to reload some registers.
788 */
789
790void _CPU_Context_restore(
791  Context_Control *new_context
792);
793
794/*
795 *  _CPU_Context_save_fp
796 *
797 *  This routine saves the floating point context passed to it.
798 */
799
800void _CPU_Context_save_fp(
801  void **fp_context_ptr
802);
803
804/*
805 *  _CPU_Context_restore_fp
806 *
807 *  This routine restores the floating point context passed to it.
808 */
809
810void _CPU_Context_restore_fp(
811  void **fp_context_ptr
812);
813
814/*  The following routine swaps the endian format of an unsigned int.
815 *  It must be static because it is referenced indirectly.
816 *
817 *  This version will work on any processor, but if there is a better
818 *  way for your CPU PLEASE use it.  The most common way to do this is to:
819 *
820 *     swap least significant two bytes with 16-bit rotate
821 *     swap upper and lower 16-bits
822 *     swap most significant two bytes with 16-bit rotate
823 *
824 *  Some CPUs have special instructions which swap a 32-bit quantity in
825 *  a single instruction (e.g. i486).  It is probably best to avoid
826 *  an "endian swapping control bit" in the CPU.  One good reason is
827 *  that interrupts would probably have to be disabled to insure that
828 *  an interrupt does not try to access the same "chunk" with the wrong
829 *  endian.  Another good reason is that on some CPUs, the endian bit
830 *  endianness for ALL fetches -- both code and data -- so the code
831 *  will be fetched incorrectly.
832 */
833 
834static inline unsigned int CPU_swap_u32(
835  unsigned int value
836)
837{
838  unsigned32 byte1, byte2, byte3, byte4, swapped;
839 
840  byte4 = (value >> 24) & 0xff;
841  byte3 = (value >> 16) & 0xff;
842  byte2 = (value >> 8)  & 0xff;
843  byte1 =  value        & 0xff;
844 
845  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
846  return( swapped );
847}
848
849#ifdef __cplusplus
850}
851#endif
852
853#endif
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