source: rtems/c/src/exec/score/cpu/mips64orion/cpu.h @ 375a6c0

4.104.114.84.95
Last change on this file since 375a6c0 was 375a6c0, checked in by Joel Sherrill <joel.sherrill@…>, on Jan 29, 1997 at 12:10:28 AM

Fixed spacing on comment.

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1/*  cpu.h
2 *
3 *  This include file contains information pertaining to the IDT 4650
4 *  processor.
5 *
6 *  Author:     Craig Lebakken <craigl@transition.com>
7 *
8 *  COPYRIGHT (c) 1996 by Transition Networks Inc.
9 *
10 *  To anyone who acknowledges that this file is provided "AS IS"
11 *  without any express or implied warranty:
12 *      permission to use, copy, modify, and distribute this file
13 *      for any purpose is hereby granted without fee, provided that
14 *      the above copyright notice and this notice appears in all
15 *      copies, and that the name of Transition Networks not be used in
16 *      advertising or publicity pertaining to distribution of the
17 *      software without specific, written prior permission.
18 *      Transition Networks makes no representations about the suitability
19 *      of this software for any purpose.
20 *
21 *  Derived from c/src/exec/score/cpu/no_cpu/cpu.h:
22 *
23 *  COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994.
24 *  On-Line Applications Research Corporation (OAR).
25 *  All rights assigned to U.S. Government, 1994.
26 *
27 *  This material may be reproduced by or for the U.S. Government pursuant
28 *  to the copyright license under the clause at DFARS 252.227-7013.  This
29 *  notice must appear in all copies of this file and its derivatives.
30 *
31 *  $Id$
32 */
33/* @(#)cpu.h       08/29/96     1.7 */
34
35#ifndef __CPU_h
36#define __CPU_h
37
38#ifdef __cplusplus
39extern "C" {
40#endif
41
42#include <rtems/score/mips64orion.h>       /* pick up machine definitions */
43#ifndef ASM
44#include <rtems/score/mipstypes.h>
45#endif
46
47extern int mips_disable_interrupts( void );
48extern void mips_enable_interrupts( int _level );
49extern int mips_disable_global_interrupts( void );
50extern void mips_enable_global_interrupts( void );
51extern void mips_fatal_error ( int error );
52
53/* conditional compilation parameters */
54
55/*
56 *  Should the calls to _Thread_Enable_dispatch be inlined?
57 *
58 *  If TRUE, then they are inlined.
59 *  If FALSE, then a subroutine call is made.
60 *
61 *  Basically this is an example of the classic trade-off of size
62 *  versus speed.  Inlining the call (TRUE) typically increases the
63 *  size of RTEMS while speeding up the enabling of dispatching.
64 *  [NOTE: In general, the _Thread_Dispatch_disable_level will
65 *  only be 0 or 1 unless you are in an interrupt handler and that
66 *  interrupt handler invokes the executive.]  When not inlined
67 *  something calls _Thread_Enable_dispatch which in turns calls
68 *  _Thread_Dispatch.  If the enable dispatch is inlined, then
69 *  one subroutine call is avoided entirely.]
70 */
71
72#define CPU_INLINE_ENABLE_DISPATCH       TRUE
73
74/*
75 *  Should the body of the search loops in _Thread_queue_Enqueue_priority
76 *  be unrolled one time?  In unrolled each iteration of the loop examines
77 *  two "nodes" on the chain being searched.  Otherwise, only one node
78 *  is examined per iteration.
79 *
80 *  If TRUE, then the loops are unrolled.
81 *  If FALSE, then the loops are not unrolled.
82 *
83 *  The primary factor in making this decision is the cost of disabling
84 *  and enabling interrupts (_ISR_Flash) versus the cost of rest of the
85 *  body of the loop.  On some CPUs, the flash is more expensive than
86 *  one iteration of the loop body.  In this case, it might be desirable
87 *  to unroll the loop.  It is important to note that on some CPUs, this
88 *  code is the longest interrupt disable period in RTEMS.  So it is
89 *  necessary to strike a balance when setting this parameter.
90 */
91
92#define CPU_UNROLL_ENQUEUE_PRIORITY      TRUE
93
94/*
95 *  Does RTEMS manage a dedicated interrupt stack in software?
96 *
97 *  If TRUE, then a stack is allocated in _Interrupt_Manager_initialization.
98 *  If FALSE, nothing is done.
99 *
100 *  If the CPU supports a dedicated interrupt stack in hardware,
101 *  then it is generally the responsibility of the BSP to allocate it
102 *  and set it up.
103 *
104 *  If the CPU does not support a dedicated interrupt stack, then
105 *  the porter has two options: (1) execute interrupts on the
106 *  stack of the interrupted task, and (2) have RTEMS manage a dedicated
107 *  interrupt stack.
108 *
109 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
110 *
111 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
112 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
113 *  possible that both are FALSE for a particular CPU.  Although it
114 *  is unclear what that would imply about the interrupt processing
115 *  procedure on that CPU.
116 */
117
118#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE
119
120/*
121 *  Does this CPU have hardware support for a dedicated interrupt stack?
122 *
123 *  If TRUE, then it must be installed during initialization.
124 *  If FALSE, then no installation is performed.
125 *
126 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
127 *
128 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
129 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
130 *  possible that both are FALSE for a particular CPU.  Although it
131 *  is unclear what that would imply about the interrupt processing
132 *  procedure on that CPU.
133 */
134
135#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
136
137/*
138 *  Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
139 *
140 *  If TRUE, then the memory is allocated during initialization.
141 *  If FALSE, then the memory is allocated during initialization.
142 *
143 *  This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE
144 *  or CPU_INSTALL_HARDWARE_INTERRUPT_STACK is TRUE.
145 */
146
147#define CPU_ALLOCATE_INTERRUPT_STACK FALSE
148
149/*
150 *  Does the CPU have hardware floating point?
151 *
152 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
153 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
154 *
155 *  If there is a FP coprocessor such as the i387 or mc68881, then
156 *  the answer is TRUE.
157 *
158 *  The macro name "MIPS64ORION_HAS_FPU" should be made CPU specific.
159 *  It indicates whether or not this CPU model has FP support.  For
160 *  example, it would be possible to have an i386_nofp CPU model
161 *  which set this to false to indicate that you have an i386 without
162 *  an i387 and wish to leave floating point support out of RTEMS.
163 */
164
165#if ( MIPS64ORION_HAS_FPU == 1 )
166#define CPU_HARDWARE_FP     TRUE
167#else
168#define CPU_HARDWARE_FP     FALSE
169#endif
170
171/*
172 *  Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
173 *
174 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
175 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
176 *
177 *  So far, the only CPU in which this option has been used is the
178 *  HP PA-RISC.  The HP C compiler and gcc both implicitly use the
179 *  floating point registers to perform integer multiplies.  If
180 *  a function which you would not think utilize the FP unit DOES,
181 *  then one can not easily predict which tasks will use the FP hardware.
182 *  In this case, this option should be TRUE.
183 *
184 *  If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
185 */
186
187#define CPU_ALL_TASKS_ARE_FP    FALSE
188
189/*
190 *  Should the IDLE task have a floating point context?
191 *
192 *  If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
193 *  and it has a floating point context which is switched in and out.
194 *  If FALSE, then the IDLE task does not have a floating point context.
195 *
196 *  Setting this to TRUE negatively impacts the time required to preempt
197 *  the IDLE task from an interrupt because the floating point context
198 *  must be saved as part of the preemption.
199 */
200
201#define CPU_IDLE_TASK_IS_FP      FALSE
202
203/*
204 *  Should the saving of the floating point registers be deferred
205 *  until a context switch is made to another different floating point
206 *  task?
207 *
208 *  If TRUE, then the floating point context will not be stored until
209 *  necessary.  It will remain in the floating point registers and not
210 *  disturned until another floating point task is switched to.
211 *
212 *  If FALSE, then the floating point context is saved when a floating
213 *  point task is switched out and restored when the next floating point
214 *  task is restored.  The state of the floating point registers between
215 *  those two operations is not specified.
216 *
217 *  If the floating point context does NOT have to be saved as part of
218 *  interrupt dispatching, then it should be safe to set this to TRUE.
219 *
220 *  Setting this flag to TRUE results in using a different algorithm
221 *  for deciding when to save and restore the floating point context.
222 *  The deferred FP switch algorithm minimizes the number of times
223 *  the FP context is saved and restored.  The FP context is not saved
224 *  until a context switch is made to another, different FP task.
225 *  Thus in a system with only one FP task, the FP context will never
226 *  be saved or restored.
227 */
228
229#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
230
231/*
232 *  Does this port provide a CPU dependent IDLE task implementation?
233 *
234 *  If TRUE, then the routine _CPU_Internal_threads_Idle_thread_body
235 *  must be provided and is the default IDLE thread body instead of
236 *  _Internal_threads_Idle_thread_body.
237 *
238 *  If FALSE, then use the generic IDLE thread body if the BSP does
239 *  not provide one.
240 *
241 *  This is intended to allow for supporting processors which have
242 *  a low power or idle mode.  When the IDLE thread is executed, then
243 *  the CPU can be powered down.
244 *
245 *  The order of precedence for selecting the IDLE thread body is:
246 *
247 *    1.  BSP provided
248 *    2.  CPU dependent (if provided)
249 *    3.  generic (if no BSP and no CPU dependent)
250 */
251
252/* we can use the low power wait instruction for the IDLE thread */
253#define CPU_PROVIDES_IDLE_THREAD_BODY    TRUE
254
255/*
256 *  Does the stack grow up (toward higher addresses) or down
257 *  (toward lower addresses)?
258 *
259 *  If TRUE, then the grows upward.
260 *  If FALSE, then the grows toward smaller addresses.
261 */
262
263/* our stack grows down */
264#define CPU_STACK_GROWS_UP               FALSE
265
266/*
267 *  The following is the variable attribute used to force alignment
268 *  of critical RTEMS structures.  On some processors it may make
269 *  sense to have these aligned on tighter boundaries than
270 *  the minimum requirements of the compiler in order to have as
271 *  much of the critical data area as possible in a cache line.
272 *
273 *  The placement of this macro in the declaration of the variables
274 *  is based on the syntactically requirements of the GNU C
275 *  "__attribute__" extension.  For example with GNU C, use
276 *  the following to force a structures to a 32 byte boundary.
277 *
278 *      __attribute__ ((aligned (32)))
279 *
280 *  NOTE:  Currently only the Priority Bit Map table uses this feature.
281 *         To benefit from using this, the data must be heavily
282 *         used so it will stay in the cache and used frequently enough
283 *         in the executive to justify turning this on.
284 */
285
286/* our cache line size is 16 bytes */
287#if __GNUC__
288#define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned (16)))
289#else
290#define CPU_STRUCTURE_ALIGNMENT
291#endif
292
293/*
294 *  The following defines the number of bits actually used in the
295 *  interrupt field of the task mode.  How those bits map to the
296 *  CPU interrupt levels is defined by the routine _CPU_ISR_Set_level().
297 */
298
299#define CPU_MODES_INTERRUPT_MASK   0x00000001
300
301/*
302 *  Processor defined structures
303 *
304 *  Examples structures include the descriptor tables from the i386
305 *  and the processor control structure on the i960ca.
306 */
307
308/* may need to put some structures here.  */
309
310/*
311 * Contexts
312 *
313 *  Generally there are 2 types of context to save.
314 *     1. Interrupt registers to save
315 *     2. Task level registers to save
316 *
317 *  This means we have the following 3 context items:
318 *     1. task level context stuff::  Context_Control
319 *     2. floating point task stuff:: Context_Control_fp
320 *     3. special interrupt level context :: Context_Control_interrupt
321 *
322 *  On some processors, it is cost-effective to save only the callee
323 *  preserved registers during a task context switch.  This means
324 *  that the ISR code needs to save those registers which do not
325 *  persist across function calls.  It is not mandatory to make this
326 *  distinctions between the caller/callee saves registers for the
327 *  purpose of minimizing context saved during task switch and on interrupts.
328 *  If the cost of saving extra registers is minimal, simplicity is the
329 *  choice.  Save the same context on interrupt entry as for tasks in
330 *  this case.
331 *
332 *  Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
333 *  care should be used in designing the context area.
334 *
335 *  On some CPUs with hardware floating point support, the Context_Control_fp
336 *  structure will not be used or it simply consist of an array of a
337 *  fixed number of bytes.   This is done when the floating point context
338 *  is dumped by a "FP save context" type instruction and the format
339 *  is not really defined by the CPU.  In this case, there is no need
340 *  to figure out the exact format -- only the size.  Of course, although
341 *  this is enough information for RTEMS, it is probably not enough for
342 *  a debugger such as gdb.  But that is another problem.
343 */
344
345/* WARNING: If this structure is modified, the constants in cpu.h must be updated. */
346typedef struct {
347    unsigned64 s0;
348    unsigned64 s1;
349    unsigned64 s2;
350    unsigned64 s3;
351    unsigned64 s4;
352    unsigned64 s5;
353    unsigned64 s6;
354    unsigned64 s7;
355    unsigned64 sp;
356    unsigned64 fp;
357    unsigned64 ra;
358    unsigned64 c0_sr;
359    unsigned64 c0_epc;
360} Context_Control;
361
362/* WARNING: If this structure is modified, the constants in cpu.h must be updated. */
363typedef struct {
364    unsigned32      fp0;
365    unsigned32      fp1;
366    unsigned32      fp2;
367    unsigned32      fp3;
368    unsigned32      fp4;
369    unsigned32      fp5;
370    unsigned32      fp6;
371    unsigned32      fp7;
372    unsigned32      fp8;
373    unsigned32      fp9;
374    unsigned32      fp10;
375    unsigned32      fp11;
376    unsigned32      fp12;
377    unsigned32      fp13;
378    unsigned32      fp14;
379    unsigned32      fp15;
380    unsigned32      fp16;
381    unsigned32      fp17;
382    unsigned32      fp18;
383    unsigned32      fp19;
384    unsigned32      fp20;
385    unsigned32      fp21;
386    unsigned32      fp22;
387    unsigned32      fp23;
388    unsigned32      fp24;
389    unsigned32      fp25;
390    unsigned32      fp26;
391    unsigned32      fp27;
392    unsigned32      fp28;
393    unsigned32      fp29;
394    unsigned32      fp30;
395    unsigned32      fp31;
396} Context_Control_fp;
397
398typedef struct {
399    unsigned32 special_interrupt_register;
400} CPU_Interrupt_frame;
401
402
403/*
404 *  The following table contains the information required to configure
405 *  the mips processor specific parameters.
406 */
407
408typedef struct {
409  void       (*pretasking_hook)( void );
410  void       (*predriver_hook)( void );
411  void       (*postdriver_hook)( void );
412  void       (*idle_task)( void );
413  boolean      do_zero_of_workspace;
414  unsigned32   interrupt_stack_size;
415  unsigned32   extra_mpci_receive_server_stack;
416  void *     (*stack_allocate_hook)( unsigned32 );
417  void       (*stack_free_hook)( void* );
418  /* end of fields required on all CPUs */
419
420  unsigned32   some_other_cpu_dependent_info;
421}   rtems_cpu_table;
422
423/*
424 *  This variable is optional.  It is used on CPUs on which it is difficult
425 *  to generate an "uninitialized" FP context.  It is filled in by
426 *  _CPU_Initialize and copied into the task's FP context area during
427 *  _CPU_Context_Initialize.
428 */
429
430SCORE_EXTERN Context_Control_fp  _CPU_Null_fp_context;
431
432/*
433 *  On some CPUs, RTEMS supports a software managed interrupt stack.
434 *  This stack is allocated by the Interrupt Manager and the switch
435 *  is performed in _ISR_Handler.  These variables contain pointers
436 *  to the lowest and highest addresses in the chunk of memory allocated
437 *  for the interrupt stack.  Since it is unknown whether the stack
438 *  grows up or down (in general), this give the CPU dependent
439 *  code the option of picking the version it wants to use.
440 *
441 *  NOTE: These two variables are required if the macro
442 *        CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
443 */
444
445SCORE_EXTERN void               *_CPU_Interrupt_stack_low;
446SCORE_EXTERN void               *_CPU_Interrupt_stack_high;
447
448/*
449 *  With some compilation systems, it is difficult if not impossible to
450 *  call a high-level language routine from assembly language.  This
451 *  is especially true of commercial Ada compilers and name mangling
452 *  C++ ones.  This variable can be optionally defined by the CPU porter
453 *  and contains the address of the routine _Thread_Dispatch.  This
454 *  can make it easier to invoke that routine at the end of the interrupt
455 *  sequence (if a dispatch is necessary).
456 */
457
458SCORE_EXTERN void           (*_CPU_Thread_dispatch_pointer)();
459
460/*
461 *  Nothing prevents the porter from declaring more CPU specific variables.
462 */
463
464/* XXX: if needed, put more variables here */
465
466/*
467 *  The size of the floating point context area.  On some CPUs this
468 *  will not be a "sizeof" because the format of the floating point
469 *  area is not defined -- only the size is.  This is usually on
470 *  CPUs with a "floating point save context" instruction.
471 */
472
473#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
474
475/*
476 *  Amount of extra stack (above minimum stack size) required by
477 *  system initialization thread.  Remember that in a multiprocessor
478 *  system the system intialization thread becomes the MP server thread.
479 */
480
481#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
482
483/*
484 *  This defines the number of entries in the ISR_Vector_table managed
485 *  by RTEMS.
486 */
487
488#define CPU_INTERRUPT_NUMBER_OF_VECTORS      8
489#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
490
491/*
492 *  Should be large enough to run all RTEMS tests.  This insures
493 *  that a "reasonable" small application should not have any problems.
494 */
495
496#define CPU_STACK_MINIMUM_SIZE          (2048*sizeof(unsigned32))
497
498/*
499 *  CPU's worst alignment requirement for data types on a byte boundary.  This
500 *  alignment does not take into account the requirements for the stack.
501 */
502
503#define CPU_ALIGNMENT              8
504
505/*
506 *  This number corresponds to the byte alignment requirement for the
507 *  heap handler.  This alignment requirement may be stricter than that
508 *  for the data types alignment specified by CPU_ALIGNMENT.  It is
509 *  common for the heap to follow the same alignment requirement as
510 *  CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict enough for the heap,
511 *  then this should be set to CPU_ALIGNMENT.
512 *
513 *  NOTE:  This does not have to be a power of 2.  It does have to
514 *         be greater or equal to than CPU_ALIGNMENT.
515 */
516
517#define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT
518
519/*
520 *  This number corresponds to the byte alignment requirement for memory
521 *  buffers allocated by the partition manager.  This alignment requirement
522 *  may be stricter than that for the data types alignment specified by
523 *  CPU_ALIGNMENT.  It is common for the partition to follow the same
524 *  alignment requirement as CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict
525 *  enough for the partition, then this should be set to CPU_ALIGNMENT.
526 *
527 *  NOTE:  This does not have to be a power of 2.  It does have to
528 *         be greater or equal to than CPU_ALIGNMENT.
529 */
530
531#define CPU_PARTITION_ALIGNMENT    CPU_ALIGNMENT
532
533/*
534 *  This number corresponds to the byte alignment requirement for the
535 *  stack.  This alignment requirement may be stricter than that for the
536 *  data types alignment specified by CPU_ALIGNMENT.  If the CPU_ALIGNMENT
537 *  is strict enough for the stack, then this should be set to 0.
538 *
539 *  NOTE:  This must be a power of 2 either 0 or greater than CPU_ALIGNMENT.
540 */
541
542#define CPU_STACK_ALIGNMENT        CPU_ALIGNMENT
543
544/* ISR handler macros */
545
546/*
547 *  Disable all interrupts for an RTEMS critical section.  The previous
548 *  level is returned in _level.
549 */
550
551#define _CPU_ISR_Disable( _int_level ) \
552  do{ \
553        _int_level = mips_disable_interrupts(); \
554  }while(0)
555
556/*
557 *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
558 *  This indicates the end of an RTEMS critical section.  The parameter
559 *  _level is not modified.
560 */
561
562#define _CPU_ISR_Enable( _level )  \
563  do{ \
564        mips_enable_interrupts(_level); \
565  }while(0)
566
567/*
568 *  This temporarily restores the interrupt to _level before immediately
569 *  disabling them again.  This is used to divide long RTEMS critical
570 *  sections into two or more parts.  The parameter _level is not
571 * modified.
572 */
573
574#define _CPU_ISR_Flash( _xlevel ) \
575  do{ \
576        int _scratch; \
577        _CPU_ISR_Enable( _xlevel ); \
578        _CPU_ISR_Disable( _scratch ); \
579  }while(0)
580
581/*
582 *  Map interrupt level in task mode onto the hardware that the CPU
583 *  actually provides.  Currently, interrupt levels which do not
584 *  map onto the CPU in a generic fashion are undefined.  Someday,
585 *  it would be nice if these were "mapped" by the application
586 *  via a callout.  For example, m68k has 8 levels 0 - 7, levels
587 *  8 - 255 would be available for bsp/application specific meaning.
588 *  This could be used to manage a programmable interrupt controller
589 *  via the rtems_task_mode directive.
590 */
591extern void _CPU_ISR_Set_level( unsigned32 _new_level );
592
593unsigned32 _CPU_ISR_Get_level( void );
594
595/* end of ISR handler macros */
596
597/* Context handler macros */
598
599/*
600 *  Initialize the context to a state suitable for starting a
601 *  task after a context restore operation.  Generally, this
602 *  involves:
603 *
604 *     - setting a starting address
605 *     - preparing the stack
606 *     - preparing the stack and frame pointers
607 *     - setting the proper interrupt level in the context
608 *     - initializing the floating point context
609 *
610 *  This routine generally does not set any unnecessary register
611 *  in the context.  The state of the "general data" registers is
612 *  undefined at task start time.
613 *
614 *  NOTE: This is_fp parameter is TRUE if the thread is to be a floating
615 *        point thread.  This is typically only used on CPUs where the
616 *        FPU may be easily disabled by software such as on the SPARC
617 *        where the PSR contains an enable FPU bit.
618 */
619
620#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
621                                 _isr, _entry_point, _is_fp ) \
622  { \
623        unsigned32 _stack_tmp = (unsigned32)(_stack_base) + (_size) - CPU_STACK_ALIGNMENT; \
624        _stack_tmp &= ~(CPU_STACK_ALIGNMENT - 1); \
625        (_the_context)->sp = _stack_tmp; \
626        (_the_context)->fp = _stack_tmp; \
627        (_the_context)->ra = (unsigned64)_entry_point; \
628        (_the_context)->c0_sr = 0; \
629  }
630
631/*
632 *  This routine is responsible for somehow restarting the currently
633 *  executing task.  If you are lucky, then all that is necessary
634 *  is restoring the context.  Otherwise, there will need to be
635 *  a special assembly routine which does something special in this
636 *  case.  Context_Restore should work most of the time.  It will
637 *  not work if restarting self conflicts with the stack frame
638 *  assumptions of restoring a context.
639 */
640
641#define _CPU_Context_Restart_self( _the_context ) \
642   _CPU_Context_restore( (_the_context) );
643
644/*
645 *  The purpose of this macro is to allow the initial pointer into
646 *  A floating point context area (used to save the floating point
647 *  context) to be at an arbitrary place in the floating point
648 *  context area.
649 *
650 *  This is necessary because some FP units are designed to have
651 *  their context saved as a stack which grows into lower addresses.
652 *  Other FP units can be saved by simply moving registers into offsets
653 *  from the base of the context area.  Finally some FP units provide
654 *  a "dump context" instruction which could fill in from high to low
655 *  or low to high based on the whim of the CPU designers.
656 */
657
658#define _CPU_Context_Fp_start( _base, _offset ) \
659   ( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
660
661/*
662 *  This routine initializes the FP context area passed to it to.
663 *  There are a few standard ways in which to initialize the
664 *  floating point context.  The code included for this macro assumes
665 *  that this is a CPU in which a "initial" FP context was saved into
666 *  _CPU_Null_fp_context and it simply copies it to the destination
667 *  context passed to it.
668 *
669 *  Other models include (1) not doing anything, and (2) putting
670 *  a "null FP status word" in the correct place in the FP context.
671 */
672
673#define _CPU_Context_Initialize_fp( _destination ) \
674  { \
675   *((Context_Control_fp *) *((void **) _destination)) = _CPU_Null_fp_context; \
676  }
677
678/* end of Context handler macros */
679
680/* Fatal Error manager macros */
681
682/*
683 *  This routine copies _error into a known place -- typically a stack
684 *  location or a register, optionally disables interrupts, and
685 *  halts/stops the CPU.
686 */
687
688#define _CPU_Fatal_halt( _error ) \
689  { \
690    mips_disable_global_interrupts(); \
691    mips_fatal_error(_error); \
692  }
693
694/* end of Fatal Error manager macros */
695
696/* Bitfield handler macros */
697
698/*
699 *  This routine sets _output to the bit number of the first bit
700 *  set in _value.  _value is of CPU dependent type Priority_Bit_map_control.
701 *  This type may be either 16 or 32 bits wide although only the 16
702 *  least significant bits will be used.
703 *
704 *  There are a number of variables in using a "find first bit" type
705 *  instruction.
706 *
707 *    (1) What happens when run on a value of zero?
708 *    (2) Bits may be numbered from MSB to LSB or vice-versa.
709 *    (3) The numbering may be zero or one based.
710 *    (4) The "find first bit" instruction may search from MSB or LSB.
711 *
712 *  RTEMS guarantees that (1) will never happen so it is not a concern.
713 *  (2),(3), (4) are handled by the macros _CPU_Priority_mask() and
714 *  _CPU_Priority_bits_index().  These three form a set of routines
715 *  which must logically operate together.  Bits in the _value are
716 *  set and cleared based on masks built by _CPU_Priority_mask().
717 *  The basic major and minor values calculated by _Priority_Major()
718 *  and _Priority_Minor() are "massaged" by _CPU_Priority_bits_index()
719 *  to properly range between the values returned by the "find first bit"
720 *  instruction.  This makes it possible for _Priority_Get_highest() to
721 *  calculate the major and directly index into the minor table.
722 *  This mapping is necessary to ensure that 0 (a high priority major/minor)
723 *  is the first bit found.
724 *
725 *  This entire "find first bit" and mapping process depends heavily
726 *  on the manner in which a priority is broken into a major and minor
727 *  components with the major being the 4 MSB of a priority and minor
728 *  the 4 LSB.  Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
729 *  priority.  And (15 << 4) + 14 corresponds to priority 254 -- the next
730 *  to the lowest priority.
731 *
732 *  If your CPU does not have a "find first bit" instruction, then
733 *  there are ways to make do without it.  Here are a handful of ways
734 *  to implement this in software:
735 *
736 *    - a series of 16 bit test instructions
737 *    - a "binary search using if's"
738 *    - _number = 0
739 *      if _value > 0x00ff
740 *        _value >>=8
741 *        _number = 8;
742 *
743 *      if _value > 0x0000f
744 *        _value >=8
745 *        _number += 4
746 *
747 *      _number += bit_set_table[ _value ]
748 *
749 *    where bit_set_table[ 16 ] has values which indicate the first
750 *      bit set
751 */
752
753#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
754#define CPU_USE_GENERIC_BITFIELD_DATA TRUE
755
756#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
757
758#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
759  { \
760    (_output) = 0;   /* do something to prevent warnings */ \
761  }
762
763#endif
764
765/* end of Bitfield handler macros */
766
767/*
768 *  This routine builds the mask which corresponds to the bit fields
769 *  as searched by _CPU_Bitfield_Find_first_bit().  See the discussion
770 *  for that routine.
771 */
772
773#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
774
775#define _CPU_Priority_Mask( _bit_number ) \
776  ( 1 << (_bit_number) )
777
778#endif
779
780/*
781 *  This routine translates the bit numbers returned by
782 *  _CPU_Bitfield_Find_first_bit() into something suitable for use as
783 *  a major or minor component of a priority.  See the discussion
784 *  for that routine.
785 */
786
787#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
788
789#define _CPU_Priority_bits_index( _priority ) \
790  (_priority)
791
792#endif
793
794/* end of Priority handler macros */
795
796/* functions */
797
798/*
799 *  _CPU_Initialize
800 *
801 *  This routine performs CPU dependent initialization.
802 */
803
804void _CPU_Initialize(
805  rtems_cpu_table  *cpu_table,
806  void      (*thread_dispatch)
807);
808
809/*
810 *  _CPU_ISR_install_raw_handler
811 *
812 *  This routine installs a "raw" interrupt handler directly into the
813 *  processor's vector table.
814 */
815 
816void _CPU_ISR_install_raw_handler(
817  unsigned32  vector,
818  proc_ptr    new_handler,
819  proc_ptr   *old_handler
820);
821
822/*
823 *  _CPU_ISR_install_vector
824 *
825 *  This routine installs an interrupt vector.
826 */
827
828void _CPU_ISR_install_vector(
829  unsigned32  vector,
830  proc_ptr    new_handler,
831  proc_ptr   *old_handler
832);
833
834/*
835 *  _CPU_Install_interrupt_stack
836 *
837 *  This routine installs the hardware interrupt stack pointer.
838 *
839 *  NOTE:  It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK
840 *         is TRUE.
841 */
842
843void _CPU_Install_interrupt_stack( void );
844
845/*
846 *  _CPU_Internal_threads_Idle_thread_body
847 *
848 *  This routine is the CPU dependent IDLE thread body.
849 *
850 *  NOTE:  It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY
851 *         is TRUE.
852 */
853
854void _CPU_Thread_Idle_body( void );
855
856/*
857 *  _CPU_Context_switch
858 *
859 *  This routine switches from the run context to the heir context.
860 */
861
862void _CPU_Context_switch(
863  Context_Control  *run,
864  Context_Control  *heir
865);
866
867/*
868 *  _CPU_Context_restore
869 *
870 *  This routine is generallu used only to restart self in an
871 *  efficient manner.  It may simply be a label in _CPU_Context_switch.
872 *
873 *  NOTE: May be unnecessary to reload some registers.
874 */
875
876void _CPU_Context_restore(
877  Context_Control *new_context
878);
879
880/*
881 *  _CPU_Context_save_fp
882 *
883 *  This routine saves the floating point context passed to it.
884 */
885
886void _CPU_Context_save_fp(
887  void **fp_context_ptr
888);
889
890/*
891 *  _CPU_Context_restore_fp
892 *
893 *  This routine restores the floating point context passed to it.
894 */
895
896void _CPU_Context_restore_fp(
897  void **fp_context_ptr
898);
899
900/*  The following routine swaps the endian format of an unsigned int.
901 *  It must be static because it is referenced indirectly.
902 *
903 *  This version will work on any processor, but if there is a better
904 *  way for your CPU PLEASE use it.  The most common way to do this is to:
905 *
906 *     swap least significant two bytes with 16-bit rotate
907 *     swap upper and lower 16-bits
908 *     swap most significant two bytes with 16-bit rotate
909 *
910 *  Some CPUs have special instructions which swap a 32-bit quantity in
911 *  a single instruction (e.g. i486).  It is probably best to avoid
912 *  an "endian swapping control bit" in the CPU.  One good reason is
913 *  that interrupts would probably have to be disabled to insure that
914 *  an interrupt does not try to access the same "chunk" with the wrong
915 *  endian.  Another good reason is that on some CPUs, the endian bit
916 *  endianness for ALL fetches -- both code and data -- so the code
917 *  will be fetched incorrectly.
918 */
919 
920static inline unsigned int CPU_swap_u32(
921  unsigned int value
922)
923{
924  unsigned32 byte1, byte2, byte3, byte4, swapped;
925 
926  byte4 = (value >> 24) & 0xff;
927  byte3 = (value >> 16) & 0xff;
928  byte2 = (value >> 8)  & 0xff;
929  byte1 =  value        & 0xff;
930 
931  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
932  return( swapped );
933}
934
935#ifdef __cplusplus
936}
937#endif
938
939#endif
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