source: rtems/c/src/exec/score/cpu/mips/rtems/score/mips.h @ e2040ba

4.104.114.84.95
Last change on this file since e2040ba was e2040ba, checked in by Joel Sherrill <joel.sherrill@…>, on May 22, 2001 at 10:59:42 PM

2001-05-22 Greg Menke <gregory.menke@…>

  • rtems/score/cpu.h: Add the interrupt stack structure and enhance the context initialization to account for floating point tasks.
  • rtems/score/mips.h: Added the routines mips_set_cause(), mips_get_fcr31(), and mips_set_fcr31().
  • Assisted in design and debug by Joel Sherrill <joel@…>.
  • Property mode set to 100644
File size: 3.4 KB
Line 
1/*  mips.h
2 *
3 *  COPYRIGHT (c) 1989-2001.
4 *  On-Line Applications Research Corporation (OAR).
5 *
6 *  The license and distribution terms for this file may be
7 *  found in the file LICENSE in this distribution or at
8 *  http://www.OARcorp.com/rtems/license.html.
9 *
10 *  $Id$
11 */
12/* @(#)mips64orion.h       08/29/96     1.3 */
13
14#ifndef _INCLUDE_MIPS_h
15#define _INCLUDE_MIPS_h
16
17#ifdef __cplusplus
18extern "C" {
19#endif
20
21#ifndef ASM
22#include <idtcpu.h>
23#endif
24
25/*
26 *  SR bits that enable/disable interrupts
27 *
28 *  NOTE: XXX what about SR_ERL?
29 */
30
31#if __mips == 3
32#ifdef ASM
33#define SR_INTERRUPT_ENABLE_BITS 0x01
34#else
35#define SR_INTERRUPT_ENABLE_BITS SR_IE
36#endif
37
38#elif __mips == 1
39#define SR_INTERRUPT_ENABLE_BITS SR_IEC
40
41#else
42#error "mips interrupt enable bits: unknown architecture level!"
43#endif
44
45/*
46 *  This file contains the information required to build
47 *  RTEMS for a particular member of the "no cpu"
48 *  family when executing in protected mode.  It does
49 *  this by setting variables to indicate which implementation
50 *  dependent features are present in a particular member
51 *  of the family.
52 */
53 
54#if defined(__mips_soft_float)
55#define MIPS_HAS_FPU 0
56#else
57#define MIPS_HAS_FPU 1
58#endif
59
60#if (__mips == 1)
61#define CPU_MODEL_NAME  "ISA Level 1 or 2"
62#elif (__mips == 3)
63#if defined(__mips64)
64#define CPU_MODEL_NAME  "ISA Level 4"
65#else
66#define CPU_MODEL_NAME  "ISA Level 3"
67#endif
68#else
69#error "Unknown MIPS ISA level"
70#endif
71
72/*
73 *  Define the name of the CPU family.
74 */
75
76#define CPU_NAME "MIPS"
77
78/*
79 *  Some macros to access registers
80 */
81
82#define mips_get_sr( _x ) \
83  do { \
84    asm volatile( "mfc0 %0, $12; nop" : "=r" (_x) : ); \
85  } while (0)
86
87#define mips_set_sr( _x ) \
88  do { \
89    register unsigned int __x = (_x); \
90    asm volatile( "mtc0 %0, $12; nop" : : "r" (__x) ); \
91  } while (0)
92
93
94
95
96
97#define mips_get_cause( _x ) \
98  do { \
99    asm volatile( "mfc0 %0, $13; nop" : "=r" (_x) : ); \
100  } while (0)
101
102
103#define mips_set_cause( _x ) \
104  do { \
105    register unsigned int __x = (_x); \
106    asm volatile( "mtc0 %0, $13; nop" : : "r" (__x) ); \
107  } while (0)
108
109
110
111
112
113#define mips_get_fcr31( _x ) \
114  do { \
115    asm volatile( "cfc1 %0, $31; nop" : "=r" (_x) : ); \
116  } while(0)
117
118
119#define mips_set_fcr31( _x ) \
120  do { \
121    register unsigned int __x = (_x); \
122    asm volatile( "ctc1 %0, $31; nop" : : "r" (__x) ); \
123  } while(0)
124
125
126
127
128
129/*
130 *  Manipulate interrupt mask
131 *
132 *  mips_unmask_interrupt( _mask)
133 *    enables interrupts - mask is positioned so it only needs to be or'ed
134 *    into the status reg. This also does some other things !!!! Caution
135 *    should be used if invoking this while in the middle of a debugging
136 *    session where the client may have nested interrupts.
137 *
138 *  mips_mask_interrupt( _mask )
139 *    disable the interrupt - mask is the complement of the bits to be
140 *    cleared - i.e. to clear ext int 5 the mask would be - 0xffff7fff
141 *
142 *
143 *  NOTE: mips_mask_interrupt() used to be disable_int().
144 *        mips_unmask_interrupt() used to be enable_int().
145 *
146 */
147
148#define mips_enable_in_interrupt_mask( _mask ) \
149  do { \
150    unsigned int _sr; \
151    mips_get_sr( _sr ); \
152    _sr |= (_mask); \
153    mips_set_sr( _sr ); \
154  } while (0)
155
156#define mips_disable_in_interrupt_mask( _mask ) \
157  do { \
158    unsigned int _sr; \
159    mips_get_sr( _sr ); \
160    _sr &= ~(_mask); \
161    mips_set_sr( _sr ); \
162  } while (0)
163
164#ifdef __cplusplus
165}
166#endif
167
168#endif /* ! _INCLUDE_MIPS_h */
169/* end of include file */
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