1 | /* mips.h |
---|
2 | * |
---|
3 | * COPYRIGHT (c) 1989-2001. |
---|
4 | * On-Line Applications Research Corporation (OAR). |
---|
5 | * |
---|
6 | * The license and distribution terms for this file may be |
---|
7 | * found in the file LICENSE in this distribution or at |
---|
8 | * http://www.OARcorp.com/rtems/license.html. |
---|
9 | * |
---|
10 | * $Id$ |
---|
11 | */ |
---|
12 | /* @(#)mips64orion.h 08/29/96 1.3 */ |
---|
13 | |
---|
14 | #ifndef _INCLUDE_MIPS_h |
---|
15 | #define _INCLUDE_MIPS_h |
---|
16 | |
---|
17 | #ifdef __cplusplus |
---|
18 | extern "C" { |
---|
19 | #endif |
---|
20 | |
---|
21 | #ifndef ASM |
---|
22 | #include <idtcpu.h> |
---|
23 | #endif |
---|
24 | |
---|
25 | /* |
---|
26 | * SR bits that enable/disable interrupts |
---|
27 | * |
---|
28 | * NOTE: XXX what about SR_ERL? |
---|
29 | */ |
---|
30 | |
---|
31 | #if __mips == 3 |
---|
32 | #ifdef ASM |
---|
33 | #define SR_INTERRUPT_ENABLE_BITS 0x01 |
---|
34 | #else |
---|
35 | #define SR_INTERRUPT_ENABLE_BITS SR_IE |
---|
36 | #endif |
---|
37 | |
---|
38 | #elif __mips == 1 |
---|
39 | #define SR_INTERRUPT_ENABLE_BITS SR_IEC |
---|
40 | |
---|
41 | #else |
---|
42 | #error "mips interrupt enable bits: unknown architecture level!" |
---|
43 | #endif |
---|
44 | |
---|
45 | /* |
---|
46 | * This file contains the information required to build |
---|
47 | * RTEMS for a particular member of the "no cpu" |
---|
48 | * family when executing in protected mode. It does |
---|
49 | * this by setting variables to indicate which implementation |
---|
50 | * dependent features are present in a particular member |
---|
51 | * of the family. |
---|
52 | */ |
---|
53 | |
---|
54 | #if defined(__mips_soft_float) |
---|
55 | #define MIPS_HAS_FPU 0 |
---|
56 | #else |
---|
57 | #define MIPS_HAS_FPU 1 |
---|
58 | #endif |
---|
59 | |
---|
60 | #if (__mips == 1) |
---|
61 | #define CPU_MODEL_NAME "ISA Level 1 or 2" |
---|
62 | #elif (__mips == 3) |
---|
63 | #if defined(__mips64) |
---|
64 | #define CPU_MODEL_NAME "ISA Level 4" |
---|
65 | #else |
---|
66 | #define CPU_MODEL_NAME "ISA Level 3" |
---|
67 | #endif |
---|
68 | #else |
---|
69 | #error "Unknown MIPS ISA level" |
---|
70 | #endif |
---|
71 | |
---|
72 | /* |
---|
73 | * Define the name of the CPU family. |
---|
74 | */ |
---|
75 | |
---|
76 | #define CPU_NAME "MIPS" |
---|
77 | |
---|
78 | /* |
---|
79 | * Some macros to access registers |
---|
80 | */ |
---|
81 | |
---|
82 | #define mips_get_sr( _x ) \ |
---|
83 | do { \ |
---|
84 | asm volatile( "mfc0 %0, $12; nop" : "=r" (_x) : ); \ |
---|
85 | } while (0) |
---|
86 | |
---|
87 | #define mips_set_sr( _x ) \ |
---|
88 | do { \ |
---|
89 | register unsigned int __x = (_x); \ |
---|
90 | asm volatile( "mtc0 %0, $12; nop" : : "r" (__x) ); \ |
---|
91 | } while (0) |
---|
92 | |
---|
93 | /* |
---|
94 | * Manipulate interrupt mask |
---|
95 | * |
---|
96 | * mips_unmask_interrupt( _mask) |
---|
97 | * enables interrupts - mask is positioned so it only needs to be or'ed |
---|
98 | * into the status reg. This also does some other things !!!! Caution |
---|
99 | * should be used if invoking this while in the middle of a debugging |
---|
100 | * session where the client may have nested interrupts. |
---|
101 | * |
---|
102 | * mips_mask_interrupt( _mask ) |
---|
103 | * disable the interrupt - mask is the complement of the bits to be |
---|
104 | * cleared - i.e. to clear ext int 5 the mask would be - 0xffff7fff |
---|
105 | * |
---|
106 | * |
---|
107 | * NOTE: mips_mask_interrupt() used to be disable_int(). |
---|
108 | * mips_unmask_interrupt() used to be enable_int(). |
---|
109 | * |
---|
110 | */ |
---|
111 | |
---|
112 | #define mips_enable_in_interrupt_mask( _mask ) \ |
---|
113 | do { \ |
---|
114 | unsigned int _sr; \ |
---|
115 | mips_get_sr( _sr ); \ |
---|
116 | _sr |= (_mask); \ |
---|
117 | mips_set_sr( _sr ); \ |
---|
118 | } while (0) |
---|
119 | |
---|
120 | #define mips_disable_in_interrupt_mask( _mask ) \ |
---|
121 | do { \ |
---|
122 | unsigned int _sr; \ |
---|
123 | mips_get_sr( _sr ); \ |
---|
124 | _sr &= ~(_mask); \ |
---|
125 | mips_set_sr( _sr ); \ |
---|
126 | } while (0) |
---|
127 | |
---|
128 | #ifdef __cplusplus |
---|
129 | } |
---|
130 | #endif |
---|
131 | |
---|
132 | #endif /* ! _INCLUDE_MIPS_h */ |
---|
133 | /* end of include file */ |
---|